Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22898

1

T1

26

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3159

1

T3

20

T7

11

T20

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19955

1

T1

1

T3

40

T5

28

auto[1]

6102

1

T1

25

T2

8

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T312	17		T313	7		T314	1
values[0]	107	1			T39	19		T226	8		T315	1
values[1]	668	1			T5	23		T26	1		T58	1
values[2]	742	1			T1	1		T22	25		T120	7
values[3]	696	1			T1	17		T5	1		T10	1
values[4]	2906	1			T2	8		T4	1		T6	39
values[5]	684	1			T7	11		T36	11		T142	18
values[6]	692	1			T3	20		T20	4		T11	7
values[7]	634	1			T1	8		T8	8		T223	46
values[8]	722	1			T5	27		T7	2		T8	3
values[9]	1148	1			T3	20		T8	17		T22	13
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1003	1			T1	1		T5	23		T22	25
values[1]	857	1			T1	17		T89	4		T120	7
values[2]	594	1			T5	1		T8	27		T10	1
values[3]	2773	1			T2	8		T4	1		T6	39
values[4]	690	1			T11	7		T36	11		T137	6
values[5]	745	1			T3	20		T8	8		T20	4
values[6]	743	1			T1	8		T7	1		T10	1
values[7]	572	1			T7	1		T8	3		T90	1
values[8]	822	1			T3	20		T5	27		T8	17
values[9]	220	1			T207	11		T161	1		T148	1
minimum	17038	1			T8	297		T25	107		T37	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T1	1		T5	12		T39	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T22	15		T26	1		T58	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T1	17		T120	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T89	1		T47	5		T122	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T8	6		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T142	1		T225	1		T33	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1575	1			T2	1		T4	1		T6	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	1		T137	1		T127	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T128	4		T151	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	4		T36	11		T137	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	4		T185	12		T186	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	12		T20	4		T121	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	8		T7	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T223	12		T124	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	1		T8	1		T227	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T90	1		T120	1		T36	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T3	10		T5	14		T8	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T22	6		T227	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T161	1		T164	1		T312	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T207	1		T148	1		T244	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16900	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T135	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	11		T39	8		T12	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T22	10		T144	10		T234	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T120	6		T142	1		T224	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T89	3		T122	21		T254	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	21		T22	17		T120	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T142	1		T33	21		T288	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	927	1			T2	7		T9	10		T20	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	10		T137	1		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T128	4		T151	7		T225	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	3		T143	8		T228	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	4		T186	9		T229	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	8		T121	13		T142	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T152	10		T235	10		T28	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T223	6		T144	9		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T8	2		T234	11		T134	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T120	9		T233	17		T231	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	10		T5	13		T8	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T22	7		T192	10		T32	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T164	15		T312	7		T316	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T207	10		T155	2		T301	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	1		T58	1		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T312	10		T313	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T314	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T39	11		T226	1		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T315	1		T157	9		T267	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	12		T223	1		T123	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T26	1		T58	1		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T120	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	15		T47	5		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	17		T5	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T89	1		T122	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1648	1			T2	1		T4	1		T6	39
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T142	1		T137	1		T33	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T128	4		T125	1		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	1		T36	11		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T151	1		T186	16		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	12		T20	4		T11	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	8		T8	4		T185	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T223	26		T124	1		T144	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	14		T7	2		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T120	1		T36	8		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T3	10		T8	15		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T22	6		T90	1		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T312	7		T313	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T39	8		T226	7		T159	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T267	12		T317	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	11		T223	3		T123	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T144	10		T234	12		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T120	6		T142	1		T12	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T22	10		T122	13		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T22	17		T224	12		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T89	3		T122	8		T143	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T2	7		T8	21		T9	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T142	1		T137	1		T33	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T128	4		T125	6		T225	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	10		T142	7		T13	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T151	7		T186	9		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	8		T11	3		T121	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	4		T229	6		T221	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T223	20		T144	9		T253	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	13		T8	2		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T120	9		T233	17		T258	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T3	10		T8	2		T121	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T22	7		T207	10		T192	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T1	1		T5	12		T39	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T22	11		T26	1		T58	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T1	1		T120	7		T142	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T89	4		T47	1		T122	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T8	24		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	2		T225	1		T33	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T2	8		T4	1		T6	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	11		T137	2		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T128	5		T151	8		T225	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	5		T36	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T8	7		T185	1		T186	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	9		T20	1		T121	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T7	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T223	7		T124	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	1		T8	3		T227	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T90	1		T120	10		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T3	11		T5	14		T8	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T22	8		T227	1		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T161	1		T164	16		T312	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T207	11		T148	1		T244	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17037	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T135	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	11		T39	10		T12	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T22	14		T144	9		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T1	16		T224	11		T271	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T47	4		T163	10		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	3		T22	13		T209	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T33	4		T269	12		T288	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T6	36		T20	8		T21	40
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T127	9		T143	13		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T128	3		T146	6		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	2		T36	10		T137	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	1		T185	11		T186	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	11		T20	3		T121	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	7		T36	14		T152	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T223	11		T144	7		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	14		T134	2		T135	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T36	7		T233	10		T291	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	9		T5	13		T8	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T22	5		T32	6		T235	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T312	9		T316	19		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T244	14		T155	2		T301	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T312	8		T313	7		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T314	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T39	9		T226	8		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T315	1		T157	1		T267	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	12		T223	4		T123	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T26	1		T58	1		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	1		T120	7		T142	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T22	11		T47	1		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T5	1		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T89	4		T122	9		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T2	8		T4	1		T6	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T142	2		T137	2		T33	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T128	5		T125	7		T225	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	11		T36	1		T142	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T151	8		T186	10		T229	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	9		T20	1		T11	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T8	7		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T223	22		T124	1		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	14		T7	2		T8	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T120	10		T36	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T3	11		T8	3		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T22	8		T90	1		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T312	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T39	10		T170	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T157	8		T267	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	11		T123	9		T233	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T144	9		T35	1		T278	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	3		T271	6		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	14		T47	4		T163	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	16		T22	13		T224	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T143	13		T288	9		T149	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T6	36		T8	3		T20	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T33	4		T35	2		T230	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T128	3		T152	10		T177	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T36	10		T142	10		T137	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T186	15		T240	7		T233	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	11		T20	3		T11	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	7		T8	1		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T223	24		T144	7		T253	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	13		T36	14		T146	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T36	7		T233	10		T291	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T3	9		T8	14		T121	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T22	5		T32	6		T235	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24