Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20253

1

T1

17

T3

20

T5

51

auto[ADC_CTRL_FILTER_COND_OUT]

5804

1

T1

9

T2

8

T3

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20063

1

T1

9

T5

24

T7

1

auto[1]

5994

1

T1

17

T2

8

T3

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T318	23		-	-		-	-
values[0]	100	1			T8	27		T16	5		T164	3
values[1]	478	1			T1	1		T5	23		T22	25
values[2]	734	1			T7	1		T10	1		T36	8
values[3]	746	1			T5	27		T8	8		T26	1
values[4]	726	1			T1	17		T7	1		T22	13
values[5]	693	1			T3	40		T5	1		T20	17
values[6]	600	1			T20	4		T142	2		T247	1
values[7]	836	1			T8	20		T10	1		T227	1
values[8]	637	1			T7	11		T89	4		T120	10
values[9]	3451	1			T1	8		T2	8		T4	1
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	801	1			T1	1		T5	23		T8	27
values[1]	2887	1			T2	8		T4	1		T6	39
values[2]	613	1			T5	27		T8	8		T26	1
values[3]	820	1			T1	17		T5	1		T7	1
values[4]	633	1			T3	20		T36	11		T207	11
values[5]	660	1			T3	20		T10	1		T20	21
values[6]	769	1			T8	20		T120	10		T121	22
values[7]	646	1			T7	11		T89	4		T121	24
values[8]	991	1			T22	31		T11	7		T209	8
values[9]	189	1			T1	8		T128	8		T319	1
minimum	17048	1			T8	297		T25	107		T37	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	12		T8	6		T120	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T22	15		T58	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T36	8		T138	1		T125	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1670	1			T2	1		T4	1		T6	39
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	14		T120	1		T136	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	4		T26	1		T36	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	17		T5	1		T22	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T7	1		T227	1		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T207	1		T124	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	10		T36	11		T142	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	12		T20	13		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	1		T238	3		T230	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T223	14		T30	2		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T8	16		T120	1		T121	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T7	1		T89	1		T186	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T121	12		T161	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T11	4		T209	3		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T22	14		T151	1		T143	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T319	1		T180	14		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T1	8		T128	4		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T143	6		T274	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	11		T8	21		T120	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T22	10		T137	1		T12	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T125	6		T230	7		T280	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	983	1			T2	7		T9	10		T23	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	13		T120	10		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T8	4		T320	3		T66	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T22	7		T137	12		T122	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T122	8		T123	8		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T207	10		T225	9		T35	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	10		T142	7		T122	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	8		T20	8		T142	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T230	10		T235	10		T231	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T223	14		T234	12		T228	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	4		T120	9		T121	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	10		T89	3		T186	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T121	12		T223	3		T31	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T11	3		T209	5		T177	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T22	17		T151	7		T143	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T180	2		T277	11		T316	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T128	4		T169	1		T321	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T143	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T318	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T8	6		T16	3		T164	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T322	1		T267	11		T323	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	12		T120	1		T121	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	1		T22	15		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	8		T207	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	1		T10	1		T58	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	14		T136	10		T223	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T8	4		T26	1		T36	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	17		T22	6		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	1		T227	1		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	12		T5	1		T20	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	10		T36	11		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T20	4		T142	1		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T247	1		T122	1		T238	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T227	1		T223	14		T249	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T8	16		T10	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	1		T89	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T120	1		T121	21		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	391	1			T11	4		T209	3		T186	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1666	1			T1	8		T2	1		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T318	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T8	21		T16	2		T164	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T322	13		T267	12		T323	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	11		T120	6		T121	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T22	10		T137	1		T12	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T123	2		T125	6		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T224	12		T233	6		T133	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T5	13		T136	10		T223	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	4		T32	7		T134	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T22	7		T120	10		T137	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T123	8		T32	4		T257	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	8		T20	8		T207	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	10		T142	7		T122	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T142	1		T192	10		T228	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T122	13		T230	10		T254	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T223	14		T234	12		T235	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	4		T142	1		T32	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	10		T89	3		T33	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T120	9		T121	25		T223	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T11	3		T209	5		T186	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1080	1			T2	7		T9	10		T22	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	12		T8	24		T120	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	1		T22	11		T58	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T36	1		T138	1		T125	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1327	1			T2	8		T4	1		T6	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	14		T120	11		T136	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	7		T26	1		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	1		T5	1		T22	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	1		T227	1		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T207	11		T124	1		T225	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	11		T36	1		T142	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	9		T20	10		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	1		T238	1		T230	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T223	15		T30	2		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T8	6		T120	10		T121	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	11		T89	4		T186	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T121	13		T161	1		T223	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T11	5		T209	6		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T22	18		T151	8		T143	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T319	1		T180	3		T277	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T1	1		T128	5		T169	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T143	9		T274	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	11		T8	3		T121	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T22	14		T12	3		T240	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T36	7		T230	5		T296	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1326	1			T6	36		T21	40		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	13		T136	9		T223	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	1		T36	14		T137	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	16		T22	5		T137	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T47	4		T185	11		T123	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T35	5		T71	16		T324	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	9		T36	10		T142	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	11		T20	11		T127	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T238	2		T230	10		T149	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T223	13		T228	12		T152	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	14		T121	8		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T186	15		T33	4		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T121	11		T229	5		T270	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	2		T209	2		T177	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T22	13		T143	13		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T180	13		T325	9		T326	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T1	7		T128	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T143	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T318	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T8	24		T16	4		T164	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T322	14		T267	13		T323	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	12		T120	7		T121	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T22	11		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T36	1		T207	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	1		T10	1		T58	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	14		T136	11		T223	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	7		T26	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T22	8		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	1		T227	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	9		T5	1		T20	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	11		T36	1		T142	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T20	1		T142	2		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T247	1		T122	14		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T227	1		T223	15		T249	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	6		T10	1		T142	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	11		T89	4		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T120	10		T121	27		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T11	5		T209	6		T186	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1440	1			T1	1		T2	8		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T318	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T8	3		T16	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T267	10		T323	1		T327	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T5	11		T121	11		T39	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T22	14		T12	3		T240	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T36	7		T123	12		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T224	11		T233	1		T146	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	13		T136	9		T223	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	1		T36	14		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	16		T22	5		T137	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T47	4		T137	5		T127	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T3	11		T20	8		T127	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	9		T36	10		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T20	3		T228	12		T146	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T238	2		T230	10		T149	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T223	13		T235	4		T261	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T8	14		T32	6		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T33	4		T144	9		T271	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T121	19		T229	5		T253	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T11	2		T209	2		T186	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1306	1			T1	7		T6	36		T21	40

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24