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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.34


Total test records in report: 919
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T796 /workspace/coverage/default/9.adc_ctrl_clock_gating.112262321 Apr 15 12:51:19 PM PDT 24 Apr 15 12:59:57 PM PDT 24 501685039274 ps
T797 /workspace/coverage/default/0.adc_ctrl_poweron_counter.3740256452 Apr 15 12:50:33 PM PDT 24 Apr 15 12:50:47 PM PDT 24 5187959561 ps
T798 /workspace/coverage/default/43.adc_ctrl_stress_all.3063626952 Apr 15 12:55:57 PM PDT 24 Apr 15 01:05:56 PM PDT 24 577382247271 ps
T799 /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.97302209 Apr 15 12:53:19 PM PDT 24 Apr 15 12:57:34 PM PDT 24 196894066906 ps
T75 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1015241598 Apr 15 03:28:50 PM PDT 24 Apr 15 03:28:52 PM PDT 24 606773425 ps
T51 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2111584481 Apr 15 03:28:17 PM PDT 24 Apr 15 03:28:20 PM PDT 24 356961110 ps
T800 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.501916824 Apr 15 03:28:20 PM PDT 24 Apr 15 03:28:22 PM PDT 24 356180667 ps
T801 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1209116715 Apr 15 03:28:27 PM PDT 24 Apr 15 03:28:29 PM PDT 24 362719978 ps
T46 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.261860853 Apr 15 03:28:05 PM PDT 24 Apr 15 03:28:07 PM PDT 24 2474901875 ps
T43 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1417052548 Apr 15 03:27:43 PM PDT 24 Apr 15 03:28:17 PM PDT 24 51989321629 ps
T48 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.676226766 Apr 15 03:27:45 PM PDT 24 Apr 15 03:27:58 PM PDT 24 8471748068 ps
T802 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2274435867 Apr 15 03:28:15 PM PDT 24 Apr 15 03:28:16 PM PDT 24 589799370 ps
T803 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3999872985 Apr 15 03:28:01 PM PDT 24 Apr 15 03:28:03 PM PDT 24 492083198 ps
T804 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.91845707 Apr 15 03:27:48 PM PDT 24 Apr 15 03:27:50 PM PDT 24 472576360 ps
T52 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4282265515 Apr 15 03:28:01 PM PDT 24 Apr 15 03:28:05 PM PDT 24 856359335 ps
T49 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1753265714 Apr 15 03:28:17 PM PDT 24 Apr 15 03:28:30 PM PDT 24 8275164467 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1768113589 Apr 15 03:27:48 PM PDT 24 Apr 15 03:27:50 PM PDT 24 481661408 ps
T44 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2123796185 Apr 15 03:27:45 PM PDT 24 Apr 15 03:28:37 PM PDT 24 42304381939 ps
T805 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3385527177 Apr 15 03:28:25 PM PDT 24 Apr 15 03:28:26 PM PDT 24 454357555 ps
T45 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2553499709 Apr 15 03:28:14 PM PDT 24 Apr 15 03:28:20 PM PDT 24 4909062121 ps
T50 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3770646779 Apr 15 03:27:49 PM PDT 24 Apr 15 03:27:56 PM PDT 24 9211117523 ps
T806 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4166582794 Apr 15 03:28:11 PM PDT 24 Apr 15 03:28:13 PM PDT 24 366543412 ps
T807 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1186223371 Apr 15 03:28:21 PM PDT 24 Apr 15 03:28:24 PM PDT 24 318559883 ps
T59 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.4254890129 Apr 15 03:28:19 PM PDT 24 Apr 15 03:28:23 PM PDT 24 4873940596 ps
T91 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1710940661 Apr 15 03:27:50 PM PDT 24 Apr 15 03:27:53 PM PDT 24 657315389 ps
T808 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.168098269 Apr 15 03:27:58 PM PDT 24 Apr 15 03:28:01 PM PDT 24 466469475 ps
T56 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2262944415 Apr 15 03:27:56 PM PDT 24 Apr 15 03:28:00 PM PDT 24 426609144 ps
T809 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1977581945 Apr 15 03:28:19 PM PDT 24 Apr 15 03:28:22 PM PDT 24 361390924 ps
T810 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1429911096 Apr 15 03:28:23 PM PDT 24 Apr 15 03:28:25 PM PDT 24 446139912 ps
T105 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1822862441 Apr 15 03:28:13 PM PDT 24 Apr 15 03:28:16 PM PDT 24 374455460 ps
T811 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1746603201 Apr 15 03:28:22 PM PDT 24 Apr 15 03:28:24 PM PDT 24 541053814 ps
T62 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3655415029 Apr 15 03:28:10 PM PDT 24 Apr 15 03:28:12 PM PDT 24 522945152 ps
T57 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1586667763 Apr 15 03:27:46 PM PDT 24 Apr 15 03:27:49 PM PDT 24 428513420 ps
T812 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1217637268 Apr 15 03:28:12 PM PDT 24 Apr 15 03:28:14 PM PDT 24 333541838 ps
T813 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1439260749 Apr 15 03:28:23 PM PDT 24 Apr 15 03:28:24 PM PDT 24 374599716 ps
T76 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1428528507 Apr 15 03:28:20 PM PDT 24 Apr 15 03:28:22 PM PDT 24 570016390 ps
T112 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4067143522 Apr 15 03:27:56 PM PDT 24 Apr 15 03:27:59 PM PDT 24 753413512 ps
T92 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1647716546 Apr 15 03:27:43 PM PDT 24 Apr 15 03:27:45 PM PDT 24 1234393384 ps
T77 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.186741257 Apr 15 03:28:19 PM PDT 24 Apr 15 03:28:23 PM PDT 24 553291073 ps
T113 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.969651904 Apr 15 03:27:49 PM PDT 24 Apr 15 03:28:06 PM PDT 24 26336513841 ps
T814 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.720878891 Apr 15 03:28:28 PM PDT 24 Apr 15 03:28:30 PM PDT 24 352761762 ps
T78 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4117585959 Apr 15 03:28:06 PM PDT 24 Apr 15 03:28:08 PM PDT 24 382588163 ps
T815 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2497477944 Apr 15 03:28:01 PM PDT 24 Apr 15 03:28:04 PM PDT 24 395165680 ps
T816 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1755198653 Apr 15 03:27:54 PM PDT 24 Apr 15 03:27:58 PM PDT 24 1025709061 ps
T93 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3054422801 Apr 15 03:27:52 PM PDT 24 Apr 15 03:27:54 PM PDT 24 366097825 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2356308045 Apr 15 03:28:08 PM PDT 24 Apr 15 03:28:12 PM PDT 24 668688597 ps
T106 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3544444351 Apr 15 03:28:20 PM PDT 24 Apr 15 03:28:23 PM PDT 24 2360513217 ps
T818 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3946492021 Apr 15 03:28:25 PM PDT 24 Apr 15 03:28:27 PM PDT 24 420362202 ps
T819 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.131867924 Apr 15 03:28:06 PM PDT 24 Apr 15 03:28:09 PM PDT 24 678365836 ps
T107 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3405914700 Apr 15 03:27:56 PM PDT 24 Apr 15 03:28:12 PM PDT 24 3924762154 ps
T108 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3531872199 Apr 15 03:28:00 PM PDT 24 Apr 15 03:28:05 PM PDT 24 4946594312 ps
T109 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.942751857 Apr 15 03:28:06 PM PDT 24 Apr 15 03:28:26 PM PDT 24 4543167892 ps
T820 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1460900586 Apr 15 03:28:10 PM PDT 24 Apr 15 03:28:12 PM PDT 24 398081021 ps
T110 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2032782864 Apr 15 03:27:57 PM PDT 24 Apr 15 03:28:00 PM PDT 24 4195226716 ps
T821 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4021170013 Apr 15 03:28:12 PM PDT 24 Apr 15 03:28:14 PM PDT 24 305691876 ps
T94 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2596114158 Apr 15 03:27:47 PM PDT 24 Apr 15 03:27:51 PM PDT 24 1369762941 ps
T822 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2791333199 Apr 15 03:28:23 PM PDT 24 Apr 15 03:28:25 PM PDT 24 357752805 ps
T823 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1013926865 Apr 15 03:28:29 PM PDT 24 Apr 15 03:28:31 PM PDT 24 484300775 ps
T824 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.276873347 Apr 15 03:27:49 PM PDT 24 Apr 15 03:27:51 PM PDT 24 595979386 ps
T95 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3777147884 Apr 15 03:27:49 PM PDT 24 Apr 15 03:27:51 PM PDT 24 490772015 ps
T63 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3914370169 Apr 15 03:28:06 PM PDT 24 Apr 15 03:28:14 PM PDT 24 8129037708 ps
T825 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3180737854 Apr 15 03:28:25 PM PDT 24 Apr 15 03:28:27 PM PDT 24 440810082 ps
T826 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3789006407 Apr 15 03:28:28 PM PDT 24 Apr 15 03:28:30 PM PDT 24 340894053 ps
T827 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4050722383 Apr 15 03:27:59 PM PDT 24 Apr 15 03:28:10 PM PDT 24 26688824804 ps
T828 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3100298632 Apr 15 03:28:00 PM PDT 24 Apr 15 03:28:07 PM PDT 24 4717656743 ps
T96 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.980504881 Apr 15 03:27:46 PM PDT 24 Apr 15 03:27:49 PM PDT 24 1174139897 ps
T829 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2718478563 Apr 15 03:28:22 PM PDT 24 Apr 15 03:28:25 PM PDT 24 512325853 ps
T830 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.349060114 Apr 15 03:27:49 PM PDT 24 Apr 15 03:27:51 PM PDT 24 701047970 ps
T831 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.196027093 Apr 15 03:28:18 PM PDT 24 Apr 15 03:28:19 PM PDT 24 441853630 ps
T832 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1264927139 Apr 15 03:27:58 PM PDT 24 Apr 15 03:28:01 PM PDT 24 412897372 ps
T351 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1393394032 Apr 15 03:27:53 PM PDT 24 Apr 15 03:28:06 PM PDT 24 8244719697 ps
T833 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3899572343 Apr 15 03:28:15 PM PDT 24 Apr 15 03:28:17 PM PDT 24 590940647 ps
T834 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4082221532 Apr 15 03:28:15 PM PDT 24 Apr 15 03:28:17 PM PDT 24 453379521 ps
T835 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2932057449 Apr 15 03:28:21 PM PDT 24 Apr 15 03:28:23 PM PDT 24 323929095 ps
T836 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3649707174 Apr 15 03:28:26 PM PDT 24 Apr 15 03:28:28 PM PDT 24 380165943 ps
T97 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2076936427 Apr 15 03:28:09 PM PDT 24 Apr 15 03:28:11 PM PDT 24 509085177 ps
T837 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3915866417 Apr 15 03:28:22 PM PDT 24 Apr 15 03:28:23 PM PDT 24 484407616 ps
T838 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1028122671 Apr 15 03:28:05 PM PDT 24 Apr 15 03:28:12 PM PDT 24 4717826307 ps
T839 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.691309826 Apr 15 03:27:56 PM PDT 24 Apr 15 03:28:02 PM PDT 24 2561694272 ps
T840 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3159638416 Apr 15 03:27:41 PM PDT 24 Apr 15 03:27:43 PM PDT 24 352021426 ps
T841 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2339924954 Apr 15 03:27:50 PM PDT 24 Apr 15 03:27:51 PM PDT 24 764078355 ps
T842 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2269709693 Apr 15 03:28:23 PM PDT 24 Apr 15 03:28:25 PM PDT 24 387894863 ps
T843 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.730864079 Apr 15 03:28:05 PM PDT 24 Apr 15 03:28:09 PM PDT 24 533602518 ps
T844 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2460536912 Apr 15 03:27:48 PM PDT 24 Apr 15 03:27:52 PM PDT 24 4947054598 ps
T845 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3653362063 Apr 15 03:28:10 PM PDT 24 Apr 15 03:28:13 PM PDT 24 577616946 ps
T846 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1753574858 Apr 15 03:28:22 PM PDT 24 Apr 15 03:28:24 PM PDT 24 543166930 ps
T847 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.482321060 Apr 15 03:28:09 PM PDT 24 Apr 15 03:28:13 PM PDT 24 554742354 ps
T848 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.790343767 Apr 15 03:27:42 PM PDT 24 Apr 15 03:27:44 PM PDT 24 2322728973 ps
T849 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1636952902 Apr 15 03:28:10 PM PDT 24 Apr 15 03:28:13 PM PDT 24 598419093 ps
T850 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3169104631 Apr 15 03:28:10 PM PDT 24 Apr 15 03:28:12 PM PDT 24 364089718 ps
T851 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1683263654 Apr 15 03:28:10 PM PDT 24 Apr 15 03:28:16 PM PDT 24 4188884885 ps
T852 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2863742242 Apr 15 03:27:57 PM PDT 24 Apr 15 03:28:00 PM PDT 24 532584396 ps
T853 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2935625766 Apr 15 03:27:48 PM PDT 24 Apr 15 03:27:50 PM PDT 24 528058016 ps
T854 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3288508418 Apr 15 03:28:26 PM PDT 24 Apr 15 03:28:29 PM PDT 24 411101491 ps
T855 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2747226614 Apr 15 03:28:04 PM PDT 24 Apr 15 03:28:07 PM PDT 24 735975770 ps
T98 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2679476137 Apr 15 03:27:51 PM PDT 24 Apr 15 03:27:54 PM PDT 24 364349029 ps
T856 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1479974024 Apr 15 03:28:05 PM PDT 24 Apr 15 03:28:06 PM PDT 24 341464037 ps
T857 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1020591182 Apr 15 03:28:01 PM PDT 24 Apr 15 03:28:04 PM PDT 24 453847077 ps
T858 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1158294037 Apr 15 03:28:25 PM PDT 24 Apr 15 03:28:26 PM PDT 24 386647167 ps
T859 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2833674355 Apr 15 03:27:44 PM PDT 24 Apr 15 03:27:46 PM PDT 24 390781174 ps
T860 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3152132651 Apr 15 03:28:14 PM PDT 24 Apr 15 03:28:22 PM PDT 24 2764006266 ps
T861 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.793973024 Apr 15 03:28:06 PM PDT 24 Apr 15 03:28:08 PM PDT 24 696291122 ps
T862 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1021012628 Apr 15 03:28:09 PM PDT 24 Apr 15 03:28:31 PM PDT 24 8178732185 ps
T863 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1906001257 Apr 15 03:28:01 PM PDT 24 Apr 15 03:28:03 PM PDT 24 332055906 ps
T864 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1156941630 Apr 15 03:27:56 PM PDT 24 Apr 15 03:28:05 PM PDT 24 8511014004 ps
T865 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1889192626 Apr 15 03:28:10 PM PDT 24 Apr 15 03:28:14 PM PDT 24 414129357 ps
T866 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1588756220 Apr 15 03:27:51 PM PDT 24 Apr 15 03:27:53 PM PDT 24 284966052 ps
T867 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4165765927 Apr 15 03:28:00 PM PDT 24 Apr 15 03:28:02 PM PDT 24 659163894 ps
T868 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2276633738 Apr 15 03:28:13 PM PDT 24 Apr 15 03:28:16 PM PDT 24 554226080 ps
T869 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.310437832 Apr 15 03:28:09 PM PDT 24 Apr 15 03:28:12 PM PDT 24 570385858 ps
T870 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.770477449 Apr 15 03:27:46 PM PDT 24 Apr 15 03:27:52 PM PDT 24 2027777329 ps
T871 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.797160886 Apr 15 03:28:14 PM PDT 24 Apr 15 03:28:17 PM PDT 24 479891196 ps
T872 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.86831243 Apr 15 03:27:58 PM PDT 24 Apr 15 03:27:59 PM PDT 24 288387556 ps
T873 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3345801034 Apr 15 03:28:04 PM PDT 24 Apr 15 03:28:14 PM PDT 24 2211481613 ps
T874 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.249411309 Apr 15 03:28:05 PM PDT 24 Apr 15 03:28:28 PM PDT 24 8437310539 ps
T875 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4045246810 Apr 15 03:27:57 PM PDT 24 Apr 15 03:27:59 PM PDT 24 499823776 ps
T876 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2612099244 Apr 15 03:27:45 PM PDT 24 Apr 15 03:27:48 PM PDT 24 628946724 ps
T877 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2902814620 Apr 15 03:28:02 PM PDT 24 Apr 15 03:28:03 PM PDT 24 529495998 ps
T99 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2518805035 Apr 15 03:28:01 PM PDT 24 Apr 15 03:28:06 PM PDT 24 819810846 ps
T878 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1017243518 Apr 15 03:28:09 PM PDT 24 Apr 15 03:28:10 PM PDT 24 481134635 ps
T879 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1078138779 Apr 15 03:28:17 PM PDT 24 Apr 15 03:28:22 PM PDT 24 2462128683 ps
T880 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3571935966 Apr 15 03:28:13 PM PDT 24 Apr 15 03:28:25 PM PDT 24 4425856155 ps
T352 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2365371521 Apr 15 03:28:04 PM PDT 24 Apr 15 03:28:09 PM PDT 24 9378489234 ps
T881 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4235002041 Apr 15 03:28:23 PM PDT 24 Apr 15 03:28:36 PM PDT 24 4269503403 ps
T882 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3588662759 Apr 15 03:27:45 PM PDT 24 Apr 15 03:27:48 PM PDT 24 318217978 ps
T100 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2890908258 Apr 15 03:28:16 PM PDT 24 Apr 15 03:28:19 PM PDT 24 548873125 ps
T883 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2797180548 Apr 15 03:28:07 PM PDT 24 Apr 15 03:28:29 PM PDT 24 8055574780 ps
T353 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3588081162 Apr 15 03:28:11 PM PDT 24 Apr 15 03:28:31 PM PDT 24 7950043012 ps
T350 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.542221396 Apr 15 03:28:12 PM PDT 24 Apr 15 03:28:20 PM PDT 24 8603425626 ps
T101 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1735443516 Apr 15 03:28:14 PM PDT 24 Apr 15 03:28:17 PM PDT 24 460080084 ps
T884 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1290512698 Apr 15 03:27:53 PM PDT 24 Apr 15 03:27:56 PM PDT 24 427759230 ps
T102 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.272578086 Apr 15 03:28:01 PM PDT 24 Apr 15 03:28:03 PM PDT 24 390978744 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2559387445 Apr 15 03:27:53 PM PDT 24 Apr 15 03:27:55 PM PDT 24 464438577 ps
T886 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1886460912 Apr 15 03:28:20 PM PDT 24 Apr 15 03:28:22 PM PDT 24 535182035 ps
T103 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3358557691 Apr 15 03:28:00 PM PDT 24 Apr 15 03:28:03 PM PDT 24 501952534 ps
T887 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2326357564 Apr 15 03:27:48 PM PDT 24 Apr 15 03:27:52 PM PDT 24 2392444860 ps
T888 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1852862554 Apr 15 03:28:03 PM PDT 24 Apr 15 03:28:05 PM PDT 24 450740002 ps
T889 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2979385090 Apr 15 03:27:50 PM PDT 24 Apr 15 03:28:04 PM PDT 24 8747736804 ps
T890 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.992980608 Apr 15 03:28:19 PM PDT 24 Apr 15 03:28:20 PM PDT 24 334733855 ps
T891 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.817942406 Apr 15 03:28:17 PM PDT 24 Apr 15 03:28:19 PM PDT 24 358702122 ps
T892 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2888825850 Apr 15 03:28:04 PM PDT 24 Apr 15 03:28:12 PM PDT 24 7618826430 ps
T893 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2624797329 Apr 15 03:28:15 PM PDT 24 Apr 15 03:28:18 PM PDT 24 2669962891 ps
T894 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2338477569 Apr 15 03:28:09 PM PDT 24 Apr 15 03:28:11 PM PDT 24 678967582 ps
T895 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3044219535 Apr 15 03:28:11 PM PDT 24 Apr 15 03:28:13 PM PDT 24 534619951 ps
T896 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2319975212 Apr 15 03:28:17 PM PDT 24 Apr 15 03:28:20 PM PDT 24 508078521 ps
T897 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.488424446 Apr 15 03:28:10 PM PDT 24 Apr 15 03:28:33 PM PDT 24 8520897891 ps
T898 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3332324415 Apr 15 03:28:23 PM PDT 24 Apr 15 03:28:25 PM PDT 24 297376728 ps
T899 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.684668964 Apr 15 03:28:20 PM PDT 24 Apr 15 03:28:24 PM PDT 24 2435451154 ps
T104 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3193737333 Apr 15 03:27:58 PM PDT 24 Apr 15 03:28:01 PM PDT 24 324419285 ps
T900 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2926312648 Apr 15 03:28:13 PM PDT 24 Apr 15 03:28:16 PM PDT 24 436385442 ps
T901 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.521651578 Apr 15 03:28:13 PM PDT 24 Apr 15 03:28:16 PM PDT 24 469966158 ps
T902 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.135486437 Apr 15 03:28:06 PM PDT 24 Apr 15 03:28:07 PM PDT 24 379849433 ps
T903 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1787314874 Apr 15 03:28:21 PM PDT 24 Apr 15 03:28:23 PM PDT 24 403775011 ps
T904 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2285695128 Apr 15 03:27:53 PM PDT 24 Apr 15 03:27:55 PM PDT 24 699847024 ps
T905 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2938816244 Apr 15 03:27:42 PM PDT 24 Apr 15 03:27:44 PM PDT 24 808457877 ps
T906 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4079624254 Apr 15 03:28:19 PM PDT 24 Apr 15 03:28:21 PM PDT 24 399132379 ps
T907 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3128212309 Apr 15 03:27:56 PM PDT 24 Apr 15 03:27:59 PM PDT 24 504850522 ps
T908 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.346064227 Apr 15 03:28:21 PM PDT 24 Apr 15 03:28:22 PM PDT 24 369063541 ps
T909 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2957415849 Apr 15 03:27:56 PM PDT 24 Apr 15 03:28:12 PM PDT 24 12093357732 ps
T910 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2296378314 Apr 15 03:28:16 PM PDT 24 Apr 15 03:28:18 PM PDT 24 453356779 ps
T911 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3090726033 Apr 15 03:28:22 PM PDT 24 Apr 15 03:28:24 PM PDT 24 444136843 ps
T912 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.350246607 Apr 15 03:28:18 PM PDT 24 Apr 15 03:28:19 PM PDT 24 316511068 ps
T913 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.982208692 Apr 15 03:28:17 PM PDT 24 Apr 15 03:28:20 PM PDT 24 516114417 ps
T914 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.4098463857 Apr 15 03:28:10 PM PDT 24 Apr 15 03:28:22 PM PDT 24 4449256289 ps
T915 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1418440384 Apr 15 03:28:03 PM PDT 24 Apr 15 03:28:05 PM PDT 24 2355681700 ps
T916 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2159093308 Apr 15 03:28:23 PM PDT 24 Apr 15 03:28:24 PM PDT 24 344868065 ps
T917 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4269678449 Apr 15 03:27:46 PM PDT 24 Apr 15 03:27:47 PM PDT 24 461892565 ps
T918 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2673976932 Apr 15 03:27:51 PM PDT 24 Apr 15 03:27:53 PM PDT 24 559595783 ps
T919 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3263961967 Apr 15 03:28:06 PM PDT 24 Apr 15 03:28:09 PM PDT 24 386296072 ps

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1333062110
Short name T8
Test name
Test status
Simulation time 946216551059 ps
CPU time 858.79 seconds
Started Apr 15 12:50:45 PM PDT 24
Finished Apr 15 01:05:04 PM PDT 24
Peak memory 211076 kb
Host smart-4f9f4e56-9c0e-445b-b96f-8c20ce4511d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333062110 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1333062110
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1416273134
Short name T22
Test name
Test status
Simulation time 562425941205 ps
CPU time 328.6 seconds
Started Apr 15 12:55:01 PM PDT 24
Finished Apr 15 01:00:30 PM PDT 24
Peak memory 202324 kb
Host smart-151727f6-96c5-4ebe-91b1-267eb3da417a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416273134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1416273134
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2754892540
Short name T223
Test name
Test status
Simulation time 500388814777 ps
CPU time 569.57 seconds
Started Apr 15 12:54:17 PM PDT 24
Finished Apr 15 01:03:47 PM PDT 24
Peak memory 202124 kb
Host smart-5a043e45-8df0-4d37-8b04-fbed883e1ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754892540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2754892540
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2100405113
Short name T36
Test name
Test status
Simulation time 515446494078 ps
CPU time 1247.39 seconds
Started Apr 15 12:54:55 PM PDT 24
Finished Apr 15 01:15:43 PM PDT 24
Peak memory 202256 kb
Host smart-8338214c-92be-49b5-aea3-1b23d4f58cf1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100405113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2100405113
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2786398081
Short name T230
Test name
Test status
Simulation time 523958063083 ps
CPU time 622.1 seconds
Started Apr 15 12:53:19 PM PDT 24
Finished Apr 15 01:03:42 PM PDT 24
Peak memory 202212 kb
Host smart-89413231-12fa-45f5-921e-94b3fbb90186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786398081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2786398081
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3578720067
Short name T11
Test name
Test status
Simulation time 45553357688 ps
CPU time 90.91 seconds
Started Apr 15 12:51:04 PM PDT 24
Finished Apr 15 12:52:36 PM PDT 24
Peak memory 210896 kb
Host smart-2a53d597-8ef9-4a6e-8d47-3ca05cda462c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578720067 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3578720067
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1909170445
Short name T122
Test name
Test status
Simulation time 485921506511 ps
CPU time 289.19 seconds
Started Apr 15 12:55:46 PM PDT 24
Finished Apr 15 01:00:36 PM PDT 24
Peak memory 202268 kb
Host smart-885f2c50-8da5-4503-b16c-b31195a63e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909170445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1909170445
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2111584481
Short name T51
Test name
Test status
Simulation time 356961110 ps
CPU time 2.56 seconds
Started Apr 15 03:28:17 PM PDT 24
Finished Apr 15 03:28:20 PM PDT 24
Peak memory 217788 kb
Host smart-ae8ac7ab-adf2-4466-9479-f74d79f87192
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111584481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2111584481
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.501251239
Short name T144
Test name
Test status
Simulation time 499475571852 ps
CPU time 215.46 seconds
Started Apr 15 12:51:51 PM PDT 24
Finished Apr 15 12:55:27 PM PDT 24
Peak memory 202356 kb
Host smart-679688b0-4b70-4b20-a8b5-e372653486b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501251239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
501251239
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.19779410
Short name T253
Test name
Test status
Simulation time 502842687736 ps
CPU time 1105.63 seconds
Started Apr 15 12:55:01 PM PDT 24
Finished Apr 15 01:13:27 PM PDT 24
Peak memory 202196 kb
Host smart-8ca92a8f-8587-4c03-a6d7-8fec7e956b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19779410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.19779410
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2622827984
Short name T5
Test name
Test status
Simulation time 545988577643 ps
CPU time 238.78 seconds
Started Apr 15 12:56:28 PM PDT 24
Finished Apr 15 01:00:27 PM PDT 24
Peak memory 202264 kb
Host smart-f1f3da09-940c-432f-b9ae-90061b92c94a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622827984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2622827984
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.804599588
Short name T239
Test name
Test status
Simulation time 336427544874 ps
CPU time 423.77 seconds
Started Apr 15 12:55:51 PM PDT 24
Finished Apr 15 01:02:55 PM PDT 24
Peak memory 202340 kb
Host smart-d8c4be67-6cfa-4d1f-919f-9c6fd3e797dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804599588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.804599588
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.292904101
Short name T32
Test name
Test status
Simulation time 542874484395 ps
CPU time 576.62 seconds
Started Apr 15 12:50:53 PM PDT 24
Finished Apr 15 01:00:30 PM PDT 24
Peak memory 210896 kb
Host smart-3644973f-c003-43a7-85d7-f1186ef9509e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292904101 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.292904101
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2275602519
Short name T374
Test name
Test status
Simulation time 468257090 ps
CPU time 1 seconds
Started Apr 15 12:50:43 PM PDT 24
Finished Apr 15 12:50:44 PM PDT 24
Peak memory 201980 kb
Host smart-20a0e67f-5327-42ef-8e6f-df6ba126ceac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275602519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2275602519
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2123796185
Short name T44
Test name
Test status
Simulation time 42304381939 ps
CPU time 51.71 seconds
Started Apr 15 03:27:45 PM PDT 24
Finished Apr 15 03:28:37 PM PDT 24
Peak memory 201492 kb
Host smart-ac1b8a40-c36a-4400-a1ef-1a654157069c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123796185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2123796185
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3529191419
Short name T20
Test name
Test status
Simulation time 484560453018 ps
CPU time 415.54 seconds
Started Apr 15 12:51:45 PM PDT 24
Finished Apr 15 12:58:41 PM PDT 24
Peak memory 202260 kb
Host smart-42b3075c-9646-425d-bdea-9a5781ca97b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529191419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3529191419
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.884253340
Short name T65
Test name
Test status
Simulation time 4262182081 ps
CPU time 5.71 seconds
Started Apr 15 12:50:33 PM PDT 24
Finished Apr 15 12:50:39 PM PDT 24
Peak memory 217800 kb
Host smart-50876aa0-8011-4a8e-856c-504adbc78fc4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884253340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.884253340
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2717199332
Short name T235
Test name
Test status
Simulation time 484631201900 ps
CPU time 598.52 seconds
Started Apr 15 12:51:28 PM PDT 24
Finished Apr 15 01:01:27 PM PDT 24
Peak memory 202264 kb
Host smart-72d6d039-1c8f-4b8c-b042-c798365f3d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717199332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2717199332
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2415558022
Short name T164
Test name
Test status
Simulation time 323546232700 ps
CPU time 208.02 seconds
Started Apr 15 12:51:04 PM PDT 24
Finished Apr 15 12:54:32 PM PDT 24
Peak memory 202260 kb
Host smart-551c8b97-cade-4b0d-ab45-446684c6d889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415558022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2415558022
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.674876692
Short name T127
Test name
Test status
Simulation time 541824723284 ps
CPU time 1142.94 seconds
Started Apr 15 12:53:36 PM PDT 24
Finished Apr 15 01:12:39 PM PDT 24
Peak memory 202384 kb
Host smart-5bda8833-3829-475d-915f-bc68b5b3e797
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674876692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.674876692
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3665356330
Short name T152
Test name
Test status
Simulation time 517347550292 ps
CPU time 583.98 seconds
Started Apr 15 12:54:42 PM PDT 24
Finished Apr 15 01:04:26 PM PDT 24
Peak memory 202276 kb
Host smart-f00f5d03-fa0b-4af4-bca8-78fc8d0c3afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665356330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3665356330
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.497445591
Short name T121
Test name
Test status
Simulation time 556577683129 ps
CPU time 649.22 seconds
Started Apr 15 12:52:09 PM PDT 24
Finished Apr 15 01:02:59 PM PDT 24
Peak memory 202204 kb
Host smart-c3ce6ea2-6b28-4aea-bbcf-2796c47f83db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497445591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.497445591
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4085237117
Short name T35
Test name
Test status
Simulation time 179738131738 ps
CPU time 212.13 seconds
Started Apr 15 12:55:22 PM PDT 24
Finished Apr 15 12:58:55 PM PDT 24
Peak memory 210596 kb
Host smart-16544cd4-2610-4101-ba69-0a8a243bf1f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085237117 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.4085237117
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3207077338
Short name T6
Test name
Test status
Simulation time 601292245594 ps
CPU time 1410.4 seconds
Started Apr 15 12:52:48 PM PDT 24
Finished Apr 15 01:16:19 PM PDT 24
Peak memory 202280 kb
Host smart-ca75567b-30ae-4179-a46f-0897a927f932
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207077338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3207077338
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.354425774
Short name T301
Test name
Test status
Simulation time 430105788963 ps
CPU time 986.25 seconds
Started Apr 15 12:52:41 PM PDT 24
Finished Apr 15 01:09:08 PM PDT 24
Peak memory 202328 kb
Host smart-825eeead-9bee-497f-a28a-29f9bdb0a581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354425774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
354425774
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.231791434
Short name T66
Test name
Test status
Simulation time 554325647635 ps
CPU time 312.34 seconds
Started Apr 15 12:51:39 PM PDT 24
Finished Apr 15 12:56:52 PM PDT 24
Peak memory 202352 kb
Host smart-e729abe0-a951-4210-9a35-e640019f6dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231791434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.231791434
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1634050142
Short name T1
Test name
Test status
Simulation time 545387888498 ps
CPU time 320.01 seconds
Started Apr 15 12:52:33 PM PDT 24
Finished Apr 15 12:57:53 PM PDT 24
Peak memory 202288 kb
Host smart-2f1607c9-ad17-4187-aca9-4f9670b72a6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634050142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1634050142
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3222138057
Short name T327
Test name
Test status
Simulation time 366782191816 ps
CPU time 378.3 seconds
Started Apr 15 12:53:46 PM PDT 24
Finished Apr 15 01:00:04 PM PDT 24
Peak memory 202340 kb
Host smart-9e4f3b9f-2f1f-424e-9918-458deb6dd2ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222138057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3222138057
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3006538228
Short name T237
Test name
Test status
Simulation time 352260613030 ps
CPU time 399 seconds
Started Apr 15 12:54:04 PM PDT 24
Finished Apr 15 01:00:44 PM PDT 24
Peak memory 202280 kb
Host smart-bda48373-92b0-4568-b3ce-953de9e24c53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006538228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3006538228
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.544719373
Short name T39
Test name
Test status
Simulation time 244099627476 ps
CPU time 541.45 seconds
Started Apr 15 12:51:06 PM PDT 24
Finished Apr 15 01:00:07 PM PDT 24
Peak memory 202592 kb
Host smart-bd8bbccc-e3d3-4ec3-a431-a4d74e48234a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544719373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.544719373
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3066354287
Short name T221
Test name
Test status
Simulation time 326906116935 ps
CPU time 177.93 seconds
Started Apr 15 12:52:55 PM PDT 24
Finished Apr 15 12:55:54 PM PDT 24
Peak memory 202248 kb
Host smart-ab47941b-3dcc-43d3-9146-7bf2d1429dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066354287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3066354287
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1393394032
Short name T351
Test name
Test status
Simulation time 8244719697 ps
CPU time 12.51 seconds
Started Apr 15 03:27:53 PM PDT 24
Finished Apr 15 03:28:06 PM PDT 24
Peak memory 201432 kb
Host smart-c6fa0d63-2ec8-4b95-9636-c6eef11a8fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393394032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1393394032
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1524354838
Short name T236
Test name
Test status
Simulation time 520928961034 ps
CPU time 272.38 seconds
Started Apr 15 12:54:21 PM PDT 24
Finished Apr 15 12:58:54 PM PDT 24
Peak memory 202284 kb
Host smart-9337882f-73d0-4054-b5d7-26992a9355d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524354838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1524354838
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1997829381
Short name T157
Test name
Test status
Simulation time 560029798464 ps
CPU time 264.32 seconds
Started Apr 15 12:52:14 PM PDT 24
Finished Apr 15 12:56:39 PM PDT 24
Peak memory 202340 kb
Host smart-0a887f5c-a6d3-49e0-b86f-a7cb1a564aaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997829381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1997829381
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3551466718
Short name T312
Test name
Test status
Simulation time 191765355532 ps
CPU time 98.06 seconds
Started Apr 15 12:52:37 PM PDT 24
Finished Apr 15 12:54:16 PM PDT 24
Peak memory 202324 kb
Host smart-dec90d90-f2c0-4dea-b73c-3c8c23440761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551466718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3551466718
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2327089222
Short name T15
Test name
Test status
Simulation time 158067958257 ps
CPU time 60.56 seconds
Started Apr 15 12:54:36 PM PDT 24
Finished Apr 15 12:55:37 PM PDT 24
Peak memory 210472 kb
Host smart-8d4c5550-b205-456e-b93c-647a0247b430
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327089222 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2327089222
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3277088868
Short name T273
Test name
Test status
Simulation time 108119105352 ps
CPU time 142.46 seconds
Started Apr 15 12:54:43 PM PDT 24
Finished Apr 15 12:57:05 PM PDT 24
Peak memory 218968 kb
Host smart-a7813dd0-e28c-4565-b65c-59f985a9f093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277088868 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3277088868
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3297532092
Short name T132
Test name
Test status
Simulation time 164848937564 ps
CPU time 100.54 seconds
Started Apr 15 12:56:26 PM PDT 24
Finished Apr 15 12:58:07 PM PDT 24
Peak memory 202228 kb
Host smart-4756b843-328f-4d83-92be-0995bb274ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297532092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3297532092
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.743101810
Short name T264
Test name
Test status
Simulation time 487139102061 ps
CPU time 222.77 seconds
Started Apr 15 12:50:28 PM PDT 24
Finished Apr 15 12:54:11 PM PDT 24
Peak memory 202212 kb
Host smart-ada16e0f-b6f2-4c44-992e-71fca462a38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743101810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.743101810
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1795451849
Short name T196
Test name
Test status
Simulation time 158673866131 ps
CPU time 98.75 seconds
Started Apr 15 12:50:33 PM PDT 24
Finished Apr 15 12:52:12 PM PDT 24
Peak memory 202084 kb
Host smart-b75a9542-d25a-4b11-b23c-d0c9d0b660ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795451849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1795451849
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.956738608
Short name T318
Test name
Test status
Simulation time 344801216514 ps
CPU time 135.75 seconds
Started Apr 15 12:56:52 PM PDT 24
Finished Apr 15 12:59:09 PM PDT 24
Peak memory 202284 kb
Host smart-ba7aa514-f89b-47ae-a642-648fcbf7e713
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956738608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.956738608
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.168310807
Short name T339
Test name
Test status
Simulation time 827761317551 ps
CPU time 1836.16 seconds
Started Apr 15 12:56:49 PM PDT 24
Finished Apr 15 01:27:26 PM PDT 24
Peak memory 202304 kb
Host smart-36339305-5771-4a59-bdb9-57263dc0a003
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168310807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
168310807
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2373001364
Short name T286
Test name
Test status
Simulation time 552521477677 ps
CPU time 1209.6 seconds
Started Apr 15 12:51:37 PM PDT 24
Finished Apr 15 01:11:47 PM PDT 24
Peak memory 202256 kb
Host smart-6f62dcca-2fa2-4f20-9b5f-57b727608099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373001364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2373001364
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4269002316
Short name T18
Test name
Test status
Simulation time 106092324064 ps
CPU time 131.81 seconds
Started Apr 15 12:53:22 PM PDT 24
Finished Apr 15 12:55:34 PM PDT 24
Peak memory 211092 kb
Host smart-7735ebb1-8ca1-499c-a5bd-e14f695cb8fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269002316 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4269002316
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3777147884
Short name T95
Test name
Test status
Simulation time 490772015 ps
CPU time 0.98 seconds
Started Apr 15 03:27:49 PM PDT 24
Finished Apr 15 03:27:51 PM PDT 24
Peak memory 201208 kb
Host smart-8825fbeb-f510-4ba6-9d55-dbce70f47027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777147884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3777147884
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2940408436
Short name T626
Test name
Test status
Simulation time 323953276536 ps
CPU time 303.26 seconds
Started Apr 15 12:51:52 PM PDT 24
Finished Apr 15 12:56:56 PM PDT 24
Peak memory 202368 kb
Host smart-0454c713-b4c0-4b46-8b87-c45ba614a833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940408436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2940408436
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2816653086
Short name T217
Test name
Test status
Simulation time 1269131899037 ps
CPU time 1856.14 seconds
Started Apr 15 12:56:33 PM PDT 24
Finished Apr 15 01:27:30 PM PDT 24
Peak memory 210800 kb
Host smart-8e565239-788a-4d75-b154-acb85e5239d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816653086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2816653086
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1166363284
Short name T252
Test name
Test status
Simulation time 490407079633 ps
CPU time 610.03 seconds
Started Apr 15 12:51:49 PM PDT 24
Finished Apr 15 01:02:00 PM PDT 24
Peak memory 202208 kb
Host smart-fec80cce-6332-4c10-bfbf-70befd0cead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166363284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1166363284
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3083931492
Short name T182
Test name
Test status
Simulation time 348328333351 ps
CPU time 205.65 seconds
Started Apr 15 12:51:57 PM PDT 24
Finished Apr 15 12:55:23 PM PDT 24
Peak memory 202168 kb
Host smart-4a0fea79-5abc-4e31-8c21-7cdbfaa3f3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083931492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3083931492
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.827818789
Short name T267
Test name
Test status
Simulation time 498844440682 ps
CPU time 1159.77 seconds
Started Apr 15 12:52:30 PM PDT 24
Finished Apr 15 01:11:50 PM PDT 24
Peak memory 202356 kb
Host smart-be873de8-30b5-4e2c-a57d-a1ea6af4b6be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827818789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.827818789
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1846506658
Short name T143
Test name
Test status
Simulation time 335766778194 ps
CPU time 558.11 seconds
Started Apr 15 12:52:48 PM PDT 24
Finished Apr 15 01:02:06 PM PDT 24
Peak memory 202348 kb
Host smart-6be98de4-422b-46e7-b3ac-1e0b8a2f0ec2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846506658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1846506658
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3238275182
Short name T234
Test name
Test status
Simulation time 497263592490 ps
CPU time 334.43 seconds
Started Apr 15 12:50:54 PM PDT 24
Finished Apr 15 12:56:29 PM PDT 24
Peak memory 202352 kb
Host smart-b229c33d-049f-4972-bec8-d6386e717949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238275182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3238275182
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3789008846
Short name T275
Test name
Test status
Simulation time 552465773301 ps
CPU time 610.54 seconds
Started Apr 15 12:50:42 PM PDT 24
Finished Apr 15 01:00:53 PM PDT 24
Peak memory 202376 kb
Host smart-ac90cab4-4d83-4136-bb1f-69d979ae6e6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789008846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3789008846
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2115834004
Short name T228
Test name
Test status
Simulation time 687103972536 ps
CPU time 665.82 seconds
Started Apr 15 12:56:19 PM PDT 24
Finished Apr 15 01:07:25 PM PDT 24
Peak memory 210872 kb
Host smart-9570fa95-9509-47d6-b1b1-24fade654231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115834004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2115834004
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.346981171
Short name T135
Test name
Test status
Simulation time 360023011813 ps
CPU time 405.97 seconds
Started Apr 15 12:51:30 PM PDT 24
Finished Apr 15 12:58:16 PM PDT 24
Peak memory 202168 kb
Host smart-b4c3f805-f12c-4eb1-ae45-2baf63673b04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346981171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.346981171
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1652275096
Short name T229
Test name
Test status
Simulation time 408991555928 ps
CPU time 867.1 seconds
Started Apr 15 12:53:37 PM PDT 24
Finished Apr 15 01:08:05 PM PDT 24
Peak memory 202292 kb
Host smart-7d3a5104-e8d1-448c-a829-d06e1c936f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652275096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1652275096
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2656970527
Short name T303
Test name
Test status
Simulation time 508211831829 ps
CPU time 1056.65 seconds
Started Apr 15 12:51:20 PM PDT 24
Finished Apr 15 01:08:58 PM PDT 24
Peak memory 202344 kb
Host smart-8e424722-573f-4eff-a7f7-c15c6b020f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656970527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2656970527
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.730864079
Short name T843
Test name
Test status
Simulation time 533602518 ps
CPU time 3.3 seconds
Started Apr 15 03:28:05 PM PDT 24
Finished Apr 15 03:28:09 PM PDT 24
Peak memory 210784 kb
Host smart-df82c868-0d96-4785-b14d-3cce8de6ff0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730864079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.730864079
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.299185144
Short name T332
Test name
Test status
Simulation time 235414872547 ps
CPU time 127.99 seconds
Started Apr 15 12:53:34 PM PDT 24
Finished Apr 15 12:55:42 PM PDT 24
Peak memory 210848 kb
Host smart-d3f97816-c3e1-4208-80a0-afc65da48c6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299185144 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.299185144
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3564891513
Short name T188
Test name
Test status
Simulation time 327979481190 ps
CPU time 745.86 seconds
Started Apr 15 12:54:40 PM PDT 24
Finished Apr 15 01:07:06 PM PDT 24
Peak memory 202348 kb
Host smart-b7115117-b772-463e-9882-2e837febd9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564891513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3564891513
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2751965569
Short name T311
Test name
Test status
Simulation time 541984764638 ps
CPU time 328.18 seconds
Started Apr 15 12:54:40 PM PDT 24
Finished Apr 15 01:00:09 PM PDT 24
Peak memory 202260 kb
Host smart-88a59cad-b3b0-4656-b09d-70faddd4691f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751965569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2751965569
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.730512535
Short name T47
Test name
Test status
Simulation time 191804311108 ps
CPU time 381.09 seconds
Started Apr 15 12:56:12 PM PDT 24
Finished Apr 15 01:02:34 PM PDT 24
Peak memory 202164 kb
Host smart-8125ff95-5e24-407a-a881-15ab2774cb94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730512535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.730512535
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1606383447
Short name T772
Test name
Test status
Simulation time 486547597255 ps
CPU time 1123.79 seconds
Started Apr 15 12:51:19 PM PDT 24
Finished Apr 15 01:10:03 PM PDT 24
Peak memory 202260 kb
Host smart-307523a0-e65c-4bbe-9e23-2a9aff49b5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606383447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1606383447
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3239870365
Short name T232
Test name
Test status
Simulation time 809238011197 ps
CPU time 1237.95 seconds
Started Apr 15 12:52:06 PM PDT 24
Finished Apr 15 01:12:44 PM PDT 24
Peak memory 202656 kb
Host smart-64df8c0b-efe3-4c95-8d09-300c384fb4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239870365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3239870365
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3724063794
Short name T256
Test name
Test status
Simulation time 490043645851 ps
CPU time 299.52 seconds
Started Apr 15 12:50:40 PM PDT 24
Finished Apr 15 12:55:39 PM PDT 24
Peak memory 202316 kb
Host smart-f485716a-f1cf-4263-bf89-4d6d30d62daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724063794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3724063794
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2798987753
Short name T314
Test name
Test status
Simulation time 323738361727 ps
CPU time 202.6 seconds
Started Apr 15 12:52:32 PM PDT 24
Finished Apr 15 12:55:55 PM PDT 24
Peak memory 202228 kb
Host smart-74be918b-cbec-4c06-8761-69db1b7db6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798987753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2798987753
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3614548656
Short name T243
Test name
Test status
Simulation time 538932209347 ps
CPU time 1316.94 seconds
Started Apr 15 12:53:09 PM PDT 24
Finished Apr 15 01:15:07 PM PDT 24
Peak memory 202276 kb
Host smart-fa358008-0091-4e5a-bc14-2bba4cbb09c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614548656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3614548656
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.151433591
Short name T261
Test name
Test status
Simulation time 153453908756 ps
CPU time 215.45 seconds
Started Apr 15 12:53:11 PM PDT 24
Finished Apr 15 12:56:47 PM PDT 24
Peak memory 210820 kb
Host smart-01f47a09-4f4f-488a-92ff-7651f5062eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151433591 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.151433591
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2649737431
Short name T308
Test name
Test status
Simulation time 338204361665 ps
CPU time 358.42 seconds
Started Apr 15 12:53:19 PM PDT 24
Finished Apr 15 12:59:18 PM PDT 24
Peak memory 202292 kb
Host smart-38d336a2-d8b6-4351-a978-ec6911ffb4a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649737431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2649737431
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.574004300
Short name T218
Test name
Test status
Simulation time 110964033792 ps
CPU time 648.09 seconds
Started Apr 15 12:53:33 PM PDT 24
Finished Apr 15 01:04:22 PM PDT 24
Peak memory 202592 kb
Host smart-19a6ae1d-4e10-4e70-a3a9-4845d7a8b9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574004300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.574004300
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.873506204
Short name T302
Test name
Test status
Simulation time 426760984496 ps
CPU time 435.92 seconds
Started Apr 15 12:53:54 PM PDT 24
Finished Apr 15 01:01:10 PM PDT 24
Peak memory 202620 kb
Host smart-fd4bd251-ab23-4750-aaad-a6c192a9e8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873506204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
873506204
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2497515232
Short name T299
Test name
Test status
Simulation time 324073494948 ps
CPU time 72.47 seconds
Started Apr 15 12:55:25 PM PDT 24
Finished Apr 15 12:56:38 PM PDT 24
Peak memory 202236 kb
Host smart-d40fbfbf-7de8-4a11-b679-bee54f792eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497515232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2497515232
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3226404915
Short name T328
Test name
Test status
Simulation time 489432862745 ps
CPU time 115.94 seconds
Started Apr 15 12:56:33 PM PDT 24
Finished Apr 15 12:58:29 PM PDT 24
Peak memory 202324 kb
Host smart-3b99c2e5-8d69-48cb-aee2-dd0b0c5b6a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226404915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3226404915
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.529105535
Short name T255
Test name
Test status
Simulation time 525776786453 ps
CPU time 243.48 seconds
Started Apr 15 12:51:07 PM PDT 24
Finished Apr 15 12:55:10 PM PDT 24
Peak memory 202380 kb
Host smart-cef2f30f-7710-4226-9425-8cf9857f0f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529105535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.529105535
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3914370169
Short name T63
Test name
Test status
Simulation time 8129037708 ps
CPU time 7.48 seconds
Started Apr 15 03:28:06 PM PDT 24
Finished Apr 15 03:28:14 PM PDT 24
Peak memory 201468 kb
Host smart-9ee5af0f-31aa-4f0f-bd1e-e1b5d4c5fdc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914370169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3914370169
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3770646779
Short name T50
Test name
Test status
Simulation time 9211117523 ps
CPU time 6.91 seconds
Started Apr 15 03:27:49 PM PDT 24
Finished Apr 15 03:27:56 PM PDT 24
Peak memory 201432 kb
Host smart-65ff1d0f-807e-479e-9eb6-95a93646d380
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770646779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3770646779
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2649353261
Short name T231
Test name
Test status
Simulation time 335829695528 ps
CPU time 195.12 seconds
Started Apr 15 12:50:32 PM PDT 24
Finished Apr 15 12:53:47 PM PDT 24
Peak memory 202356 kb
Host smart-ad8228a4-2efa-46fe-9a51-ef4368f74958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649353261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2649353261
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1915052795
Short name T304
Test name
Test status
Simulation time 678723411923 ps
CPU time 490.89 seconds
Started Apr 15 12:50:37 PM PDT 24
Finished Apr 15 12:58:49 PM PDT 24
Peak memory 202360 kb
Host smart-911f42ca-c0dc-49c7-b17f-91ceb493bbd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915052795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1915052795
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1854589670
Short name T307
Test name
Test status
Simulation time 164977059921 ps
CPU time 101.77 seconds
Started Apr 15 12:51:23 PM PDT 24
Finished Apr 15 12:53:05 PM PDT 24
Peak memory 202336 kb
Host smart-0b506699-e930-4c64-9a33-7ff0bb1db479
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854589670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1854589670
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.4141795225
Short name T190
Test name
Test status
Simulation time 713556896658 ps
CPU time 283.53 seconds
Started Apr 15 12:51:37 PM PDT 24
Finished Apr 15 12:56:21 PM PDT 24
Peak memory 202236 kb
Host smart-09c51137-f559-457c-85cd-a19728033432
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141795225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.4141795225
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.4120396999
Short name T281
Test name
Test status
Simulation time 357739332014 ps
CPU time 268.29 seconds
Started Apr 15 12:52:04 PM PDT 24
Finished Apr 15 12:56:33 PM PDT 24
Peak memory 202272 kb
Host smart-7776508c-5c00-43b9-b692-2b2f49d5a731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120396999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.4120396999
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1103533898
Short name T242
Test name
Test status
Simulation time 492772313296 ps
CPU time 1168.63 seconds
Started Apr 15 12:52:36 PM PDT 24
Finished Apr 15 01:12:05 PM PDT 24
Peak memory 202276 kb
Host smart-4be8f9bc-d696-46b9-bec4-39371a055d27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103533898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1103533898
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3737008857
Short name T198
Test name
Test status
Simulation time 325673847811 ps
CPU time 167.92 seconds
Started Apr 15 12:53:11 PM PDT 24
Finished Apr 15 12:55:59 PM PDT 24
Peak memory 202240 kb
Host smart-3b025f9a-3980-4b76-80b4-cf4476c72823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737008857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3737008857
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3964557550
Short name T756
Test name
Test status
Simulation time 72182146905 ps
CPU time 353.73 seconds
Started Apr 15 12:53:41 PM PDT 24
Finished Apr 15 12:59:35 PM PDT 24
Peak memory 202644 kb
Host smart-566a5db0-67f6-4c19-b8b2-d148b23cba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964557550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3964557550
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3746450912
Short name T357
Test name
Test status
Simulation time 125487918177 ps
CPU time 393.73 seconds
Started Apr 15 12:54:28 PM PDT 24
Finished Apr 15 01:01:02 PM PDT 24
Peak memory 202564 kb
Host smart-3acbd2e7-8f08-414d-89cd-cb0c0c98eabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746450912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3746450912
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3444114607
Short name T216
Test name
Test status
Simulation time 791939270328 ps
CPU time 1142.4 seconds
Started Apr 15 12:54:36 PM PDT 24
Finished Apr 15 01:13:39 PM PDT 24
Peak memory 202524 kb
Host smart-c72713cd-6459-423c-90b4-5bb8090c54f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444114607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3444114607
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2305999468
Short name T211
Test name
Test status
Simulation time 114650103154 ps
CPU time 341.22 seconds
Started Apr 15 12:54:53 PM PDT 24
Finished Apr 15 01:00:34 PM PDT 24
Peak memory 202672 kb
Host smart-9d8dee8f-5ca8-45c0-9123-de1c4fdffcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305999468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2305999468
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.999185722
Short name T360
Test name
Test status
Simulation time 110907987837 ps
CPU time 557.21 seconds
Started Apr 15 12:55:01 PM PDT 24
Finished Apr 15 01:04:18 PM PDT 24
Peak memory 202640 kb
Host smart-e8285ade-e0db-42ef-a452-94a3880c634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999185722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.999185722
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2221696224
Short name T203
Test name
Test status
Simulation time 367942193064 ps
CPU time 224.17 seconds
Started Apr 15 12:56:20 PM PDT 24
Finished Apr 15 01:00:05 PM PDT 24
Peak memory 202244 kb
Host smart-49c3a30f-283f-450c-a3a0-ad28ba6921d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221696224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2221696224
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.451582805
Short name T259
Test name
Test status
Simulation time 372297857134 ps
CPU time 868.65 seconds
Started Apr 15 12:50:59 PM PDT 24
Finished Apr 15 01:05:29 PM PDT 24
Peak memory 202296 kb
Host smart-9f4f72e1-e3ce-46fa-aeda-e0834b003344
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451582805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.451582805
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2938816244
Short name T905
Test name
Test status
Simulation time 808457877 ps
CPU time 1.72 seconds
Started Apr 15 03:27:42 PM PDT 24
Finished Apr 15 03:27:44 PM PDT 24
Peak memory 201432 kb
Host smart-53d14ae9-344d-4e98-aef0-cdb97bbd2c28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938816244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2938816244
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1417052548
Short name T43
Test name
Test status
Simulation time 51989321629 ps
CPU time 33.24 seconds
Started Apr 15 03:27:43 PM PDT 24
Finished Apr 15 03:28:17 PM PDT 24
Peak memory 201504 kb
Host smart-69b608fb-5b9f-48d3-969a-d953eca0a37a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417052548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1417052548
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1647716546
Short name T92
Test name
Test status
Simulation time 1234393384 ps
CPU time 1.6 seconds
Started Apr 15 03:27:43 PM PDT 24
Finished Apr 15 03:27:45 PM PDT 24
Peak memory 201248 kb
Host smart-135d2a24-e637-4d5a-b8ce-cc15d9eba53f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647716546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1647716546
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2833674355
Short name T859
Test name
Test status
Simulation time 390781174 ps
CPU time 1.68 seconds
Started Apr 15 03:27:44 PM PDT 24
Finished Apr 15 03:27:46 PM PDT 24
Peak memory 201280 kb
Host smart-635abc01-7a0e-49f6-a8ac-73beaa6fb807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833674355 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2833674355
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1768113589
Short name T111
Test name
Test status
Simulation time 481661408 ps
CPU time 1.11 seconds
Started Apr 15 03:27:48 PM PDT 24
Finished Apr 15 03:27:50 PM PDT 24
Peak memory 201208 kb
Host smart-5f59646e-7d5d-4300-a70f-3bf0677e1298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768113589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1768113589
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3159638416
Short name T840
Test name
Test status
Simulation time 352021426 ps
CPU time 1.43 seconds
Started Apr 15 03:27:41 PM PDT 24
Finished Apr 15 03:27:43 PM PDT 24
Peak memory 201248 kb
Host smart-226522b8-2d88-4595-81b9-f8fa74902aba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159638416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3159638416
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.790343767
Short name T848
Test name
Test status
Simulation time 2322728973 ps
CPU time 2.18 seconds
Started Apr 15 03:27:42 PM PDT 24
Finished Apr 15 03:27:44 PM PDT 24
Peak memory 201312 kb
Host smart-02f4f4f2-63f3-43c0-a2d0-f36e5e92f4f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790343767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.790343767
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.349060114
Short name T830
Test name
Test status
Simulation time 701047970 ps
CPU time 1.55 seconds
Started Apr 15 03:27:49 PM PDT 24
Finished Apr 15 03:27:51 PM PDT 24
Peak memory 201480 kb
Host smart-0f7acee4-ac4f-4a8b-9d35-1c39206bb347
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349060114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.349060114
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2460536912
Short name T844
Test name
Test status
Simulation time 4947054598 ps
CPU time 2.96 seconds
Started Apr 15 03:27:48 PM PDT 24
Finished Apr 15 03:27:52 PM PDT 24
Peak memory 201496 kb
Host smart-cf0b3e12-6746-4a46-98a6-fe884ca95fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460536912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2460536912
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.980504881
Short name T96
Test name
Test status
Simulation time 1174139897 ps
CPU time 2.61 seconds
Started Apr 15 03:27:46 PM PDT 24
Finished Apr 15 03:27:49 PM PDT 24
Peak memory 201480 kb
Host smart-0efd3881-9711-4243-88c3-217d6a10b8af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980504881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.980504881
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2612099244
Short name T876
Test name
Test status
Simulation time 628946724 ps
CPU time 1.95 seconds
Started Apr 15 03:27:45 PM PDT 24
Finished Apr 15 03:27:48 PM PDT 24
Peak memory 201136 kb
Host smart-837f1ed3-8d7b-4525-ac62-70f44c8d5383
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612099244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2612099244
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4269678449
Short name T917
Test name
Test status
Simulation time 461892565 ps
CPU time 1.23 seconds
Started Apr 15 03:27:46 PM PDT 24
Finished Apr 15 03:27:47 PM PDT 24
Peak memory 201300 kb
Host smart-8ed5c522-f33c-436b-b55c-485284d9c58b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269678449 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.4269678449
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.91845707
Short name T804
Test name
Test status
Simulation time 472576360 ps
CPU time 1.47 seconds
Started Apr 15 03:27:48 PM PDT 24
Finished Apr 15 03:27:50 PM PDT 24
Peak memory 201260 kb
Host smart-2d509cf7-7802-4bad-9598-6a516aee7656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91845707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.91845707
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.770477449
Short name T870
Test name
Test status
Simulation time 2027777329 ps
CPU time 5.66 seconds
Started Apr 15 03:27:46 PM PDT 24
Finished Apr 15 03:27:52 PM PDT 24
Peak memory 201248 kb
Host smart-c3c2a390-1174-4b8a-840b-526eafc76844
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770477449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.770477449
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3588662759
Short name T882
Test name
Test status
Simulation time 318217978 ps
CPU time 1.98 seconds
Started Apr 15 03:27:45 PM PDT 24
Finished Apr 15 03:27:48 PM PDT 24
Peak memory 201552 kb
Host smart-5cf17e15-be5a-4699-bac1-df487b385226
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588662759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3588662759
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2338477569
Short name T894
Test name
Test status
Simulation time 678967582 ps
CPU time 1.26 seconds
Started Apr 15 03:28:09 PM PDT 24
Finished Apr 15 03:28:11 PM PDT 24
Peak memory 201328 kb
Host smart-b8ae5fed-15c7-4910-a0e2-99566fa21209
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338477569 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2338477569
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.793973024
Short name T861
Test name
Test status
Simulation time 696291122 ps
CPU time 0.85 seconds
Started Apr 15 03:28:06 PM PDT 24
Finished Apr 15 03:28:08 PM PDT 24
Peak memory 201248 kb
Host smart-cdd8e75e-e720-4f73-a9b4-97cc9fbc73b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793973024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.793973024
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.135486437
Short name T902
Test name
Test status
Simulation time 379849433 ps
CPU time 0.75 seconds
Started Apr 15 03:28:06 PM PDT 24
Finished Apr 15 03:28:07 PM PDT 24
Peak memory 201216 kb
Host smart-a064d497-f454-4263-bd52-1124afd8d114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135486437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.135486437
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3345801034
Short name T873
Test name
Test status
Simulation time 2211481613 ps
CPU time 9.33 seconds
Started Apr 15 03:28:04 PM PDT 24
Finished Apr 15 03:28:14 PM PDT 24
Peak memory 201276 kb
Host smart-93f6e149-714c-4242-8fd3-06ad6a5e0fe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345801034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3345801034
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2797180548
Short name T883
Test name
Test status
Simulation time 8055574780 ps
CPU time 21.2 seconds
Started Apr 15 03:28:07 PM PDT 24
Finished Apr 15 03:28:29 PM PDT 24
Peak memory 201452 kb
Host smart-544a4565-3239-4c14-9c0d-99eff43bc015
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797180548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2797180548
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.131867924
Short name T819
Test name
Test status
Simulation time 678365836 ps
CPU time 1.72 seconds
Started Apr 15 03:28:06 PM PDT 24
Finished Apr 15 03:28:09 PM PDT 24
Peak memory 201248 kb
Host smart-13234448-61ae-4930-9689-b6167a4ba859
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131867924 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.131867924
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3263961967
Short name T919
Test name
Test status
Simulation time 386296072 ps
CPU time 1.48 seconds
Started Apr 15 03:28:06 PM PDT 24
Finished Apr 15 03:28:09 PM PDT 24
Peak memory 201248 kb
Host smart-e8500572-ed96-40c5-85f3-06f7ae9d33a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263961967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3263961967
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1479974024
Short name T856
Test name
Test status
Simulation time 341464037 ps
CPU time 1.03 seconds
Started Apr 15 03:28:05 PM PDT 24
Finished Apr 15 03:28:06 PM PDT 24
Peak memory 201240 kb
Host smart-757e165b-166f-4d3f-a54f-2816385a7e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479974024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1479974024
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.261860853
Short name T46
Test name
Test status
Simulation time 2474901875 ps
CPU time 1.3 seconds
Started Apr 15 03:28:05 PM PDT 24
Finished Apr 15 03:28:07 PM PDT 24
Peak memory 201284 kb
Host smart-36dd3bbd-a220-4e70-a88b-3c41f9a1b933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261860853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.261860853
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4117585959
Short name T78
Test name
Test status
Simulation time 382588163 ps
CPU time 1.43 seconds
Started Apr 15 03:28:06 PM PDT 24
Finished Apr 15 03:28:08 PM PDT 24
Peak memory 201488 kb
Host smart-0d145d9b-31a4-47bb-909e-fa9421e8d97d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117585959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.4117585959
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3044219535
Short name T895
Test name
Test status
Simulation time 534619951 ps
CPU time 1.29 seconds
Started Apr 15 03:28:11 PM PDT 24
Finished Apr 15 03:28:13 PM PDT 24
Peak memory 201316 kb
Host smart-4d659489-191c-4136-8ce0-19788fda9f78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044219535 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3044219535
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1735443516
Short name T101
Test name
Test status
Simulation time 460080084 ps
CPU time 1.82 seconds
Started Apr 15 03:28:14 PM PDT 24
Finished Apr 15 03:28:17 PM PDT 24
Peak memory 201200 kb
Host smart-846caa1b-3c40-4101-afe2-088df90c3bcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735443516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1735443516
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1460900586
Short name T820
Test name
Test status
Simulation time 398081021 ps
CPU time 0.77 seconds
Started Apr 15 03:28:10 PM PDT 24
Finished Apr 15 03:28:12 PM PDT 24
Peak memory 201232 kb
Host smart-3e28fae6-977c-4606-8ff8-42180eecfef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460900586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1460900586
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2624797329
Short name T893
Test name
Test status
Simulation time 2669962891 ps
CPU time 2.27 seconds
Started Apr 15 03:28:15 PM PDT 24
Finished Apr 15 03:28:18 PM PDT 24
Peak memory 201304 kb
Host smart-089aad12-20c3-4057-b141-278ae12db908
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624797329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2624797329
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3655415029
Short name T62
Test name
Test status
Simulation time 522945152 ps
CPU time 1.76 seconds
Started Apr 15 03:28:10 PM PDT 24
Finished Apr 15 03:28:12 PM PDT 24
Peak memory 201496 kb
Host smart-64a68837-2e6a-4a75-aeee-e000b0f0a420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655415029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3655415029
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.488424446
Short name T897
Test name
Test status
Simulation time 8520897891 ps
CPU time 21.74 seconds
Started Apr 15 03:28:10 PM PDT 24
Finished Apr 15 03:28:33 PM PDT 24
Peak memory 201492 kb
Host smart-e48ca95f-8efc-49c6-8137-cfde0cc4bf14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488424446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.488424446
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1636952902
Short name T849
Test name
Test status
Simulation time 598419093 ps
CPU time 1.67 seconds
Started Apr 15 03:28:10 PM PDT 24
Finished Apr 15 03:28:13 PM PDT 24
Peak memory 201316 kb
Host smart-8b8f9dad-0f10-42bb-8656-e013339cd773
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636952902 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1636952902
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1822862441
Short name T105
Test name
Test status
Simulation time 374455460 ps
CPU time 1.81 seconds
Started Apr 15 03:28:13 PM PDT 24
Finished Apr 15 03:28:16 PM PDT 24
Peak memory 201244 kb
Host smart-4898dad2-b513-4a14-a9d2-650e3fb88cfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822862441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1822862441
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4082221532
Short name T834
Test name
Test status
Simulation time 453379521 ps
CPU time 1.64 seconds
Started Apr 15 03:28:15 PM PDT 24
Finished Apr 15 03:28:17 PM PDT 24
Peak memory 201240 kb
Host smart-ed28c7f2-6c52-4966-90ad-c4f8520b919d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082221532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4082221532
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1683263654
Short name T851
Test name
Test status
Simulation time 4188884885 ps
CPU time 4.98 seconds
Started Apr 15 03:28:10 PM PDT 24
Finished Apr 15 03:28:16 PM PDT 24
Peak memory 201528 kb
Host smart-015c230e-861d-4bdb-9512-ef8a976321d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683263654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1683263654
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1889192626
Short name T865
Test name
Test status
Simulation time 414129357 ps
CPU time 2.75 seconds
Started Apr 15 03:28:10 PM PDT 24
Finished Apr 15 03:28:14 PM PDT 24
Peak memory 201484 kb
Host smart-9071d9ef-8b95-44e4-9b35-3e491f4c9bcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889192626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1889192626
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1021012628
Short name T862
Test name
Test status
Simulation time 8178732185 ps
CPU time 21.15 seconds
Started Apr 15 03:28:09 PM PDT 24
Finished Apr 15 03:28:31 PM PDT 24
Peak memory 201620 kb
Host smart-b352bd08-f372-45a4-9203-f62b2332195d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021012628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1021012628
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3653362063
Short name T845
Test name
Test status
Simulation time 577616946 ps
CPU time 2.28 seconds
Started Apr 15 03:28:10 PM PDT 24
Finished Apr 15 03:28:13 PM PDT 24
Peak memory 201308 kb
Host smart-42ee7551-044e-4d12-8e3a-77cbbec6d3dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653362063 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3653362063
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3169104631
Short name T850
Test name
Test status
Simulation time 364089718 ps
CPU time 1.63 seconds
Started Apr 15 03:28:10 PM PDT 24
Finished Apr 15 03:28:12 PM PDT 24
Peak memory 201248 kb
Host smart-e48d046d-fd53-4510-9bfc-641eabdc20b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169104631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3169104631
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1017243518
Short name T878
Test name
Test status
Simulation time 481134635 ps
CPU time 0.94 seconds
Started Apr 15 03:28:09 PM PDT 24
Finished Apr 15 03:28:10 PM PDT 24
Peak memory 201200 kb
Host smart-243042ce-d1bf-4c37-a920-e291dcd8705a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017243518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1017243518
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.4098463857
Short name T914
Test name
Test status
Simulation time 4449256289 ps
CPU time 10.44 seconds
Started Apr 15 03:28:10 PM PDT 24
Finished Apr 15 03:28:22 PM PDT 24
Peak memory 201504 kb
Host smart-e36e56f7-474f-4daa-b5f8-4301cee68bbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098463857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.4098463857
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2356308045
Short name T817
Test name
Test status
Simulation time 668688597 ps
CPU time 2.68 seconds
Started Apr 15 03:28:08 PM PDT 24
Finished Apr 15 03:28:12 PM PDT 24
Peak memory 209724 kb
Host smart-a7bb1489-e96c-4343-af25-d17b46c27c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356308045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2356308045
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3588081162
Short name T353
Test name
Test status
Simulation time 7950043012 ps
CPU time 19.52 seconds
Started Apr 15 03:28:11 PM PDT 24
Finished Apr 15 03:28:31 PM PDT 24
Peak memory 201516 kb
Host smart-64a08c75-de24-4ec7-ae2e-d2ba56fb3d61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588081162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3588081162
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3899572343
Short name T833
Test name
Test status
Simulation time 590940647 ps
CPU time 1.26 seconds
Started Apr 15 03:28:15 PM PDT 24
Finished Apr 15 03:28:17 PM PDT 24
Peak memory 201328 kb
Host smart-b2da846a-68fd-4b86-97e0-dde96513ac4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899572343 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3899572343
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4021170013
Short name T821
Test name
Test status
Simulation time 305691876 ps
CPU time 1.37 seconds
Started Apr 15 03:28:12 PM PDT 24
Finished Apr 15 03:28:14 PM PDT 24
Peak memory 201264 kb
Host smart-68956bb4-72ec-40f7-b0c4-e3d6ea6317b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021170013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.4021170013
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4166582794
Short name T806
Test name
Test status
Simulation time 366543412 ps
CPU time 1.08 seconds
Started Apr 15 03:28:11 PM PDT 24
Finished Apr 15 03:28:13 PM PDT 24
Peak memory 201232 kb
Host smart-d91eae87-fdd5-4742-8380-11cb5f158a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166582794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.4166582794
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3152132651
Short name T860
Test name
Test status
Simulation time 2764006266 ps
CPU time 7.02 seconds
Started Apr 15 03:28:14 PM PDT 24
Finished Apr 15 03:28:22 PM PDT 24
Peak memory 201304 kb
Host smart-1f916fe6-ffc6-4cd4-adaa-71b5d6a0fb08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152132651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3152132651
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.482321060
Short name T847
Test name
Test status
Simulation time 554742354 ps
CPU time 2.71 seconds
Started Apr 15 03:28:09 PM PDT 24
Finished Apr 15 03:28:13 PM PDT 24
Peak memory 217492 kb
Host smart-78eff13e-6707-4ded-a814-4bb23aa5d5df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482321060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.482321060
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4235002041
Short name T881
Test name
Test status
Simulation time 4269503403 ps
CPU time 12.31 seconds
Started Apr 15 03:28:23 PM PDT 24
Finished Apr 15 03:28:36 PM PDT 24
Peak memory 201508 kb
Host smart-b926afad-9758-4210-88fb-3d5b27776faf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235002041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4235002041
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2296378314
Short name T910
Test name
Test status
Simulation time 453356779 ps
CPU time 1.35 seconds
Started Apr 15 03:28:16 PM PDT 24
Finished Apr 15 03:28:18 PM PDT 24
Peak memory 201316 kb
Host smart-58f805e5-5429-450e-935b-ea77045d7b1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296378314 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2296378314
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.521651578
Short name T901
Test name
Test status
Simulation time 469966158 ps
CPU time 2.02 seconds
Started Apr 15 03:28:13 PM PDT 24
Finished Apr 15 03:28:16 PM PDT 24
Peak memory 201236 kb
Host smart-1358c12a-e270-4cf4-97b5-a4038a4189b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521651578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.521651578
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2274435867
Short name T802
Test name
Test status
Simulation time 589799370 ps
CPU time 0.72 seconds
Started Apr 15 03:28:15 PM PDT 24
Finished Apr 15 03:28:16 PM PDT 24
Peak memory 201244 kb
Host smart-ff6762f0-c63c-4422-80f7-619389873af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274435867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2274435867
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2553499709
Short name T45
Test name
Test status
Simulation time 4909062121 ps
CPU time 5.93 seconds
Started Apr 15 03:28:14 PM PDT 24
Finished Apr 15 03:28:20 PM PDT 24
Peak memory 201412 kb
Host smart-de52ec74-630c-45df-9949-ef8e1c855afd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553499709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2553499709
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2276633738
Short name T868
Test name
Test status
Simulation time 554226080 ps
CPU time 2.95 seconds
Started Apr 15 03:28:13 PM PDT 24
Finished Apr 15 03:28:16 PM PDT 24
Peak memory 210708 kb
Host smart-70cfb333-cfd1-4f16-b938-11e74ea89a07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276633738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2276633738
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3571935966
Short name T880
Test name
Test status
Simulation time 4425856155 ps
CPU time 11.75 seconds
Started Apr 15 03:28:13 PM PDT 24
Finished Apr 15 03:28:25 PM PDT 24
Peak memory 201444 kb
Host smart-58ffbfc9-6c93-4f25-9949-820e43563889
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571935966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3571935966
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1428528507
Short name T76
Test name
Test status
Simulation time 570016390 ps
CPU time 1.22 seconds
Started Apr 15 03:28:20 PM PDT 24
Finished Apr 15 03:28:22 PM PDT 24
Peak memory 201328 kb
Host smart-fb3d677c-e05b-44b6-a79e-3d3a8d68e729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428528507 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1428528507
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2926312648
Short name T900
Test name
Test status
Simulation time 436385442 ps
CPU time 1.35 seconds
Started Apr 15 03:28:13 PM PDT 24
Finished Apr 15 03:28:16 PM PDT 24
Peak memory 201252 kb
Host smart-de00179b-72ea-4af3-a47c-1643d11a346f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926312648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2926312648
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1217637268
Short name T812
Test name
Test status
Simulation time 333541838 ps
CPU time 0.83 seconds
Started Apr 15 03:28:12 PM PDT 24
Finished Apr 15 03:28:14 PM PDT 24
Peak memory 201232 kb
Host smart-6280edc6-fadf-41da-bfee-b6071f0926db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217637268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1217637268
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.684668964
Short name T899
Test name
Test status
Simulation time 2435451154 ps
CPU time 2.88 seconds
Started Apr 15 03:28:20 PM PDT 24
Finished Apr 15 03:28:24 PM PDT 24
Peak memory 201304 kb
Host smart-a8cea81f-818c-4572-be94-04086ccd285e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684668964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.684668964
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.797160886
Short name T871
Test name
Test status
Simulation time 479891196 ps
CPU time 2.57 seconds
Started Apr 15 03:28:14 PM PDT 24
Finished Apr 15 03:28:17 PM PDT 24
Peak memory 201500 kb
Host smart-d3a4b8ef-fd90-41ad-ab4a-78ad739e5d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797160886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.797160886
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.542221396
Short name T350
Test name
Test status
Simulation time 8603425626 ps
CPU time 7.44 seconds
Started Apr 15 03:28:12 PM PDT 24
Finished Apr 15 03:28:20 PM PDT 24
Peak memory 201484 kb
Host smart-e2aaadcb-7678-4c53-bbca-41ee68b9f010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542221396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.542221396
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.982208692
Short name T913
Test name
Test status
Simulation time 516114417 ps
CPU time 1.89 seconds
Started Apr 15 03:28:17 PM PDT 24
Finished Apr 15 03:28:20 PM PDT 24
Peak memory 201288 kb
Host smart-b09063ab-1cc3-4636-a6e7-c8381e9299f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982208692 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.982208692
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2890908258
Short name T100
Test name
Test status
Simulation time 548873125 ps
CPU time 2.11 seconds
Started Apr 15 03:28:16 PM PDT 24
Finished Apr 15 03:28:19 PM PDT 24
Peak memory 201248 kb
Host smart-5005f517-d9ce-46d9-9c7e-02c3ce60dfc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890908258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2890908258
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.196027093
Short name T831
Test name
Test status
Simulation time 441853630 ps
CPU time 0.77 seconds
Started Apr 15 03:28:18 PM PDT 24
Finished Apr 15 03:28:19 PM PDT 24
Peak memory 201268 kb
Host smart-b5e05588-952b-4995-bee1-f1de5caabe87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196027093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.196027093
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1078138779
Short name T879
Test name
Test status
Simulation time 2462128683 ps
CPU time 4.78 seconds
Started Apr 15 03:28:17 PM PDT 24
Finished Apr 15 03:28:22 PM PDT 24
Peak memory 201296 kb
Host smart-46d1cde8-8893-47f1-bcbd-d0079d3c33b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078138779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1078138779
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2718478563
Short name T829
Test name
Test status
Simulation time 512325853 ps
CPU time 2.41 seconds
Started Apr 15 03:28:22 PM PDT 24
Finished Apr 15 03:28:25 PM PDT 24
Peak memory 217196 kb
Host smart-b28aba49-add7-4a37-abc2-b02fc307a59d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718478563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2718478563
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1753265714
Short name T49
Test name
Test status
Simulation time 8275164467 ps
CPU time 12.4 seconds
Started Apr 15 03:28:17 PM PDT 24
Finished Apr 15 03:28:30 PM PDT 24
Peak memory 201556 kb
Host smart-69b6f136-36d2-40e8-a259-7cb9bd686c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753265714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1753265714
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.186741257
Short name T77
Test name
Test status
Simulation time 553291073 ps
CPU time 2.19 seconds
Started Apr 15 03:28:19 PM PDT 24
Finished Apr 15 03:28:23 PM PDT 24
Peak memory 201308 kb
Host smart-0752e5f5-13aa-4339-a564-5f75c7348e14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186741257 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.186741257
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4079624254
Short name T906
Test name
Test status
Simulation time 399132379 ps
CPU time 0.96 seconds
Started Apr 15 03:28:19 PM PDT 24
Finished Apr 15 03:28:21 PM PDT 24
Peak memory 201244 kb
Host smart-206ddb6b-a5bb-4222-9592-cd985b4ef460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079624254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.4079624254
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1977581945
Short name T809
Test name
Test status
Simulation time 361390924 ps
CPU time 1.53 seconds
Started Apr 15 03:28:19 PM PDT 24
Finished Apr 15 03:28:22 PM PDT 24
Peak memory 201240 kb
Host smart-a949a05f-b349-4e82-a295-51da3f8e79b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977581945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1977581945
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3544444351
Short name T106
Test name
Test status
Simulation time 2360513217 ps
CPU time 1.84 seconds
Started Apr 15 03:28:20 PM PDT 24
Finished Apr 15 03:28:23 PM PDT 24
Peak memory 201236 kb
Host smart-063962f5-73c5-4f8c-a24b-5adeaafb1b65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544444351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3544444351
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.4254890129
Short name T59
Test name
Test status
Simulation time 4873940596 ps
CPU time 3.37 seconds
Started Apr 15 03:28:19 PM PDT 24
Finished Apr 15 03:28:23 PM PDT 24
Peak memory 201512 kb
Host smart-3cb50d1f-1640-4385-9aa4-c5b7899766c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254890129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.4254890129
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1710940661
Short name T91
Test name
Test status
Simulation time 657315389 ps
CPU time 2.18 seconds
Started Apr 15 03:27:50 PM PDT 24
Finished Apr 15 03:27:53 PM PDT 24
Peak memory 201488 kb
Host smart-a8e0e754-bf4f-4dde-bf49-23f1ee4171ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710940661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1710940661
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.969651904
Short name T113
Test name
Test status
Simulation time 26336513841 ps
CPU time 15.9 seconds
Started Apr 15 03:27:49 PM PDT 24
Finished Apr 15 03:28:06 PM PDT 24
Peak memory 201504 kb
Host smart-17db1036-45c5-4d9b-b153-418b73c41f07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969651904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.969651904
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2596114158
Short name T94
Test name
Test status
Simulation time 1369762941 ps
CPU time 2.92 seconds
Started Apr 15 03:27:47 PM PDT 24
Finished Apr 15 03:27:51 PM PDT 24
Peak memory 201260 kb
Host smart-5d1ec65c-ef24-42bb-a110-8ed7b77cd81d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596114158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2596114158
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.276873347
Short name T824
Test name
Test status
Simulation time 595979386 ps
CPU time 1.17 seconds
Started Apr 15 03:27:49 PM PDT 24
Finished Apr 15 03:27:51 PM PDT 24
Peak memory 201324 kb
Host smart-75ffedc1-af56-48f0-aa24-f5f0ada43ab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276873347 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.276873347
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3054422801
Short name T93
Test name
Test status
Simulation time 366097825 ps
CPU time 0.96 seconds
Started Apr 15 03:27:52 PM PDT 24
Finished Apr 15 03:27:54 PM PDT 24
Peak memory 201252 kb
Host smart-29200409-826e-4e9b-ab3c-59faa49f9116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054422801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3054422801
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2935625766
Short name T853
Test name
Test status
Simulation time 528058016 ps
CPU time 1.25 seconds
Started Apr 15 03:27:48 PM PDT 24
Finished Apr 15 03:27:50 PM PDT 24
Peak memory 201280 kb
Host smart-72f49897-fcb2-4414-b8b8-4bb9ab3f2071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935625766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2935625766
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2326357564
Short name T887
Test name
Test status
Simulation time 2392444860 ps
CPU time 3.5 seconds
Started Apr 15 03:27:48 PM PDT 24
Finished Apr 15 03:27:52 PM PDT 24
Peak memory 201280 kb
Host smart-3418f04b-78b0-4eca-81e4-c80aed47d8e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326357564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2326357564
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1586667763
Short name T57
Test name
Test status
Simulation time 428513420 ps
CPU time 2.11 seconds
Started Apr 15 03:27:46 PM PDT 24
Finished Apr 15 03:27:49 PM PDT 24
Peak memory 201476 kb
Host smart-7c75ab6a-8a30-4505-a17e-e160f82f6e15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586667763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1586667763
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.676226766
Short name T48
Test name
Test status
Simulation time 8471748068 ps
CPU time 11.88 seconds
Started Apr 15 03:27:45 PM PDT 24
Finished Apr 15 03:27:58 PM PDT 24
Peak memory 201496 kb
Host smart-823bccbe-cb36-4de7-8753-9e4d57294503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676226766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.676226766
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2791333199
Short name T822
Test name
Test status
Simulation time 357752805 ps
CPU time 1.49 seconds
Started Apr 15 03:28:23 PM PDT 24
Finished Apr 15 03:28:25 PM PDT 24
Peak memory 201232 kb
Host smart-c4c41dd7-3275-4cb0-9b56-4207d98646b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791333199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2791333199
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2159093308
Short name T916
Test name
Test status
Simulation time 344868065 ps
CPU time 0.85 seconds
Started Apr 15 03:28:23 PM PDT 24
Finished Apr 15 03:28:24 PM PDT 24
Peak memory 201240 kb
Host smart-0769a13e-b1e1-47c3-876f-2837aa66dd16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159093308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2159093308
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.992980608
Short name T890
Test name
Test status
Simulation time 334733855 ps
CPU time 1.02 seconds
Started Apr 15 03:28:19 PM PDT 24
Finished Apr 15 03:28:20 PM PDT 24
Peak memory 201224 kb
Host smart-5a95c66c-1aeb-4dd6-81b4-271cf96ff4a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992980608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.992980608
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.350246607
Short name T912
Test name
Test status
Simulation time 316511068 ps
CPU time 1.01 seconds
Started Apr 15 03:28:18 PM PDT 24
Finished Apr 15 03:28:19 PM PDT 24
Peak memory 201244 kb
Host smart-1604c05e-78a0-4f27-97d1-c5ed6b41040e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350246607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.350246607
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.817942406
Short name T891
Test name
Test status
Simulation time 358702122 ps
CPU time 1.25 seconds
Started Apr 15 03:28:17 PM PDT 24
Finished Apr 15 03:28:19 PM PDT 24
Peak memory 201204 kb
Host smart-125d0f44-ae55-4638-a28b-48d8f1f83746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817942406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.817942406
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2319975212
Short name T896
Test name
Test status
Simulation time 508078521 ps
CPU time 1.78 seconds
Started Apr 15 03:28:17 PM PDT 24
Finished Apr 15 03:28:20 PM PDT 24
Peak memory 201240 kb
Host smart-cd73f26b-4af5-4e1f-8405-f2da6760cf86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319975212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2319975212
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3915866417
Short name T837
Test name
Test status
Simulation time 484407616 ps
CPU time 0.95 seconds
Started Apr 15 03:28:22 PM PDT 24
Finished Apr 15 03:28:23 PM PDT 24
Peak memory 201244 kb
Host smart-e6165989-07e6-4ce8-bee9-9d28c24a02dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915866417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3915866417
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3332324415
Short name T898
Test name
Test status
Simulation time 297376728 ps
CPU time 1.39 seconds
Started Apr 15 03:28:23 PM PDT 24
Finished Apr 15 03:28:25 PM PDT 24
Peak memory 201232 kb
Host smart-32f7f1a8-9feb-400c-aee0-2e0bc86a7af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332324415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3332324415
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2269709693
Short name T842
Test name
Test status
Simulation time 387894863 ps
CPU time 0.87 seconds
Started Apr 15 03:28:23 PM PDT 24
Finished Apr 15 03:28:25 PM PDT 24
Peak memory 201340 kb
Host smart-5626aaf6-f377-41e0-a9a5-b9520ed81e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269709693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2269709693
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3180737854
Short name T825
Test name
Test status
Simulation time 440810082 ps
CPU time 1.32 seconds
Started Apr 15 03:28:25 PM PDT 24
Finished Apr 15 03:28:27 PM PDT 24
Peak memory 201236 kb
Host smart-0e0a95ef-0439-4e9d-aab5-e225877c4bbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180737854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3180737854
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1755198653
Short name T816
Test name
Test status
Simulation time 1025709061 ps
CPU time 3.56 seconds
Started Apr 15 03:27:54 PM PDT 24
Finished Apr 15 03:27:58 PM PDT 24
Peak memory 201428 kb
Host smart-488fa7d6-aaf7-4819-8905-169c677de21d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755198653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1755198653
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2957415849
Short name T909
Test name
Test status
Simulation time 12093357732 ps
CPU time 15.55 seconds
Started Apr 15 03:27:56 PM PDT 24
Finished Apr 15 03:28:12 PM PDT 24
Peak memory 201476 kb
Host smart-fd50abb6-a9a2-440b-9da0-ac5e3b13e78b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957415849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2957415849
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2339924954
Short name T841
Test name
Test status
Simulation time 764078355 ps
CPU time 0.87 seconds
Started Apr 15 03:27:50 PM PDT 24
Finished Apr 15 03:27:51 PM PDT 24
Peak memory 201264 kb
Host smart-645fe69f-15f2-4c52-ac24-e5f0b0acc293
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339924954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2339924954
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2285695128
Short name T904
Test name
Test status
Simulation time 699847024 ps
CPU time 1.29 seconds
Started Apr 15 03:27:53 PM PDT 24
Finished Apr 15 03:27:55 PM PDT 24
Peak memory 201212 kb
Host smart-45b11706-2fe2-4f4c-ba00-b7ef9e7ced79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285695128 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2285695128
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2679476137
Short name T98
Test name
Test status
Simulation time 364349029 ps
CPU time 1.72 seconds
Started Apr 15 03:27:51 PM PDT 24
Finished Apr 15 03:27:54 PM PDT 24
Peak memory 201240 kb
Host smart-c7c8d5a0-5008-466f-a1a9-1089e04c9d52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679476137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2679476137
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1588756220
Short name T866
Test name
Test status
Simulation time 284966052 ps
CPU time 1.34 seconds
Started Apr 15 03:27:51 PM PDT 24
Finished Apr 15 03:27:53 PM PDT 24
Peak memory 201212 kb
Host smart-8b5ab7fc-a85e-4bd7-914c-f3b26518019e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588756220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1588756220
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.691309826
Short name T839
Test name
Test status
Simulation time 2561694272 ps
CPU time 5.44 seconds
Started Apr 15 03:27:56 PM PDT 24
Finished Apr 15 03:28:02 PM PDT 24
Peak memory 201308 kb
Host smart-4b2717fd-0af3-451e-b0f5-5a05b3e48a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691309826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.691309826
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2673976932
Short name T918
Test name
Test status
Simulation time 559595783 ps
CPU time 1.88 seconds
Started Apr 15 03:27:51 PM PDT 24
Finished Apr 15 03:27:53 PM PDT 24
Peak memory 201480 kb
Host smart-0a58e5c4-ddaf-4689-9a83-fb065cd22557
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673976932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2673976932
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2979385090
Short name T889
Test name
Test status
Simulation time 8747736804 ps
CPU time 13.03 seconds
Started Apr 15 03:27:50 PM PDT 24
Finished Apr 15 03:28:04 PM PDT 24
Peak memory 201500 kb
Host smart-d2f60129-b6b3-41dd-8783-56bd00fd1f5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979385090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2979385090
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1753574858
Short name T846
Test name
Test status
Simulation time 543166930 ps
CPU time 0.93 seconds
Started Apr 15 03:28:22 PM PDT 24
Finished Apr 15 03:28:24 PM PDT 24
Peak memory 201228 kb
Host smart-2e0c551e-0302-4f30-83c8-fd8d536f6b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753574858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1753574858
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3288508418
Short name T854
Test name
Test status
Simulation time 411101491 ps
CPU time 1.61 seconds
Started Apr 15 03:28:26 PM PDT 24
Finished Apr 15 03:28:29 PM PDT 24
Peak memory 201268 kb
Host smart-efb2a690-8704-4be7-81b8-97978d8ca0df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288508418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3288508418
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1746603201
Short name T811
Test name
Test status
Simulation time 541053814 ps
CPU time 1.23 seconds
Started Apr 15 03:28:22 PM PDT 24
Finished Apr 15 03:28:24 PM PDT 24
Peak memory 201172 kb
Host smart-ee4a2d76-c49a-41d4-9842-1118fd42ee70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746603201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1746603201
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1186223371
Short name T807
Test name
Test status
Simulation time 318559883 ps
CPU time 1.43 seconds
Started Apr 15 03:28:21 PM PDT 24
Finished Apr 15 03:28:24 PM PDT 24
Peak memory 201256 kb
Host smart-2e8ff94d-6ef6-4e57-a04b-d519707f792c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186223371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1186223371
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3649707174
Short name T836
Test name
Test status
Simulation time 380165943 ps
CPU time 1.41 seconds
Started Apr 15 03:28:26 PM PDT 24
Finished Apr 15 03:28:28 PM PDT 24
Peak memory 201244 kb
Host smart-512a5929-0908-48d3-b8e0-26013fdead5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649707174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3649707174
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2932057449
Short name T835
Test name
Test status
Simulation time 323929095 ps
CPU time 1.17 seconds
Started Apr 15 03:28:21 PM PDT 24
Finished Apr 15 03:28:23 PM PDT 24
Peak memory 201244 kb
Host smart-de1e6a69-b223-4c95-8186-48a7cae6ea4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932057449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2932057449
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1886460912
Short name T886
Test name
Test status
Simulation time 535182035 ps
CPU time 0.75 seconds
Started Apr 15 03:28:20 PM PDT 24
Finished Apr 15 03:28:22 PM PDT 24
Peak memory 201212 kb
Host smart-cfab1c1e-3807-41dc-b738-91010bb6f556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886460912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1886460912
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3385527177
Short name T805
Test name
Test status
Simulation time 454357555 ps
CPU time 0.92 seconds
Started Apr 15 03:28:25 PM PDT 24
Finished Apr 15 03:28:26 PM PDT 24
Peak memory 201228 kb
Host smart-67a5d421-b7b6-4110-b91e-612fd788f6c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385527177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3385527177
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1209116715
Short name T801
Test name
Test status
Simulation time 362719978 ps
CPU time 1.29 seconds
Started Apr 15 03:28:27 PM PDT 24
Finished Apr 15 03:28:29 PM PDT 24
Peak memory 201240 kb
Host smart-bd0258c2-c42c-4bb2-9c57-3b7111e05aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209116715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1209116715
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1013926865
Short name T823
Test name
Test status
Simulation time 484300775 ps
CPU time 0.97 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:28:31 PM PDT 24
Peak memory 201200 kb
Host smart-00be190a-3cb1-4124-9625-c1f5b319d904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013926865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1013926865
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2518805035
Short name T99
Test name
Test status
Simulation time 819810846 ps
CPU time 4.67 seconds
Started Apr 15 03:28:01 PM PDT 24
Finished Apr 15 03:28:06 PM PDT 24
Peak memory 201460 kb
Host smart-4709bd45-1bde-45b2-96bd-7f6ab32bb113
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518805035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2518805035
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4050722383
Short name T827
Test name
Test status
Simulation time 26688824804 ps
CPU time 10.93 seconds
Started Apr 15 03:27:59 PM PDT 24
Finished Apr 15 03:28:10 PM PDT 24
Peak memory 201516 kb
Host smart-c7c59190-0e59-4dcc-af42-93360e59df96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050722383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.4050722383
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4067143522
Short name T112
Test name
Test status
Simulation time 753413512 ps
CPU time 2.45 seconds
Started Apr 15 03:27:56 PM PDT 24
Finished Apr 15 03:27:59 PM PDT 24
Peak memory 201196 kb
Host smart-9fdd7d3e-3bd9-4e0e-a51d-10e16a917995
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067143522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4067143522
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4045246810
Short name T875
Test name
Test status
Simulation time 499823776 ps
CPU time 1.18 seconds
Started Apr 15 03:27:57 PM PDT 24
Finished Apr 15 03:27:59 PM PDT 24
Peak memory 201296 kb
Host smart-646009a7-d19a-49b9-b6e7-ea795a204278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045246810 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.4045246810
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3128212309
Short name T907
Test name
Test status
Simulation time 504850522 ps
CPU time 1.95 seconds
Started Apr 15 03:27:56 PM PDT 24
Finished Apr 15 03:27:59 PM PDT 24
Peak memory 201200 kb
Host smart-da4b747c-ff43-4fcc-ac3f-5de8478e6819
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128212309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3128212309
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2559387445
Short name T885
Test name
Test status
Simulation time 464438577 ps
CPU time 0.91 seconds
Started Apr 15 03:27:53 PM PDT 24
Finished Apr 15 03:27:55 PM PDT 24
Peak memory 201236 kb
Host smart-c10e6e53-deed-42da-bce9-ee29931f45ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559387445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2559387445
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2032782864
Short name T110
Test name
Test status
Simulation time 4195226716 ps
CPU time 2.23 seconds
Started Apr 15 03:27:57 PM PDT 24
Finished Apr 15 03:28:00 PM PDT 24
Peak memory 201588 kb
Host smart-3ca08c93-35ab-42df-8385-e9e98420d521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032782864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2032782864
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1290512698
Short name T884
Test name
Test status
Simulation time 427759230 ps
CPU time 2.83 seconds
Started Apr 15 03:27:53 PM PDT 24
Finished Apr 15 03:27:56 PM PDT 24
Peak memory 201500 kb
Host smart-368dfb9a-00a4-4930-9cdd-2a13140124c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290512698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1290512698
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1429911096
Short name T810
Test name
Test status
Simulation time 446139912 ps
CPU time 0.96 seconds
Started Apr 15 03:28:23 PM PDT 24
Finished Apr 15 03:28:25 PM PDT 24
Peak memory 201224 kb
Host smart-205a75b9-2bd7-4866-9f5e-628ebda9c40b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429911096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1429911096
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3090726033
Short name T911
Test name
Test status
Simulation time 444136843 ps
CPU time 0.86 seconds
Started Apr 15 03:28:22 PM PDT 24
Finished Apr 15 03:28:24 PM PDT 24
Peak memory 201252 kb
Host smart-daf8fbf9-0d1d-40fb-a84e-b95bf8385e31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090726033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3090726033
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3946492021
Short name T818
Test name
Test status
Simulation time 420362202 ps
CPU time 1.21 seconds
Started Apr 15 03:28:25 PM PDT 24
Finished Apr 15 03:28:27 PM PDT 24
Peak memory 201228 kb
Host smart-921682ff-5920-4eb7-b2a2-a985fc91478b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946492021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3946492021
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.501916824
Short name T800
Test name
Test status
Simulation time 356180667 ps
CPU time 0.88 seconds
Started Apr 15 03:28:20 PM PDT 24
Finished Apr 15 03:28:22 PM PDT 24
Peak memory 201212 kb
Host smart-01614eef-6108-4fa7-ac5c-c1a61e6b18a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501916824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.501916824
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3789006407
Short name T826
Test name
Test status
Simulation time 340894053 ps
CPU time 1.08 seconds
Started Apr 15 03:28:28 PM PDT 24
Finished Apr 15 03:28:30 PM PDT 24
Peak memory 201232 kb
Host smart-1183ab84-7c97-4182-9a92-ee08d601f0c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789006407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3789006407
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1439260749
Short name T813
Test name
Test status
Simulation time 374599716 ps
CPU time 0.9 seconds
Started Apr 15 03:28:23 PM PDT 24
Finished Apr 15 03:28:24 PM PDT 24
Peak memory 201236 kb
Host smart-0fa860fd-416b-4521-91a9-e320d9f1bb6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439260749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1439260749
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1787314874
Short name T903
Test name
Test status
Simulation time 403775011 ps
CPU time 1.05 seconds
Started Apr 15 03:28:21 PM PDT 24
Finished Apr 15 03:28:23 PM PDT 24
Peak memory 201240 kb
Host smart-10321088-aaf9-486c-a0e7-141c7c3ac19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787314874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1787314874
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.346064227
Short name T908
Test name
Test status
Simulation time 369063541 ps
CPU time 0.8 seconds
Started Apr 15 03:28:21 PM PDT 24
Finished Apr 15 03:28:22 PM PDT 24
Peak memory 201232 kb
Host smart-8260c50d-3b88-43f1-9dd9-042bd6592eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346064227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.346064227
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1158294037
Short name T858
Test name
Test status
Simulation time 386647167 ps
CPU time 0.86 seconds
Started Apr 15 03:28:25 PM PDT 24
Finished Apr 15 03:28:26 PM PDT 24
Peak memory 201236 kb
Host smart-abdbfae1-f8a0-4df7-b018-0b0b6b3d0682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158294037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1158294037
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.720878891
Short name T814
Test name
Test status
Simulation time 352761762 ps
CPU time 1.47 seconds
Started Apr 15 03:28:28 PM PDT 24
Finished Apr 15 03:28:30 PM PDT 24
Peak memory 201208 kb
Host smart-17b026b1-077b-4596-aecb-7a0679f3fcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720878891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.720878891
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1015241598
Short name T75
Test name
Test status
Simulation time 606773425 ps
CPU time 1.21 seconds
Started Apr 15 03:28:50 PM PDT 24
Finished Apr 15 03:28:52 PM PDT 24
Peak memory 201292 kb
Host smart-85e2f291-3a57-4fa5-bc1b-7f98950db6e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015241598 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1015241598
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.272578086
Short name T102
Test name
Test status
Simulation time 390978744 ps
CPU time 1.68 seconds
Started Apr 15 03:28:01 PM PDT 24
Finished Apr 15 03:28:03 PM PDT 24
Peak memory 201224 kb
Host smart-a33059b1-3912-4c0e-a98c-eb70b6695b21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272578086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.272578086
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.168098269
Short name T808
Test name
Test status
Simulation time 466469475 ps
CPU time 1.74 seconds
Started Apr 15 03:27:58 PM PDT 24
Finished Apr 15 03:28:01 PM PDT 24
Peak memory 201232 kb
Host smart-faa0b5e4-aa56-4c6b-b152-06c460529eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168098269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.168098269
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3405914700
Short name T107
Test name
Test status
Simulation time 3924762154 ps
CPU time 15.49 seconds
Started Apr 15 03:27:56 PM PDT 24
Finished Apr 15 03:28:12 PM PDT 24
Peak memory 201484 kb
Host smart-5ee89b68-dacb-4c8d-b43a-89662cc7174a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405914700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3405914700
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2262944415
Short name T56
Test name
Test status
Simulation time 426609144 ps
CPU time 2.46 seconds
Started Apr 15 03:27:56 PM PDT 24
Finished Apr 15 03:28:00 PM PDT 24
Peak memory 217424 kb
Host smart-4d7a3351-1fb2-4715-a9e0-d17991044fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262944415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2262944415
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.249411309
Short name T874
Test name
Test status
Simulation time 8437310539 ps
CPU time 22.1 seconds
Started Apr 15 03:28:05 PM PDT 24
Finished Apr 15 03:28:28 PM PDT 24
Peak memory 201500 kb
Host smart-4afc2eb9-5860-4e86-8a5a-cecb73045797
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249411309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.249411309
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2497477944
Short name T815
Test name
Test status
Simulation time 395165680 ps
CPU time 1.71 seconds
Started Apr 15 03:28:01 PM PDT 24
Finished Apr 15 03:28:04 PM PDT 24
Peak memory 201292 kb
Host smart-3de7efcd-1b09-407c-8159-a2c457f32ebc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497477944 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2497477944
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3193737333
Short name T104
Test name
Test status
Simulation time 324419285 ps
CPU time 1.68 seconds
Started Apr 15 03:27:58 PM PDT 24
Finished Apr 15 03:28:01 PM PDT 24
Peak memory 201236 kb
Host smart-b34d351d-a930-4713-b256-40405ee0f473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193737333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3193737333
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.86831243
Short name T872
Test name
Test status
Simulation time 288387556 ps
CPU time 1 seconds
Started Apr 15 03:27:58 PM PDT 24
Finished Apr 15 03:27:59 PM PDT 24
Peak memory 201204 kb
Host smart-25f46086-fade-400e-8677-ba7e34879f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86831243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.86831243
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1028122671
Short name T838
Test name
Test status
Simulation time 4717826307 ps
CPU time 7.17 seconds
Started Apr 15 03:28:05 PM PDT 24
Finished Apr 15 03:28:12 PM PDT 24
Peak memory 201460 kb
Host smart-505b4b54-b1c7-4197-b0b5-1a02cea0317b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028122671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1028122671
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2863742242
Short name T852
Test name
Test status
Simulation time 532584396 ps
CPU time 2.03 seconds
Started Apr 15 03:27:57 PM PDT 24
Finished Apr 15 03:28:00 PM PDT 24
Peak memory 201512 kb
Host smart-c4ae1bdc-8142-4319-8ca8-074ed1d1d5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863742242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2863742242
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1156941630
Short name T864
Test name
Test status
Simulation time 8511014004 ps
CPU time 7.65 seconds
Started Apr 15 03:27:56 PM PDT 24
Finished Apr 15 03:28:05 PM PDT 24
Peak memory 201472 kb
Host smart-4d4bf7a8-1d22-4fc1-a358-9445d92251c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156941630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1156941630
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4165765927
Short name T867
Test name
Test status
Simulation time 659163894 ps
CPU time 1.25 seconds
Started Apr 15 03:28:00 PM PDT 24
Finished Apr 15 03:28:02 PM PDT 24
Peak memory 209688 kb
Host smart-fe626a37-27f5-46d3-87be-4bd5046779c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165765927 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4165765927
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2902814620
Short name T877
Test name
Test status
Simulation time 529495998 ps
CPU time 0.92 seconds
Started Apr 15 03:28:02 PM PDT 24
Finished Apr 15 03:28:03 PM PDT 24
Peak memory 201236 kb
Host smart-c0b8e316-6aec-4a49-b6d4-7b108594e436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902814620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2902814620
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3999872985
Short name T803
Test name
Test status
Simulation time 492083198 ps
CPU time 1.71 seconds
Started Apr 15 03:28:01 PM PDT 24
Finished Apr 15 03:28:03 PM PDT 24
Peak memory 201224 kb
Host smart-1785f194-be11-47aa-b4ad-40e2cdb1b96c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999872985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3999872985
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3531872199
Short name T108
Test name
Test status
Simulation time 4946594312 ps
CPU time 3.83 seconds
Started Apr 15 03:28:00 PM PDT 24
Finished Apr 15 03:28:05 PM PDT 24
Peak memory 201472 kb
Host smart-d047457b-333b-4b4c-9e22-eaa6e2ee0853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531872199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3531872199
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1264927139
Short name T832
Test name
Test status
Simulation time 412897372 ps
CPU time 2.74 seconds
Started Apr 15 03:27:58 PM PDT 24
Finished Apr 15 03:28:01 PM PDT 24
Peak memory 201492 kb
Host smart-e6dc83fe-5e96-49eb-ad7b-8e681c41a413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264927139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1264927139
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2365371521
Short name T352
Test name
Test status
Simulation time 9378489234 ps
CPU time 3.53 seconds
Started Apr 15 03:28:04 PM PDT 24
Finished Apr 15 03:28:09 PM PDT 24
Peak memory 201452 kb
Host smart-32cf2478-3390-4e51-857f-543a07cc3dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365371521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2365371521
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1020591182
Short name T857
Test name
Test status
Simulation time 453847077 ps
CPU time 2.16 seconds
Started Apr 15 03:28:01 PM PDT 24
Finished Apr 15 03:28:04 PM PDT 24
Peak memory 201320 kb
Host smart-bad4ec5d-c727-4d56-ae47-4ed163775a68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020591182 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1020591182
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3358557691
Short name T103
Test name
Test status
Simulation time 501952534 ps
CPU time 1.97 seconds
Started Apr 15 03:28:00 PM PDT 24
Finished Apr 15 03:28:03 PM PDT 24
Peak memory 201240 kb
Host smart-f34eb619-7a63-440f-a503-66ee1117dd3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358557691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3358557691
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1906001257
Short name T863
Test name
Test status
Simulation time 332055906 ps
CPU time 0.84 seconds
Started Apr 15 03:28:01 PM PDT 24
Finished Apr 15 03:28:03 PM PDT 24
Peak memory 201248 kb
Host smart-51034c97-576e-4929-ad46-1cadce1b8135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906001257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1906001257
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1418440384
Short name T915
Test name
Test status
Simulation time 2355681700 ps
CPU time 2.25 seconds
Started Apr 15 03:28:03 PM PDT 24
Finished Apr 15 03:28:05 PM PDT 24
Peak memory 201296 kb
Host smart-531a1b15-22e7-4468-abc3-cd686febd9a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418440384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1418440384
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2747226614
Short name T855
Test name
Test status
Simulation time 735975770 ps
CPU time 2.47 seconds
Started Apr 15 03:28:04 PM PDT 24
Finished Apr 15 03:28:07 PM PDT 24
Peak memory 201468 kb
Host smart-83c8c556-9713-4b7a-b25c-f5929aed6345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747226614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2747226614
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3100298632
Short name T828
Test name
Test status
Simulation time 4717656743 ps
CPU time 5.42 seconds
Started Apr 15 03:28:00 PM PDT 24
Finished Apr 15 03:28:07 PM PDT 24
Peak memory 201500 kb
Host smart-5275bae3-6c3a-46d4-bff6-41b9575b16b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100298632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3100298632
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.310437832
Short name T869
Test name
Test status
Simulation time 570385858 ps
CPU time 2.28 seconds
Started Apr 15 03:28:09 PM PDT 24
Finished Apr 15 03:28:12 PM PDT 24
Peak memory 201292 kb
Host smart-741894e7-1553-47b6-8691-25bc644b0a23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310437832 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.310437832
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2076936427
Short name T97
Test name
Test status
Simulation time 509085177 ps
CPU time 1.24 seconds
Started Apr 15 03:28:09 PM PDT 24
Finished Apr 15 03:28:11 PM PDT 24
Peak memory 201252 kb
Host smart-cb1c9ed6-c8a9-4ab3-b177-12fa0ba0baaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076936427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2076936427
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1852862554
Short name T888
Test name
Test status
Simulation time 450740002 ps
CPU time 1.72 seconds
Started Apr 15 03:28:03 PM PDT 24
Finished Apr 15 03:28:05 PM PDT 24
Peak memory 201236 kb
Host smart-610eea67-0d47-4fed-8152-5ac70f58bea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852862554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1852862554
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.942751857
Short name T109
Test name
Test status
Simulation time 4543167892 ps
CPU time 18.9 seconds
Started Apr 15 03:28:06 PM PDT 24
Finished Apr 15 03:28:26 PM PDT 24
Peak memory 201460 kb
Host smart-c556a099-c484-4fd1-a906-dfb90963c2c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942751857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.942751857
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4282265515
Short name T52
Test name
Test status
Simulation time 856359335 ps
CPU time 3.2 seconds
Started Apr 15 03:28:01 PM PDT 24
Finished Apr 15 03:28:05 PM PDT 24
Peak memory 201544 kb
Host smart-c986e597-56d1-4d63-b9ec-b9317909c0ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282265515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.4282265515
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2888825850
Short name T892
Test name
Test status
Simulation time 7618826430 ps
CPU time 7 seconds
Started Apr 15 03:28:04 PM PDT 24
Finished Apr 15 03:28:12 PM PDT 24
Peak memory 201452 kb
Host smart-ca1ff282-6998-4007-91c2-275b8af48410
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888825850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2888825850
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1671772659
Short name T774
Test name
Test status
Simulation time 347739662 ps
CPU time 1.47 seconds
Started Apr 15 12:50:34 PM PDT 24
Finished Apr 15 12:50:36 PM PDT 24
Peak memory 202000 kb
Host smart-9a9de062-11c0-4a07-922b-5b320f114a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671772659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1671772659
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1845790867
Short name T652
Test name
Test status
Simulation time 354794333660 ps
CPU time 797.61 seconds
Started Apr 15 12:50:30 PM PDT 24
Finished Apr 15 01:03:48 PM PDT 24
Peak memory 202268 kb
Host smart-7b4a3e1a-892c-4dba-b78c-a3fb26e4988d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845790867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1845790867
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.403997821
Short name T712
Test name
Test status
Simulation time 500049203948 ps
CPU time 1164.14 seconds
Started Apr 15 12:50:27 PM PDT 24
Finished Apr 15 01:09:52 PM PDT 24
Peak memory 202204 kb
Host smart-d045344f-6292-46db-8975-7468174be2d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=403997821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.403997821
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1259705853
Short name T580
Test name
Test status
Simulation time 162445073452 ps
CPU time 210.77 seconds
Started Apr 15 12:50:29 PM PDT 24
Finished Apr 15 12:54:00 PM PDT 24
Peak memory 202136 kb
Host smart-876a4f55-f30c-43d2-b496-a8f8d4bab901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259705853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1259705853
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1676441964
Short name T383
Test name
Test status
Simulation time 161136323154 ps
CPU time 94.68 seconds
Started Apr 15 12:50:31 PM PDT 24
Finished Apr 15 12:52:06 PM PDT 24
Peak memory 202308 kb
Host smart-612c602d-e586-4d25-92e6-d336bec90034
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676441964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1676441964
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2236408614
Short name T326
Test name
Test status
Simulation time 162573836595 ps
CPU time 348.81 seconds
Started Apr 15 12:50:31 PM PDT 24
Finished Apr 15 12:56:20 PM PDT 24
Peak memory 202348 kb
Host smart-82b8cf10-0471-46f0-97d8-d20e9bf3f624
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236408614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2236408614
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3711132620
Short name T509
Test name
Test status
Simulation time 615711201608 ps
CPU time 1392.97 seconds
Started Apr 15 12:50:39 PM PDT 24
Finished Apr 15 01:13:52 PM PDT 24
Peak memory 202236 kb
Host smart-9cef3e08-c07f-49f5-a019-595dda02a83d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711132620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3711132620
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2951808486
Short name T478
Test name
Test status
Simulation time 113586375693 ps
CPU time 385.66 seconds
Started Apr 15 12:50:32 PM PDT 24
Finished Apr 15 12:56:58 PM PDT 24
Peak memory 202700 kb
Host smart-61032f45-df67-45ad-8f75-522231b9ec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951808486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2951808486
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2296126181
Short name T625
Test name
Test status
Simulation time 36104500651 ps
CPU time 19.36 seconds
Started Apr 15 12:50:33 PM PDT 24
Finished Apr 15 12:50:53 PM PDT 24
Peak memory 202068 kb
Host smart-4fabda03-36ed-45b5-bf3e-b3c750a21b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296126181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2296126181
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3740256452
Short name T797
Test name
Test status
Simulation time 5187959561 ps
CPU time 13.56 seconds
Started Apr 15 12:50:33 PM PDT 24
Finished Apr 15 12:50:47 PM PDT 24
Peak memory 202044 kb
Host smart-244f6ca3-dd2e-4dfa-bd4a-ab89c0b79b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740256452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3740256452
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.4259948957
Short name T70
Test name
Test status
Simulation time 5912158222 ps
CPU time 7.74 seconds
Started Apr 15 12:50:28 PM PDT 24
Finished Apr 15 12:50:36 PM PDT 24
Peak memory 201900 kb
Host smart-e18d7b5e-dc58-4e25-8580-89af94dcbda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259948957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.4259948957
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.4092019823
Short name T28
Test name
Test status
Simulation time 654258078734 ps
CPU time 781.59 seconds
Started Apr 15 12:50:35 PM PDT 24
Finished Apr 15 01:03:37 PM PDT 24
Peak memory 202224 kb
Host smart-f761507d-28de-42d7-99df-405b36273cb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092019823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
4092019823
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4799617
Short name T79
Test name
Test status
Simulation time 137386402136 ps
CPU time 187.21 seconds
Started Apr 15 12:50:35 PM PDT 24
Finished Apr 15 12:53:42 PM PDT 24
Peak memory 218412 kb
Host smart-8c3ce480-3cf0-4fe7-81fa-fdfab540d487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4799617 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4799617
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.64975124
Short name T570
Test name
Test status
Simulation time 356249097366 ps
CPU time 464.77 seconds
Started Apr 15 12:50:38 PM PDT 24
Finished Apr 15 12:58:23 PM PDT 24
Peak memory 202080 kb
Host smart-9ec66820-709c-4e17-93c1-02f657f95546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64975124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.64975124
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.485603287
Short name T736
Test name
Test status
Simulation time 165844168167 ps
CPU time 389.06 seconds
Started Apr 15 12:50:35 PM PDT 24
Finished Apr 15 12:57:04 PM PDT 24
Peak memory 202264 kb
Host smart-9cb556bc-550e-4300-a00f-101edbf0a4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485603287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.485603287
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.4247961659
Short name T572
Test name
Test status
Simulation time 326825385011 ps
CPU time 831.23 seconds
Started Apr 15 12:50:33 PM PDT 24
Finished Apr 15 01:04:25 PM PDT 24
Peak memory 202356 kb
Host smart-249b7e4f-8afe-4bf3-b325-768b7910c964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247961659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.4247961659
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.523518983
Short name T568
Test name
Test status
Simulation time 495859440212 ps
CPU time 1028.1 seconds
Started Apr 15 12:50:33 PM PDT 24
Finished Apr 15 01:07:41 PM PDT 24
Peak memory 202328 kb
Host smart-b6850b06-c486-4f9a-b0ac-333a854cc079
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=523518983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.523518983
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.433207657
Short name T689
Test name
Test status
Simulation time 176608057126 ps
CPU time 104.46 seconds
Started Apr 15 12:50:33 PM PDT 24
Finished Apr 15 12:52:18 PM PDT 24
Peak memory 202256 kb
Host smart-eb9514ff-007c-40d6-88bc-accaccf4749d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433207657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.433207657
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4023482529
Short name T488
Test name
Test status
Simulation time 196732622297 ps
CPU time 501.6 seconds
Started Apr 15 12:50:38 PM PDT 24
Finished Apr 15 12:59:00 PM PDT 24
Peak memory 202288 kb
Host smart-a7eb2daa-f126-44a2-b489-8ffba0dd4f28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023482529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4023482529
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2678095755
Short name T690
Test name
Test status
Simulation time 75321950924 ps
CPU time 319.02 seconds
Started Apr 15 12:50:42 PM PDT 24
Finished Apr 15 12:56:02 PM PDT 24
Peak memory 202560 kb
Host smart-040a1762-cf91-4c7c-bf38-37f83ca6f61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678095755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2678095755
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3253288962
Short name T396
Test name
Test status
Simulation time 26982922647 ps
CPU time 12.4 seconds
Started Apr 15 12:50:38 PM PDT 24
Finished Apr 15 12:50:50 PM PDT 24
Peak memory 202016 kb
Host smart-6d4e0569-6663-4eed-b692-11226f4255df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253288962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3253288962
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.824783923
Short name T420
Test name
Test status
Simulation time 4540559603 ps
CPU time 10.65 seconds
Started Apr 15 12:50:40 PM PDT 24
Finished Apr 15 12:50:51 PM PDT 24
Peak memory 202068 kb
Host smart-71c29c35-de87-4761-b366-ee552d240233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824783923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.824783923
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2572521346
Short name T54
Test name
Test status
Simulation time 7767472008 ps
CPU time 5.98 seconds
Started Apr 15 12:50:39 PM PDT 24
Finished Apr 15 12:50:45 PM PDT 24
Peak memory 218872 kb
Host smart-5bc50e29-8923-4871-8d2c-54795537033b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572521346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2572521346
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.952533403
Short name T637
Test name
Test status
Simulation time 6080856943 ps
CPU time 4.79 seconds
Started Apr 15 12:50:33 PM PDT 24
Finished Apr 15 12:50:38 PM PDT 24
Peak memory 202076 kb
Host smart-573f212c-f449-40d4-a708-9cdd619840ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952533403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.952533403
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2375961095
Short name T270
Test name
Test status
Simulation time 445086495761 ps
CPU time 1224.41 seconds
Started Apr 15 12:50:39 PM PDT 24
Finished Apr 15 01:11:04 PM PDT 24
Peak memory 218936 kb
Host smart-ec8d933e-847d-49d1-aadc-e1e017373fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375961095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2375961095
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2085821414
Short name T19
Test name
Test status
Simulation time 77442173199 ps
CPU time 211.84 seconds
Started Apr 15 12:50:39 PM PDT 24
Finished Apr 15 12:54:12 PM PDT 24
Peak memory 210956 kb
Host smart-d259ad36-f953-4e35-aada-a243ac50048c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085821414 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2085821414
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.745985842
Short name T607
Test name
Test status
Simulation time 544280457 ps
CPU time 0.89 seconds
Started Apr 15 12:51:23 PM PDT 24
Finished Apr 15 12:51:25 PM PDT 24
Peak memory 201960 kb
Host smart-6aa1a148-73b9-4998-9c9d-6112b8a829e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745985842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.745985842
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1859987791
Short name T402
Test name
Test status
Simulation time 163803329606 ps
CPU time 177.72 seconds
Started Apr 15 12:51:23 PM PDT 24
Finished Apr 15 12:54:21 PM PDT 24
Peak memory 202232 kb
Host smart-5154dc77-6585-484d-95ff-48d11de65b93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859987791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1859987791
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1339311420
Short name T131
Test name
Test status
Simulation time 327135354433 ps
CPU time 767.59 seconds
Started Apr 15 12:51:20 PM PDT 24
Finished Apr 15 01:04:09 PM PDT 24
Peak memory 202316 kb
Host smart-68b39a30-b89a-41bd-adac-cfce115dfd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339311420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1339311420
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3599187146
Short name T552
Test name
Test status
Simulation time 491163431878 ps
CPU time 594.37 seconds
Started Apr 15 12:51:21 PM PDT 24
Finished Apr 15 01:01:16 PM PDT 24
Peak memory 202204 kb
Host smart-ed1ae53b-48d8-4d79-a00c-f4d29a2d822b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599187146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3599187146
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.556006215
Short name T639
Test name
Test status
Simulation time 198121143688 ps
CPU time 438.73 seconds
Started Apr 15 12:51:24 PM PDT 24
Finished Apr 15 12:58:43 PM PDT 24
Peak memory 202188 kb
Host smart-f3506fb5-63e8-48ad-a1a8-ec00659d02fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556006215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.556006215
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1585579515
Short name T754
Test name
Test status
Simulation time 70133659609 ps
CPU time 293.1 seconds
Started Apr 15 12:51:25 PM PDT 24
Finished Apr 15 12:56:18 PM PDT 24
Peak memory 202632 kb
Host smart-2f43aa30-589f-4fdc-9fbb-543687e6cd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585579515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1585579515
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.955896910
Short name T474
Test name
Test status
Simulation time 33578906567 ps
CPU time 40.54 seconds
Started Apr 15 12:51:23 PM PDT 24
Finished Apr 15 12:52:04 PM PDT 24
Peak memory 202092 kb
Host smart-8adfcf8d-9a4e-4a44-a224-87e233a7dd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955896910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.955896910
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1397294928
Short name T633
Test name
Test status
Simulation time 4593279197 ps
CPU time 11.48 seconds
Started Apr 15 12:51:24 PM PDT 24
Finished Apr 15 12:51:36 PM PDT 24
Peak memory 202076 kb
Host smart-6fad8a5b-92db-4477-b45a-21511ee54e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397294928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1397294928
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3251452379
Short name T576
Test name
Test status
Simulation time 6086575322 ps
CPU time 14.08 seconds
Started Apr 15 12:51:18 PM PDT 24
Finished Apr 15 12:51:33 PM PDT 24
Peak memory 202100 kb
Host smart-2ba44ea8-a4bc-43a3-af93-01a619225105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251452379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3251452379
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3160690766
Short name T136
Test name
Test status
Simulation time 222991592029 ps
CPU time 131.24 seconds
Started Apr 15 12:51:25 PM PDT 24
Finished Apr 15 12:53:37 PM PDT 24
Peak memory 202360 kb
Host smart-7624dcb4-1802-4765-9d5d-1e3bb1388e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160690766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3160690766
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1482468444
Short name T13
Test name
Test status
Simulation time 221916278303 ps
CPU time 68.21 seconds
Started Apr 15 12:51:24 PM PDT 24
Finished Apr 15 12:52:33 PM PDT 24
Peak memory 202392 kb
Host smart-5a906526-083e-458f-a622-afbac0d565bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482468444 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1482468444
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.4213130213
Short name T750
Test name
Test status
Simulation time 352868419 ps
CPU time 1.39 seconds
Started Apr 15 12:51:31 PM PDT 24
Finished Apr 15 12:51:32 PM PDT 24
Peak memory 201988 kb
Host smart-59db58a7-0e7b-488d-a834-f18e6234550b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213130213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4213130213
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3683604020
Short name T137
Test name
Test status
Simulation time 578330455241 ps
CPU time 998.25 seconds
Started Apr 15 12:51:30 PM PDT 24
Finished Apr 15 01:08:09 PM PDT 24
Peak memory 202216 kb
Host smart-b712d088-2741-4e50-a1d8-b68fb7318fdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683604020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3683604020
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2142874399
Short name T697
Test name
Test status
Simulation time 191411000107 ps
CPU time 435.59 seconds
Started Apr 15 12:51:33 PM PDT 24
Finished Apr 15 12:58:49 PM PDT 24
Peak memory 202336 kb
Host smart-5897379e-31de-456e-b88f-5d8fcd5c5f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142874399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2142874399
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3962593134
Short name T276
Test name
Test status
Simulation time 483200083011 ps
CPU time 281.11 seconds
Started Apr 15 12:51:33 PM PDT 24
Finished Apr 15 12:56:15 PM PDT 24
Peak memory 202292 kb
Host smart-95c175ac-f5bb-41f9-98f5-9c5d6a66d6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962593134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3962593134
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2415155239
Short name T419
Test name
Test status
Simulation time 331334964294 ps
CPU time 213.54 seconds
Started Apr 15 12:51:30 PM PDT 24
Finished Apr 15 12:55:04 PM PDT 24
Peak memory 202324 kb
Host smart-dcd1f9ef-636b-4042-a3bc-8557cbf9cfde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415155239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2415155239
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.541434001
Short name T290
Test name
Test status
Simulation time 484937721207 ps
CPU time 1063.76 seconds
Started Apr 15 12:51:33 PM PDT 24
Finished Apr 15 01:09:17 PM PDT 24
Peak memory 202260 kb
Host smart-e3c35da2-f52b-4ded-bd21-392650b15dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541434001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.541434001
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1797061766
Short name T194
Test name
Test status
Simulation time 331402025739 ps
CPU time 295.05 seconds
Started Apr 15 12:51:28 PM PDT 24
Finished Apr 15 12:56:24 PM PDT 24
Peak memory 202248 kb
Host smart-305cb453-7211-46e1-a12a-0cbbcc5a5ba6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797061766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1797061766
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.664939277
Short name T185
Test name
Test status
Simulation time 198139919639 ps
CPU time 104.82 seconds
Started Apr 15 12:51:30 PM PDT 24
Finished Apr 15 12:53:16 PM PDT 24
Peak memory 202288 kb
Host smart-33bfa6fa-afcc-475b-9465-fd8edd9b6fe3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664939277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.664939277
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1302650329
Short name T510
Test name
Test status
Simulation time 201949294056 ps
CPU time 460.51 seconds
Started Apr 15 12:51:33 PM PDT 24
Finished Apr 15 12:59:14 PM PDT 24
Peak memory 202296 kb
Host smart-63be2434-f83a-4ce5-8412-058f0b7717e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302650329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1302650329
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3319425985
Short name T525
Test name
Test status
Simulation time 92779342189 ps
CPU time 335.46 seconds
Started Apr 15 12:51:30 PM PDT 24
Finished Apr 15 12:57:06 PM PDT 24
Peak memory 202608 kb
Host smart-908a01be-9fc4-42ce-b3bc-5002e1c0a211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319425985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3319425985
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1212557244
Short name T473
Test name
Test status
Simulation time 23774143740 ps
CPU time 54.47 seconds
Started Apr 15 12:51:29 PM PDT 24
Finished Apr 15 12:52:24 PM PDT 24
Peak memory 202036 kb
Host smart-1ddd74dd-d5c4-4779-ad15-dd3fae8b6122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212557244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1212557244
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.352726710
Short name T471
Test name
Test status
Simulation time 4132115401 ps
CPU time 10.46 seconds
Started Apr 15 12:51:30 PM PDT 24
Finished Apr 15 12:51:41 PM PDT 24
Peak memory 202064 kb
Host smart-1c14b75f-7362-4cee-8a7b-bd58f810653f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352726710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.352726710
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.457334549
Short name T404
Test name
Test status
Simulation time 5624088545 ps
CPU time 4.27 seconds
Started Apr 15 12:51:23 PM PDT 24
Finished Apr 15 12:51:28 PM PDT 24
Peak memory 202084 kb
Host smart-5861adbb-769b-4fcc-b828-4a00c8b0cdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457334549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.457334549
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1595942506
Short name T586
Test name
Test status
Simulation time 1210930379 ps
CPU time 1.95 seconds
Started Apr 15 12:51:31 PM PDT 24
Finished Apr 15 12:51:33 PM PDT 24
Peak memory 201960 kb
Host smart-20464f89-3550-4da5-bded-558339edbd14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595942506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1595942506
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2725507811
Short name T287
Test name
Test status
Simulation time 271523706511 ps
CPU time 196.01 seconds
Started Apr 15 12:51:31 PM PDT 24
Finished Apr 15 12:54:47 PM PDT 24
Peak memory 210884 kb
Host smart-10b0a3c5-7174-493c-b540-b039a60b0809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725507811 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2725507811
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2757754830
Short name T433
Test name
Test status
Simulation time 406803640 ps
CPU time 0.88 seconds
Started Apr 15 12:51:37 PM PDT 24
Finished Apr 15 12:51:38 PM PDT 24
Peak memory 201956 kb
Host smart-de2be13f-ec75-484f-b5b1-3f3edd2c64ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757754830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2757754830
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.4130627345
Short name T69
Test name
Test status
Simulation time 437912756065 ps
CPU time 374.16 seconds
Started Apr 15 12:51:33 PM PDT 24
Finished Apr 15 12:57:48 PM PDT 24
Peak memory 202220 kb
Host smart-245e1dee-4888-4756-b6a2-195559c4ef6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130627345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.4130627345
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.945656571
Short name T589
Test name
Test status
Simulation time 162868355104 ps
CPU time 405.76 seconds
Started Apr 15 12:51:34 PM PDT 24
Finished Apr 15 12:58:20 PM PDT 24
Peak memory 202248 kb
Host smart-68dc54fc-7055-46c5-9d01-04cb5ec68471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945656571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.945656571
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2127598039
Short name T472
Test name
Test status
Simulation time 330740426591 ps
CPU time 121.63 seconds
Started Apr 15 12:51:33 PM PDT 24
Finished Apr 15 12:53:36 PM PDT 24
Peak memory 202228 kb
Host smart-e45dd875-f6c1-4b5f-b183-4efef73a87f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127598039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2127598039
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.732923781
Short name T178
Test name
Test status
Simulation time 160014893485 ps
CPU time 401.65 seconds
Started Apr 15 12:51:30 PM PDT 24
Finished Apr 15 12:58:12 PM PDT 24
Peak memory 202528 kb
Host smart-b75b9376-a6dd-4e37-84d7-9eaa778af870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732923781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.732923781
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.536005707
Short name T780
Test name
Test status
Simulation time 164844326379 ps
CPU time 190.27 seconds
Started Apr 15 12:51:32 PM PDT 24
Finished Apr 15 12:54:42 PM PDT 24
Peak memory 202232 kb
Host smart-e8860ec3-04b4-4cac-bc85-c9054de28023
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=536005707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.536005707
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3655099845
Short name T536
Test name
Test status
Simulation time 394584822607 ps
CPU time 67.37 seconds
Started Apr 15 12:51:34 PM PDT 24
Finished Apr 15 12:52:42 PM PDT 24
Peak memory 202096 kb
Host smart-b97dd5df-bf55-43a5-bf1b-5d2a3362e2ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655099845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3655099845
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3506364248
Short name T761
Test name
Test status
Simulation time 101448185460 ps
CPU time 498 seconds
Started Apr 15 12:51:37 PM PDT 24
Finished Apr 15 12:59:55 PM PDT 24
Peak memory 202588 kb
Host smart-9cf4ef57-1209-4205-9245-62cd3b7f86d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506364248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3506364248
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3939263070
Short name T584
Test name
Test status
Simulation time 44716533979 ps
CPU time 25.9 seconds
Started Apr 15 12:51:33 PM PDT 24
Finished Apr 15 12:51:59 PM PDT 24
Peak memory 202072 kb
Host smart-a4ba24e3-68f2-4c22-a237-536ecf31fe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939263070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3939263070
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3437994740
Short name T465
Test name
Test status
Simulation time 5063016181 ps
CPU time 11.74 seconds
Started Apr 15 12:51:33 PM PDT 24
Finished Apr 15 12:51:46 PM PDT 24
Peak memory 202012 kb
Host smart-b20c110f-9ae0-4c55-9f43-454ce1f7abf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437994740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3437994740
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.397714188
Short name T407
Test name
Test status
Simulation time 6035828993 ps
CPU time 8.37 seconds
Started Apr 15 12:51:28 PM PDT 24
Finished Apr 15 12:51:37 PM PDT 24
Peak memory 202072 kb
Host smart-812f3ec2-ae53-46e2-a3e8-de09d7c7b4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397714188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.397714188
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2929796555
Short name T263
Test name
Test status
Simulation time 146504458310 ps
CPU time 129.87 seconds
Started Apr 15 12:51:34 PM PDT 24
Finished Apr 15 12:53:44 PM PDT 24
Peak memory 218432 kb
Host smart-e610e7f3-c19f-4040-aaa0-0e22b47a45fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929796555 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2929796555
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1135632320
Short name T385
Test name
Test status
Simulation time 476256414 ps
CPU time 1.6 seconds
Started Apr 15 12:51:39 PM PDT 24
Finished Apr 15 12:51:41 PM PDT 24
Peak memory 201972 kb
Host smart-c66934f7-2354-4804-b486-383eace50b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135632320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1135632320
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.16437099
Short name T288
Test name
Test status
Simulation time 165400471364 ps
CPU time 24.68 seconds
Started Apr 15 12:51:38 PM PDT 24
Finished Apr 15 12:52:04 PM PDT 24
Peak memory 202344 kb
Host smart-41c0c05a-780c-482e-bd15-2935fc7783f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16437099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gatin
g.16437099
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3117968238
Short name T3
Test name
Test status
Simulation time 359759790945 ps
CPU time 820.24 seconds
Started Apr 15 12:51:38 PM PDT 24
Finished Apr 15 01:05:20 PM PDT 24
Peak memory 202240 kb
Host smart-48b89d78-a2bc-47e5-aa5d-e485d8b5f51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117968238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3117968238
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2457566546
Short name T789
Test name
Test status
Simulation time 162170434112 ps
CPU time 398.46 seconds
Started Apr 15 12:51:34 PM PDT 24
Finished Apr 15 12:58:13 PM PDT 24
Peak memory 202240 kb
Host smart-470ef4f9-8efa-4813-a098-4dd9a0fb934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457566546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2457566546
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3636561945
Short name T760
Test name
Test status
Simulation time 325439913436 ps
CPU time 687.77 seconds
Started Apr 15 12:51:38 PM PDT 24
Finished Apr 15 01:03:06 PM PDT 24
Peak memory 202248 kb
Host smart-2cb44349-0be1-4327-911f-a2bb0be12bbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636561945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3636561945
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2549441027
Short name T329
Test name
Test status
Simulation time 337005245854 ps
CPU time 786.71 seconds
Started Apr 15 12:51:38 PM PDT 24
Finished Apr 15 01:04:46 PM PDT 24
Peak memory 202260 kb
Host smart-0daeac05-b834-4345-b4ff-09ad1f5848a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549441027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2549441027
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2464585358
Short name T598
Test name
Test status
Simulation time 486516534420 ps
CPU time 1177.65 seconds
Started Apr 15 12:51:34 PM PDT 24
Finished Apr 15 01:11:12 PM PDT 24
Peak memory 202316 kb
Host smart-911005cd-4d34-402c-99e4-c841f427c744
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464585358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2464585358
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2404394215
Short name T325
Test name
Test status
Simulation time 256194569793 ps
CPU time 144.84 seconds
Started Apr 15 12:51:37 PM PDT 24
Finished Apr 15 12:54:02 PM PDT 24
Peak memory 202336 kb
Host smart-2e95492a-6720-4764-8fd3-018eb16316c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404394215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2404394215
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2447336970
Short name T634
Test name
Test status
Simulation time 201706906446 ps
CPU time 159.64 seconds
Started Apr 15 12:51:38 PM PDT 24
Finished Apr 15 12:54:18 PM PDT 24
Peak memory 202220 kb
Host smart-4d0bfd1f-2f8e-4900-80ac-0937b8e46f8c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447336970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2447336970
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.69954618
Short name T709
Test name
Test status
Simulation time 93671498061 ps
CPU time 388.79 seconds
Started Apr 15 12:51:36 PM PDT 24
Finished Apr 15 12:58:06 PM PDT 24
Peak memory 202548 kb
Host smart-bb9a3ef2-c774-4f48-9c0f-b75677b0a7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69954618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.69954618
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.170393904
Short name T724
Test name
Test status
Simulation time 22244574555 ps
CPU time 13.14 seconds
Started Apr 15 12:51:38 PM PDT 24
Finished Apr 15 12:51:51 PM PDT 24
Peak memory 202064 kb
Host smart-a79c8212-71cf-4370-a236-670edbae6790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170393904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.170393904
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2087929311
Short name T506
Test name
Test status
Simulation time 4988149995 ps
CPU time 12.47 seconds
Started Apr 15 12:51:37 PM PDT 24
Finished Apr 15 12:51:50 PM PDT 24
Peak memory 202104 kb
Host smart-3518f2b4-187d-44c7-81f2-199437af0600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087929311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2087929311
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2071842696
Short name T543
Test name
Test status
Simulation time 6080727224 ps
CPU time 8.38 seconds
Started Apr 15 12:51:35 PM PDT 24
Finished Apr 15 12:51:44 PM PDT 24
Peak memory 202056 kb
Host smart-da108af7-9b97-4bd1-aa47-5a4a87e8ee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071842696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2071842696
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.637339235
Short name T248
Test name
Test status
Simulation time 340633348549 ps
CPU time 780.15 seconds
Started Apr 15 12:51:37 PM PDT 24
Finished Apr 15 01:04:37 PM PDT 24
Peak memory 202392 kb
Host smart-6d480e60-bf01-43ad-b174-512b1a1ec27d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637339235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
637339235
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2748072328
Short name T16
Test name
Test status
Simulation time 340153048511 ps
CPU time 344.29 seconds
Started Apr 15 12:51:39 PM PDT 24
Finished Apr 15 12:57:24 PM PDT 24
Peak memory 210988 kb
Host smart-7d9bdf9f-b1a4-43a7-bf57-896b2e00a342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748072328 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2748072328
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2885226552
Short name T398
Test name
Test status
Simulation time 401821735 ps
CPU time 1.08 seconds
Started Apr 15 12:51:48 PM PDT 24
Finished Apr 15 12:51:49 PM PDT 24
Peak memory 201980 kb
Host smart-3a2ff46f-8e9d-4752-ad72-935ce90b0169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885226552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2885226552
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3261946214
Short name T186
Test name
Test status
Simulation time 181544023456 ps
CPU time 453.69 seconds
Started Apr 15 12:51:43 PM PDT 24
Finished Apr 15 12:59:17 PM PDT 24
Peak memory 202248 kb
Host smart-dce34488-9575-48ac-9a8a-d5b197211e80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261946214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3261946214
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1044842577
Short name T521
Test name
Test status
Simulation time 327210152299 ps
CPU time 671.05 seconds
Started Apr 15 12:51:43 PM PDT 24
Finished Apr 15 01:02:54 PM PDT 24
Peak memory 202276 kb
Host smart-0506fd7e-457a-41f2-9dc2-f828cf549e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044842577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1044842577
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3149388129
Short name T68
Test name
Test status
Simulation time 165602437957 ps
CPU time 105.59 seconds
Started Apr 15 12:51:44 PM PDT 24
Finished Apr 15 12:53:30 PM PDT 24
Peak memory 202300 kb
Host smart-3de2da82-1e4f-41c9-818c-6dd49a356520
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149388129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3149388129
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2791542937
Short name T337
Test name
Test status
Simulation time 336404473378 ps
CPU time 797.33 seconds
Started Apr 15 12:51:45 PM PDT 24
Finished Apr 15 01:05:03 PM PDT 24
Peak memory 202344 kb
Host smart-eb6210a0-a13a-4b42-855a-ff998316b2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791542937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2791542937
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.943767810
Short name T653
Test name
Test status
Simulation time 495540174783 ps
CPU time 1031.29 seconds
Started Apr 15 12:51:42 PM PDT 24
Finished Apr 15 01:08:53 PM PDT 24
Peak memory 202244 kb
Host smart-16bea272-bec4-4ae0-bea9-693416992e9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=943767810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.943767810
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2458375644
Short name T729
Test name
Test status
Simulation time 196956341184 ps
CPU time 84.89 seconds
Started Apr 15 12:51:42 PM PDT 24
Finished Apr 15 12:53:07 PM PDT 24
Peak memory 202336 kb
Host smart-7920cb22-57ad-407e-9576-b0b04f91dd87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458375644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2458375644
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.602614819
Short name T711
Test name
Test status
Simulation time 192491949510 ps
CPU time 386.77 seconds
Started Apr 15 12:51:42 PM PDT 24
Finished Apr 15 12:58:09 PM PDT 24
Peak memory 202316 kb
Host smart-be6a8761-8719-422b-8275-3bc0f340bfbe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602614819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.602614819
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.482200649
Short name T25
Test name
Test status
Simulation time 76713595320 ps
CPU time 363.51 seconds
Started Apr 15 12:51:43 PM PDT 24
Finished Apr 15 12:57:47 PM PDT 24
Peak memory 202572 kb
Host smart-fbff2a0c-dc8d-409f-8532-1cea5847b6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482200649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.482200649
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3336115814
Short name T679
Test name
Test status
Simulation time 44147665181 ps
CPU time 27.55 seconds
Started Apr 15 12:51:45 PM PDT 24
Finished Apr 15 12:52:12 PM PDT 24
Peak memory 202100 kb
Host smart-bfbf0a66-292e-45d5-9f16-6e20740f798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336115814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3336115814
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2895673210
Short name T620
Test name
Test status
Simulation time 5045520332 ps
CPU time 12.07 seconds
Started Apr 15 12:51:44 PM PDT 24
Finished Apr 15 12:51:56 PM PDT 24
Peak memory 202092 kb
Host smart-d5d12f34-12f2-433e-8384-ed918b995623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895673210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2895673210
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.353398420
Short name T490
Test name
Test status
Simulation time 5745424007 ps
CPU time 14.5 seconds
Started Apr 15 12:51:43 PM PDT 24
Finished Apr 15 12:51:58 PM PDT 24
Peak memory 202112 kb
Host smart-bd2858ca-3f5d-49fa-9c34-c9070a85794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353398420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.353398420
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3521124761
Short name T265
Test name
Test status
Simulation time 335137018166 ps
CPU time 215.17 seconds
Started Apr 15 12:51:51 PM PDT 24
Finished Apr 15 12:55:26 PM PDT 24
Peak memory 202376 kb
Host smart-2cfc0328-9c43-4c39-a1ce-17ca16beb08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521124761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3521124761
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4103415285
Short name T250
Test name
Test status
Simulation time 302679730363 ps
CPU time 111.04 seconds
Started Apr 15 12:51:48 PM PDT 24
Finished Apr 15 12:53:39 PM PDT 24
Peak memory 210936 kb
Host smart-5f4d6b76-29c3-4691-90ee-ca16cb96fa63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103415285 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.4103415285
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1910459832
Short name T542
Test name
Test status
Simulation time 311941530 ps
CPU time 0.83 seconds
Started Apr 15 12:51:53 PM PDT 24
Finished Apr 15 12:51:54 PM PDT 24
Peak memory 201960 kb
Host smart-5964d68e-6edd-43a9-84b7-7f475d35531c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910459832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1910459832
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2954853653
Short name T674
Test name
Test status
Simulation time 175195001221 ps
CPU time 429.41 seconds
Started Apr 15 12:51:51 PM PDT 24
Finished Apr 15 12:59:01 PM PDT 24
Peak memory 202368 kb
Host smart-08849e93-51c0-4a4b-8bc0-98bfa7c61b23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954853653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2954853653
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3028663480
Short name T624
Test name
Test status
Simulation time 376542871766 ps
CPU time 396.82 seconds
Started Apr 15 12:51:54 PM PDT 24
Finished Apr 15 12:58:31 PM PDT 24
Peak memory 202160 kb
Host smart-d307af88-d7d3-4191-8b56-1a5037ec6739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028663480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3028663480
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4088823920
Short name T728
Test name
Test status
Simulation time 171125865742 ps
CPU time 90.43 seconds
Started Apr 15 12:51:48 PM PDT 24
Finished Apr 15 12:53:19 PM PDT 24
Peak memory 202228 kb
Host smart-948086b5-b4a2-40c1-97ac-f99d8e975572
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088823920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.4088823920
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1850036958
Short name T605
Test name
Test status
Simulation time 331551195154 ps
CPU time 191.34 seconds
Started Apr 15 12:51:52 PM PDT 24
Finished Apr 15 12:55:03 PM PDT 24
Peak memory 202324 kb
Host smart-6c94d59f-fe5d-4326-9cb1-a64bb0732b3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850036958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1850036958
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3850100904
Short name T770
Test name
Test status
Simulation time 182557449811 ps
CPU time 416.55 seconds
Started Apr 15 12:51:49 PM PDT 24
Finished Apr 15 12:58:46 PM PDT 24
Peak memory 202320 kb
Host smart-335a4697-5bef-4616-8ec6-144e4572adc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850100904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3850100904
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4059175195
Short name T417
Test name
Test status
Simulation time 408986462249 ps
CPU time 99.32 seconds
Started Apr 15 12:51:52 PM PDT 24
Finished Apr 15 12:53:32 PM PDT 24
Peak memory 202308 kb
Host smart-4e876f60-a260-4781-ad06-4ed6c60149df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059175195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4059175195
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3012708271
Short name T499
Test name
Test status
Simulation time 91375500427 ps
CPU time 393.16 seconds
Started Apr 15 12:51:53 PM PDT 24
Finished Apr 15 12:58:27 PM PDT 24
Peak memory 202468 kb
Host smart-0eba25dd-ed53-4f50-9b93-3e72d61fc320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012708271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3012708271
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1753600961
Short name T540
Test name
Test status
Simulation time 37980080988 ps
CPU time 92.69 seconds
Started Apr 15 12:51:51 PM PDT 24
Finished Apr 15 12:53:24 PM PDT 24
Peak memory 202060 kb
Host smart-8f68fdaa-69c8-4277-afd2-93fce21f9bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753600961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1753600961
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1824765831
Short name T450
Test name
Test status
Simulation time 3985280156 ps
CPU time 7.96 seconds
Started Apr 15 12:51:52 PM PDT 24
Finished Apr 15 12:52:01 PM PDT 24
Peak memory 202084 kb
Host smart-9d26fdee-66bd-41a9-a79f-6c7a9d6d873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824765831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1824765831
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1772596914
Short name T379
Test name
Test status
Simulation time 6018570392 ps
CPU time 7.42 seconds
Started Apr 15 12:51:52 PM PDT 24
Finished Apr 15 12:52:00 PM PDT 24
Peak memory 202112 kb
Host smart-59136b30-fdd6-4284-ade4-e5bb073c7906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772596914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1772596914
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.88600129
Short name T340
Test name
Test status
Simulation time 804341773581 ps
CPU time 323.79 seconds
Started Apr 15 12:51:57 PM PDT 24
Finished Apr 15 12:57:22 PM PDT 24
Peak memory 218092 kb
Host smart-0b9d8f76-ab88-4107-bdd7-102c72a8c882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88600129 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.88600129
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1750883162
Short name T60
Test name
Test status
Simulation time 581371164 ps
CPU time 0.94 seconds
Started Apr 15 12:52:01 PM PDT 24
Finished Apr 15 12:52:02 PM PDT 24
Peak memory 202004 kb
Host smart-bf531818-0b94-44ab-b0a3-354972d63509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750883162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1750883162
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2441961871
Short name T183
Test name
Test status
Simulation time 574079696754 ps
CPU time 254.42 seconds
Started Apr 15 12:51:55 PM PDT 24
Finished Apr 15 12:56:10 PM PDT 24
Peak memory 202276 kb
Host smart-b930ff2f-6735-44dd-a669-026f02ec76e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441961871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2441961871
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1564113837
Short name T320
Test name
Test status
Simulation time 164960736169 ps
CPU time 277.76 seconds
Started Apr 15 12:51:58 PM PDT 24
Finished Apr 15 12:56:36 PM PDT 24
Peak memory 202252 kb
Host smart-3c452317-0550-48e9-8c3b-c625a0b03b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564113837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1564113837
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2280314555
Short name T700
Test name
Test status
Simulation time 501879990142 ps
CPU time 1056.82 seconds
Started Apr 15 12:51:57 PM PDT 24
Finished Apr 15 01:09:34 PM PDT 24
Peak memory 202256 kb
Host smart-72541da0-6450-4108-a6a0-811ec87adbfa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280314555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2280314555
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.552969769
Short name T153
Test name
Test status
Simulation time 485457107115 ps
CPU time 248.48 seconds
Started Apr 15 12:51:51 PM PDT 24
Finished Apr 15 12:56:00 PM PDT 24
Peak memory 202264 kb
Host smart-169b1f52-39c8-4eb3-b73c-64b90abaf532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552969769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.552969769
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.928232636
Short name T727
Test name
Test status
Simulation time 487702750214 ps
CPU time 307.3 seconds
Started Apr 15 12:51:55 PM PDT 24
Finished Apr 15 12:57:02 PM PDT 24
Peak memory 202044 kb
Host smart-9d80a50a-3844-4d98-bec3-8b6778862876
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=928232636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.928232636
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.259531934
Short name T296
Test name
Test status
Simulation time 424376978856 ps
CPU time 943.25 seconds
Started Apr 15 12:51:56 PM PDT 24
Finished Apr 15 01:07:40 PM PDT 24
Peak memory 202304 kb
Host smart-7bbe4338-93e8-4ffa-928c-c8441ad48de5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259531934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.259531934
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1783234481
Short name T556
Test name
Test status
Simulation time 203704390086 ps
CPU time 440.9 seconds
Started Apr 15 12:51:58 PM PDT 24
Finished Apr 15 12:59:19 PM PDT 24
Peak memory 202212 kb
Host smart-ccc2ce7a-31c1-4d16-b9ed-126a2e3347c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783234481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1783234481
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1826341817
Short name T464
Test name
Test status
Simulation time 80894905035 ps
CPU time 245.35 seconds
Started Apr 15 12:52:05 PM PDT 24
Finished Apr 15 12:56:10 PM PDT 24
Peak memory 202544 kb
Host smart-037ba62b-c41e-497e-8573-10b9502a315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826341817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1826341817
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2973898824
Short name T722
Test name
Test status
Simulation time 27756718905 ps
CPU time 17.63 seconds
Started Apr 15 12:51:57 PM PDT 24
Finished Apr 15 12:52:15 PM PDT 24
Peak memory 202100 kb
Host smart-44acf739-e845-4141-9289-79ee47283978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973898824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2973898824
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1857717292
Short name T730
Test name
Test status
Simulation time 5287284193 ps
CPU time 2.75 seconds
Started Apr 15 12:51:56 PM PDT 24
Finished Apr 15 12:51:59 PM PDT 24
Peak memory 202080 kb
Host smart-87bbaa85-182d-45c0-a22a-4059eda7c673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857717292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1857717292
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1718326894
Short name T680
Test name
Test status
Simulation time 6165211206 ps
CPU time 8.48 seconds
Started Apr 15 12:51:57 PM PDT 24
Finished Apr 15 12:52:06 PM PDT 24
Peak memory 202080 kb
Host smart-bae59274-9dc3-4f2b-83b5-268aa29a919c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718326894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1718326894
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.838341895
Short name T310
Test name
Test status
Simulation time 241303997472 ps
CPU time 732.99 seconds
Started Apr 15 12:52:00 PM PDT 24
Finished Apr 15 01:04:14 PM PDT 24
Peak memory 210848 kb
Host smart-d8a19df0-971a-4d00-b808-b421a2f0f8d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838341895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
838341895
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2242982553
Short name T441
Test name
Test status
Simulation time 100765067780 ps
CPU time 140.25 seconds
Started Apr 15 12:52:00 PM PDT 24
Finished Apr 15 12:54:21 PM PDT 24
Peak memory 210912 kb
Host smart-83a334c3-acf1-4e65-bf8c-93272d6dc457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242982553 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2242982553
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1370822538
Short name T614
Test name
Test status
Simulation time 346063583 ps
CPU time 1.43 seconds
Started Apr 15 12:52:09 PM PDT 24
Finished Apr 15 12:52:11 PM PDT 24
Peak memory 201968 kb
Host smart-8512b4e6-bc45-4c86-8fc9-bdb6c5b842e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370822538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1370822538
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2328712370
Short name T285
Test name
Test status
Simulation time 166850394798 ps
CPU time 205.7 seconds
Started Apr 15 12:52:04 PM PDT 24
Finished Apr 15 12:55:30 PM PDT 24
Peak memory 202344 kb
Host smart-1c139cac-a0e9-499d-9332-74a581876f9b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328712370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2328712370
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2847383865
Short name T563
Test name
Test status
Simulation time 320617902713 ps
CPU time 188.49 seconds
Started Apr 15 12:52:00 PM PDT 24
Finished Apr 15 12:55:09 PM PDT 24
Peak memory 202336 kb
Host smart-e5803283-b4be-4612-9278-1aed9ea158a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847383865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2847383865
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3377185690
Short name T599
Test name
Test status
Simulation time 328142845823 ps
CPU time 223.94 seconds
Started Apr 15 12:52:06 PM PDT 24
Finished Apr 15 12:55:50 PM PDT 24
Peak memory 202252 kb
Host smart-1f2765a2-a06c-4679-8213-9eb35a98429e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377185690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3377185690
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.435146410
Short name T124
Test name
Test status
Simulation time 491038613209 ps
CPU time 924.95 seconds
Started Apr 15 12:52:05 PM PDT 24
Finished Apr 15 01:07:30 PM PDT 24
Peak memory 202320 kb
Host smart-cd5fbf54-b1f2-4b97-873d-2ecb13841ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435146410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.435146410
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4157575931
Short name T694
Test name
Test status
Simulation time 329850336578 ps
CPU time 722.88 seconds
Started Apr 15 12:52:02 PM PDT 24
Finished Apr 15 01:04:05 PM PDT 24
Peak memory 202420 kb
Host smart-037f957d-a0e4-4d75-be72-c5e1afe9c4eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157575931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4157575931
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.799042667
Short name T291
Test name
Test status
Simulation time 178133692899 ps
CPU time 97.55 seconds
Started Apr 15 12:52:06 PM PDT 24
Finished Apr 15 12:53:44 PM PDT 24
Peak memory 202248 kb
Host smart-7d62d5cc-f6d9-4fe8-86c0-e5465fe688ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799042667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.799042667
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.436592273
Short name T627
Test name
Test status
Simulation time 204018039647 ps
CPU time 450.84 seconds
Started Apr 15 12:52:05 PM PDT 24
Finished Apr 15 12:59:36 PM PDT 24
Peak memory 202272 kb
Host smart-9d6a5ace-6ad1-44f0-ad61-6a65a949eeb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436592273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.436592273
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2665535816
Short name T455
Test name
Test status
Simulation time 98213217980 ps
CPU time 338.5 seconds
Started Apr 15 12:52:05 PM PDT 24
Finished Apr 15 12:57:43 PM PDT 24
Peak memory 202568 kb
Host smart-b1573118-3239-4118-b2aa-d1c96c7c7c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665535816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2665535816
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2007251464
Short name T794
Test name
Test status
Simulation time 45627030486 ps
CPU time 27.42 seconds
Started Apr 15 12:52:04 PM PDT 24
Finished Apr 15 12:52:32 PM PDT 24
Peak memory 202104 kb
Host smart-6de7f83d-db75-4eb8-9943-118cdb67565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007251464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2007251464
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.4046229491
Short name T411
Test name
Test status
Simulation time 5161081247 ps
CPU time 1.78 seconds
Started Apr 15 12:52:05 PM PDT 24
Finished Apr 15 12:52:07 PM PDT 24
Peak memory 202024 kb
Host smart-56462053-cf56-48c3-be98-0a2b50d59fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046229491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4046229491
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2617666848
Short name T384
Test name
Test status
Simulation time 5653438455 ps
CPU time 7.42 seconds
Started Apr 15 12:52:01 PM PDT 24
Finished Apr 15 12:52:08 PM PDT 24
Peak memory 202064 kb
Host smart-82ce6b61-837c-4be2-95f3-dc6df9fc5073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617666848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2617666848
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1748637853
Short name T590
Test name
Test status
Simulation time 58853530876 ps
CPU time 132.83 seconds
Started Apr 15 12:52:07 PM PDT 24
Finished Apr 15 12:54:20 PM PDT 24
Peak memory 211876 kb
Host smart-f692815e-a77d-4008-82fe-f7778a326e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748637853 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1748637853
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.678313261
Short name T720
Test name
Test status
Simulation time 602476420 ps
CPU time 0.77 seconds
Started Apr 15 12:52:13 PM PDT 24
Finished Apr 15 12:52:14 PM PDT 24
Peak memory 201984 kb
Host smart-f65b0d01-8417-485f-bbb6-5f5d8d735b0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678313261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.678313261
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.797443561
Short name T775
Test name
Test status
Simulation time 355027498251 ps
CPU time 197.03 seconds
Started Apr 15 12:52:15 PM PDT 24
Finished Apr 15 12:55:33 PM PDT 24
Peak memory 202308 kb
Host smart-e7eb5b90-c074-4b68-9420-7700dc38ab6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797443561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.797443561
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.808058607
Short name T120
Test name
Test status
Simulation time 474300078049 ps
CPU time 1094.96 seconds
Started Apr 15 12:52:15 PM PDT 24
Finished Apr 15 01:10:31 PM PDT 24
Peak memory 202180 kb
Host smart-9f3e145e-5910-44fe-9f64-3febc973339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808058607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.808058607
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2866202799
Short name T446
Test name
Test status
Simulation time 483772856268 ps
CPU time 299.59 seconds
Started Apr 15 12:52:10 PM PDT 24
Finished Apr 15 12:57:10 PM PDT 24
Peak memory 202304 kb
Host smart-fd4ea3a0-007b-45da-8cc0-97ce213bfe99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866202799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2866202799
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1342299878
Short name T171
Test name
Test status
Simulation time 327968441272 ps
CPU time 793.23 seconds
Started Apr 15 12:52:11 PM PDT 24
Finished Apr 15 01:05:25 PM PDT 24
Peak memory 202120 kb
Host smart-2a4dda70-b69a-4868-a422-7b573d54de55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342299878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1342299878
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2923447625
Short name T645
Test name
Test status
Simulation time 474838330862 ps
CPU time 252.95 seconds
Started Apr 15 12:52:10 PM PDT 24
Finished Apr 15 12:56:23 PM PDT 24
Peak memory 202280 kb
Host smart-0b093080-b959-4f25-94ba-345622d765f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923447625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2923447625
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3117769800
Short name T154
Test name
Test status
Simulation time 347508103609 ps
CPU time 598.41 seconds
Started Apr 15 12:52:10 PM PDT 24
Finished Apr 15 01:02:09 PM PDT 24
Peak memory 202344 kb
Host smart-a6a4433e-20fc-4084-a541-a844c0ff8d8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117769800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3117769800
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3827333197
Short name T129
Test name
Test status
Simulation time 405011504706 ps
CPU time 110.81 seconds
Started Apr 15 12:52:09 PM PDT 24
Finished Apr 15 12:54:01 PM PDT 24
Peak memory 202304 kb
Host smart-274d14a6-8a96-4d90-8e65-d462d51643fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827333197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3827333197
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1580127728
Short name T547
Test name
Test status
Simulation time 99618386902 ps
CPU time 528.56 seconds
Started Apr 15 12:52:10 PM PDT 24
Finished Apr 15 01:00:59 PM PDT 24
Peak memory 202560 kb
Host smart-000c6c61-00e6-44e7-97fa-37fd72e6378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580127728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1580127728
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1461412730
Short name T373
Test name
Test status
Simulation time 25814353821 ps
CPU time 14.71 seconds
Started Apr 15 12:52:13 PM PDT 24
Finished Apr 15 12:52:29 PM PDT 24
Peak memory 202068 kb
Host smart-a7550c38-db99-445d-9312-01f1e78c8886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461412730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1461412730
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3675827575
Short name T608
Test name
Test status
Simulation time 4397042191 ps
CPU time 1.7 seconds
Started Apr 15 12:52:11 PM PDT 24
Finished Apr 15 12:52:13 PM PDT 24
Peak memory 202048 kb
Host smart-8437a6f1-12b3-446b-a11f-ec1e00c713da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675827575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3675827575
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.940796399
Short name T765
Test name
Test status
Simulation time 5867747447 ps
CPU time 13.83 seconds
Started Apr 15 12:52:09 PM PDT 24
Finished Apr 15 12:52:23 PM PDT 24
Peak memory 202088 kb
Host smart-bfc37486-d170-4c32-8edd-07251ac8fcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940796399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.940796399
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2380175275
Short name T177
Test name
Test status
Simulation time 201467890486 ps
CPU time 438.62 seconds
Started Apr 15 12:52:14 PM PDT 24
Finished Apr 15 12:59:33 PM PDT 24
Peak memory 202364 kb
Host smart-6b16e812-d5c0-4060-9de9-0d713d2bfa03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380175275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2380175275
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3115191468
Short name T790
Test name
Test status
Simulation time 29416278349 ps
CPU time 109.64 seconds
Started Apr 15 12:52:14 PM PDT 24
Finished Apr 15 12:54:04 PM PDT 24
Peak memory 210880 kb
Host smart-314f7033-2e69-4f2f-9b53-fefa21f30d48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115191468 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3115191468
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2620001524
Short name T476
Test name
Test status
Simulation time 476695031 ps
CPU time 0.9 seconds
Started Apr 15 12:52:24 PM PDT 24
Finished Apr 15 12:52:25 PM PDT 24
Peak memory 201960 kb
Host smart-e820eb18-430b-4dd6-9eec-2261f03f784c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620001524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2620001524
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3872787659
Short name T187
Test name
Test status
Simulation time 359794971395 ps
CPU time 763.59 seconds
Started Apr 15 12:52:19 PM PDT 24
Finished Apr 15 01:05:03 PM PDT 24
Peak memory 202268 kb
Host smart-06b4bd8c-eeb6-489b-9d42-f2568904f13b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872787659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3872787659
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.613861434
Short name T338
Test name
Test status
Simulation time 554932400970 ps
CPU time 671.73 seconds
Started Apr 15 12:52:18 PM PDT 24
Finished Apr 15 01:03:31 PM PDT 24
Peak memory 202248 kb
Host smart-d05a5332-b243-4e46-b59a-9037c1c25055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613861434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.613861434
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.346003334
Short name T622
Test name
Test status
Simulation time 325069986532 ps
CPU time 359.03 seconds
Started Apr 15 12:52:14 PM PDT 24
Finished Apr 15 12:58:13 PM PDT 24
Peak memory 202348 kb
Host smart-3a07e34a-97a7-4af6-a1ef-a6d69fc9f944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346003334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.346003334
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3773046723
Short name T72
Test name
Test status
Simulation time 333437594069 ps
CPU time 250.88 seconds
Started Apr 15 12:52:14 PM PDT 24
Finished Apr 15 12:56:25 PM PDT 24
Peak memory 202292 kb
Host smart-9bc52c72-9a07-4839-a0fa-6ce8fad219f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773046723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3773046723
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.549102724
Short name T677
Test name
Test status
Simulation time 168817616817 ps
CPU time 52.61 seconds
Started Apr 15 12:52:15 PM PDT 24
Finished Apr 15 12:53:08 PM PDT 24
Peak memory 202332 kb
Host smart-77505cc0-261c-45ca-a525-0205dfede3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549102724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.549102724
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3666282237
Short name T678
Test name
Test status
Simulation time 160815731526 ps
CPU time 94.86 seconds
Started Apr 15 12:52:13 PM PDT 24
Finished Apr 15 12:53:49 PM PDT 24
Peak memory 202200 kb
Host smart-a42bb740-727a-4e92-84ef-c05fa8057965
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666282237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3666282237
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.984963274
Short name T393
Test name
Test status
Simulation time 590623724805 ps
CPU time 379.34 seconds
Started Apr 15 12:52:18 PM PDT 24
Finished Apr 15 12:58:38 PM PDT 24
Peak memory 202212 kb
Host smart-60dbbdc9-2174-46f0-9dfb-5f58e9015435
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984963274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.984963274
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4269303121
Short name T85
Test name
Test status
Simulation time 96679226601 ps
CPU time 419.15 seconds
Started Apr 15 12:52:24 PM PDT 24
Finished Apr 15 12:59:23 PM PDT 24
Peak memory 202704 kb
Host smart-9a611beb-49ce-4e0e-872c-956166f56c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269303121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4269303121
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2336384744
Short name T173
Test name
Test status
Simulation time 23754817679 ps
CPU time 29.65 seconds
Started Apr 15 12:52:19 PM PDT 24
Finished Apr 15 12:52:49 PM PDT 24
Peak memory 202084 kb
Host smart-6f3b78dd-0a23-418d-987e-5348d9b05260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336384744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2336384744
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1664096462
Short name T86
Test name
Test status
Simulation time 4978631594 ps
CPU time 3.61 seconds
Started Apr 15 12:52:18 PM PDT 24
Finished Apr 15 12:52:22 PM PDT 24
Peak memory 202080 kb
Host smart-4673ceb5-17c8-4007-82e6-865c01cddc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664096462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1664096462
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1340573126
Short name T578
Test name
Test status
Simulation time 5954981976 ps
CPU time 14.81 seconds
Started Apr 15 12:52:15 PM PDT 24
Finished Apr 15 12:52:30 PM PDT 24
Peak memory 201980 kb
Host smart-c819be27-7a4f-49fe-ae97-1bdea9594c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340573126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1340573126
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.140475077
Short name T666
Test name
Test status
Simulation time 344905426227 ps
CPU time 298.8 seconds
Started Apr 15 12:52:24 PM PDT 24
Finished Apr 15 12:57:23 PM PDT 24
Peak memory 202324 kb
Host smart-649ed888-8d84-464e-bb4c-18c64c6a3d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140475077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
140475077
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3676120737
Short name T293
Test name
Test status
Simulation time 55082046370 ps
CPU time 247.99 seconds
Started Apr 15 12:52:22 PM PDT 24
Finished Apr 15 12:56:30 PM PDT 24
Peak memory 218212 kb
Host smart-313abe45-583c-4a1f-9c38-7dddebcf1835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676120737 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3676120737
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2593421749
Short name T623
Test name
Test status
Simulation time 342107544 ps
CPU time 0.91 seconds
Started Apr 15 12:50:43 PM PDT 24
Finished Apr 15 12:50:45 PM PDT 24
Peak memory 201996 kb
Host smart-66189ff8-ca98-4a85-bb5e-bafb6139c672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593421749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2593421749
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3738408657
Short name T767
Test name
Test status
Simulation time 193769538946 ps
CPU time 428.78 seconds
Started Apr 15 12:50:37 PM PDT 24
Finished Apr 15 12:57:46 PM PDT 24
Peak memory 202360 kb
Host smart-7de90cb5-5d8b-4195-a299-d6adcf5b3bbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738408657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3738408657
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1592934476
Short name T632
Test name
Test status
Simulation time 161114530749 ps
CPU time 340.41 seconds
Started Apr 15 12:50:40 PM PDT 24
Finished Apr 15 12:56:21 PM PDT 24
Peak memory 202164 kb
Host smart-787c413c-3d57-42be-9ffb-b1e2a2a9c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592934476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1592934476
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.15194747
Short name T621
Test name
Test status
Simulation time 490599912609 ps
CPU time 552.12 seconds
Started Apr 15 12:50:38 PM PDT 24
Finished Apr 15 12:59:50 PM PDT 24
Peak memory 202260 kb
Host smart-2823770f-180f-436c-a691-7b473a4a08d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15194747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.15194747
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3691875932
Short name T514
Test name
Test status
Simulation time 160774198195 ps
CPU time 145.24 seconds
Started Apr 15 12:50:37 PM PDT 24
Finished Apr 15 12:53:03 PM PDT 24
Peak memory 202220 kb
Host smart-ef20ca9a-682e-41a4-a84f-096fa8cace87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691875932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3691875932
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1051703094
Short name T390
Test name
Test status
Simulation time 328137781483 ps
CPU time 758.81 seconds
Started Apr 15 12:50:37 PM PDT 24
Finished Apr 15 01:03:16 PM PDT 24
Peak memory 202236 kb
Host smart-c6344d01-b917-4bf9-aa8a-fa84f314d831
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051703094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1051703094
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1596992024
Short name T334
Test name
Test status
Simulation time 202476252390 ps
CPU time 121.71 seconds
Started Apr 15 12:50:38 PM PDT 24
Finished Apr 15 12:52:40 PM PDT 24
Peak memory 202324 kb
Host smart-81ce6fb7-a508-4579-b5e0-8372eccd2737
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596992024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1596992024
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2106701107
Short name T654
Test name
Test status
Simulation time 201656968292 ps
CPU time 472.81 seconds
Started Apr 15 12:50:43 PM PDT 24
Finished Apr 15 12:58:36 PM PDT 24
Peak memory 202212 kb
Host smart-a9b5d749-275e-4c84-852e-32765ae21791
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106701107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2106701107
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3030714668
Short name T596
Test name
Test status
Simulation time 111740840960 ps
CPU time 466.49 seconds
Started Apr 15 12:50:42 PM PDT 24
Finished Apr 15 12:58:29 PM PDT 24
Peak memory 202552 kb
Host smart-74a19745-3e69-42c5-a478-0c40834a321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030714668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3030714668
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.4154965345
Short name T747
Test name
Test status
Simulation time 42171716929 ps
CPU time 49.27 seconds
Started Apr 15 12:50:44 PM PDT 24
Finished Apr 15 12:51:34 PM PDT 24
Peak memory 202108 kb
Host smart-ac40d760-5f80-45f5-85d8-1b777d3b3b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154965345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.4154965345
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2984915551
Short name T205
Test name
Test status
Simulation time 3292310546 ps
CPU time 2.56 seconds
Started Apr 15 12:50:43 PM PDT 24
Finished Apr 15 12:50:46 PM PDT 24
Peak memory 202064 kb
Host smart-43e3cc79-3d97-4a04-a8d0-fb4c6a85ae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984915551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2984915551
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.897110511
Short name T53
Test name
Test status
Simulation time 4318677172 ps
CPU time 10.59 seconds
Started Apr 15 12:50:43 PM PDT 24
Finished Apr 15 12:50:54 PM PDT 24
Peak memory 217828 kb
Host smart-567e51c1-2868-4828-b7ab-aa7611815551
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897110511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.897110511
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2479333701
Short name T453
Test name
Test status
Simulation time 5816686445 ps
CPU time 13.6 seconds
Started Apr 15 12:50:42 PM PDT 24
Finished Apr 15 12:50:56 PM PDT 24
Peak memory 202084 kb
Host smart-fe2d5ec4-d238-4756-8614-1772f564f1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479333701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2479333701
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.4081136575
Short name T445
Test name
Test status
Simulation time 175052247923 ps
CPU time 427.21 seconds
Started Apr 15 12:50:45 PM PDT 24
Finished Apr 15 12:57:52 PM PDT 24
Peak memory 202260 kb
Host smart-4510e775-7d76-4cf2-bc6c-786ca1fe83a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081136575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
4081136575
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3492406952
Short name T439
Test name
Test status
Simulation time 314414377 ps
CPU time 0.79 seconds
Started Apr 15 12:52:33 PM PDT 24
Finished Apr 15 12:52:35 PM PDT 24
Peak memory 202000 kb
Host smart-c6775705-f5ca-4fae-a463-e9d6482c08b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492406952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3492406952
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3580110576
Short name T306
Test name
Test status
Simulation time 174721666681 ps
CPU time 105.08 seconds
Started Apr 15 12:52:28 PM PDT 24
Finished Apr 15 12:54:14 PM PDT 24
Peak memory 202296 kb
Host smart-38816a17-c51f-40a4-8b44-a7d6a0c0e70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580110576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3580110576
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2960811926
Short name T160
Test name
Test status
Simulation time 490887516963 ps
CPU time 158.02 seconds
Started Apr 15 12:52:28 PM PDT 24
Finished Apr 15 12:55:06 PM PDT 24
Peak memory 202260 kb
Host smart-caa194ef-e9b8-490b-b09c-5c2a7f251a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960811926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2960811926
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2167062769
Short name T657
Test name
Test status
Simulation time 328536499321 ps
CPU time 514.61 seconds
Started Apr 15 12:52:28 PM PDT 24
Finished Apr 15 01:01:03 PM PDT 24
Peak memory 202292 kb
Host smart-f50ecdd2-7cc8-4392-8b99-8f4c047e3b33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167062769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2167062769
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3808456312
Short name T571
Test name
Test status
Simulation time 489294848330 ps
CPU time 1168.2 seconds
Started Apr 15 12:52:31 PM PDT 24
Finished Apr 15 01:12:00 PM PDT 24
Peak memory 202204 kb
Host smart-2d8a34d6-ed34-4242-9fd0-5474465b6d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808456312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3808456312
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3594031342
Short name T504
Test name
Test status
Simulation time 490242627478 ps
CPU time 1167.59 seconds
Started Apr 15 12:52:31 PM PDT 24
Finished Apr 15 01:11:59 PM PDT 24
Peak memory 202164 kb
Host smart-af797a9b-5fc1-41ff-9678-84f63bfe363f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594031342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3594031342
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2068555867
Short name T743
Test name
Test status
Simulation time 174377768328 ps
CPU time 94.5 seconds
Started Apr 15 12:52:29 PM PDT 24
Finished Apr 15 12:54:03 PM PDT 24
Peak memory 202344 kb
Host smart-dd7c6674-abd5-41cc-a10f-3b18466e8c5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068555867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2068555867
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3979608883
Short name T741
Test name
Test status
Simulation time 190515933302 ps
CPU time 460.19 seconds
Started Apr 15 12:52:30 PM PDT 24
Finished Apr 15 01:00:10 PM PDT 24
Peak memory 202244 kb
Host smart-c976b6e7-e8bc-47ec-ba21-5045047615dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979608883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3979608883
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1341992447
Short name T210
Test name
Test status
Simulation time 105943942834 ps
CPU time 366.5 seconds
Started Apr 15 12:52:28 PM PDT 24
Finished Apr 15 12:58:35 PM PDT 24
Peak memory 202572 kb
Host smart-e1e88467-b0bc-430c-b60c-1e1ef5c52961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341992447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1341992447
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2291418235
Short name T515
Test name
Test status
Simulation time 33150008026 ps
CPU time 34.83 seconds
Started Apr 15 12:52:31 PM PDT 24
Finished Apr 15 12:53:06 PM PDT 24
Peak memory 202048 kb
Host smart-0469f76c-48a9-4cf5-a0ee-901f8ed58765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291418235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2291418235
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.935704738
Short name T667
Test name
Test status
Simulation time 4794766856 ps
CPU time 3.95 seconds
Started Apr 15 12:52:30 PM PDT 24
Finished Apr 15 12:52:34 PM PDT 24
Peak memory 202088 kb
Host smart-8b468a89-f34e-489b-b595-eeae3151227d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935704738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.935704738
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1169381262
Short name T777
Test name
Test status
Simulation time 5823148811 ps
CPU time 4.01 seconds
Started Apr 15 12:52:25 PM PDT 24
Finished Apr 15 12:52:30 PM PDT 24
Peak memory 202076 kb
Host smart-6d4c50ec-af35-4ca5-b8aa-8ab50447a962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169381262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1169381262
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1632245199
Short name T213
Test name
Test status
Simulation time 88298233521 ps
CPU time 480.97 seconds
Started Apr 15 12:52:33 PM PDT 24
Finished Apr 15 01:00:35 PM PDT 24
Peak memory 202548 kb
Host smart-b675ba49-6664-4251-aca3-a582e6579b7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632245199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1632245199
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.603355371
Short name T14
Test name
Test status
Simulation time 90233726922 ps
CPU time 467.83 seconds
Started Apr 15 12:52:30 PM PDT 24
Finished Apr 15 01:00:19 PM PDT 24
Peak memory 210980 kb
Host smart-44320cdb-d07f-4753-8c4c-92f99ebcc8df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603355371 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.603355371
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1071096293
Short name T456
Test name
Test status
Simulation time 538902780 ps
CPU time 0.93 seconds
Started Apr 15 12:52:42 PM PDT 24
Finished Apr 15 12:52:43 PM PDT 24
Peak memory 201984 kb
Host smart-9a2d69e1-c286-43f1-8980-48ab19477de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071096293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1071096293
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3047392555
Short name T125
Test name
Test status
Simulation time 163862215659 ps
CPU time 375.77 seconds
Started Apr 15 12:52:59 PM PDT 24
Finished Apr 15 12:59:15 PM PDT 24
Peak memory 202252 kb
Host smart-caec4fcb-1ecd-473f-8c39-f1ded410af0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047392555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3047392555
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1994437028
Short name T662
Test name
Test status
Simulation time 327231930001 ps
CPU time 406.82 seconds
Started Apr 15 12:52:32 PM PDT 24
Finished Apr 15 12:59:19 PM PDT 24
Peak memory 202220 kb
Host smart-505ae053-e390-4fcd-9362-f1326e8ab4a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994437028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1994437028
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.234720588
Short name T140
Test name
Test status
Simulation time 496092508360 ps
CPU time 161.07 seconds
Started Apr 15 12:52:32 PM PDT 24
Finished Apr 15 12:55:13 PM PDT 24
Peak memory 202236 kb
Host smart-1ef972bc-844b-46da-8211-57cbbf9f7c41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=234720588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.234720588
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2772530285
Short name T752
Test name
Test status
Simulation time 197512960436 ps
CPU time 227.07 seconds
Started Apr 15 12:52:32 PM PDT 24
Finished Apr 15 12:56:19 PM PDT 24
Peak memory 202240 kb
Host smart-efb72c4c-3a7f-43d7-b2c3-2cf1c2e8518c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772530285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2772530285
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.572428470
Short name T175
Test name
Test status
Simulation time 79754963788 ps
CPU time 361.05 seconds
Started Apr 15 12:52:38 PM PDT 24
Finished Apr 15 12:58:40 PM PDT 24
Peak memory 202668 kb
Host smart-72b8357f-cf8c-4718-b8ba-5c06108f1c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572428470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.572428470
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3869885021
Short name T587
Test name
Test status
Simulation time 34196752693 ps
CPU time 23.56 seconds
Started Apr 15 12:52:39 PM PDT 24
Finished Apr 15 12:53:03 PM PDT 24
Peak memory 202120 kb
Host smart-fa70d0a4-b0db-4e80-a4bc-44785b02c17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869885021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3869885021
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.445686094
Short name T535
Test name
Test status
Simulation time 3430590717 ps
CPU time 9.26 seconds
Started Apr 15 12:52:39 PM PDT 24
Finished Apr 15 12:52:48 PM PDT 24
Peak memory 202092 kb
Host smart-dcd2cea8-0bc7-4a55-8d18-72260165698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445686094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.445686094
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2957685178
Short name T671
Test name
Test status
Simulation time 5864671347 ps
CPU time 14.22 seconds
Started Apr 15 12:52:34 PM PDT 24
Finished Apr 15 12:52:48 PM PDT 24
Peak memory 202064 kb
Host smart-fe96db9e-3528-4eb9-85d5-654831db11e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957685178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2957685178
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2161022383
Short name T717
Test name
Test status
Simulation time 41231965802 ps
CPU time 95.79 seconds
Started Apr 15 12:52:42 PM PDT 24
Finished Apr 15 12:54:18 PM PDT 24
Peak memory 210596 kb
Host smart-4ec7aba9-93ac-4d60-b3bc-332aeaa36c29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161022383 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2161022383
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1253704823
Short name T408
Test name
Test status
Simulation time 445351852 ps
CPU time 1.77 seconds
Started Apr 15 12:52:53 PM PDT 24
Finished Apr 15 12:52:55 PM PDT 24
Peak memory 201852 kb
Host smart-a3497c80-a3a3-4424-8968-1be3a85175ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253704823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1253704823
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3766181004
Short name T348
Test name
Test status
Simulation time 225087166080 ps
CPU time 120.66 seconds
Started Apr 15 12:52:48 PM PDT 24
Finished Apr 15 12:54:49 PM PDT 24
Peak memory 202248 kb
Host smart-785f6e50-b8d2-47d5-acd7-99928488eb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766181004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3766181004
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.4092083891
Short name T333
Test name
Test status
Simulation time 332008835441 ps
CPU time 413.62 seconds
Started Apr 15 12:52:42 PM PDT 24
Finished Apr 15 12:59:36 PM PDT 24
Peak memory 202256 kb
Host smart-a8392436-1f82-4d56-b6e3-f2058d7a4f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092083891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.4092083891
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3270113238
Short name T395
Test name
Test status
Simulation time 494938193948 ps
CPU time 1019.44 seconds
Started Apr 15 12:52:44 PM PDT 24
Finished Apr 15 01:09:44 PM PDT 24
Peak memory 202244 kb
Host smart-901a622e-90b5-41ee-9918-ee031a1f46d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270113238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3270113238
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2553054956
Short name T562
Test name
Test status
Simulation time 500886613553 ps
CPU time 1258.14 seconds
Started Apr 15 12:52:41 PM PDT 24
Finished Apr 15 01:13:39 PM PDT 24
Peak memory 202352 kb
Host smart-38986bbb-16bc-4cfc-af31-74e57ea1337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553054956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2553054956
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.477654559
Short name T436
Test name
Test status
Simulation time 491952542720 ps
CPU time 1139.53 seconds
Started Apr 15 12:52:43 PM PDT 24
Finished Apr 15 01:11:43 PM PDT 24
Peak memory 202260 kb
Host smart-38367135-2b0b-49a8-9a93-37f8888227ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=477654559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.477654559
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2619268
Short name T503
Test name
Test status
Simulation time 352796285407 ps
CPU time 433.75 seconds
Started Apr 15 12:52:45 PM PDT 24
Finished Apr 15 01:00:00 PM PDT 24
Peak memory 202344 kb
Host smart-14c6e6e5-2f7a-4cab-b1a5-ebabbe78acd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wa
keup.2619268
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.983956480
Short name T193
Test name
Test status
Simulation time 121985082105 ps
CPU time 393.18 seconds
Started Apr 15 12:52:48 PM PDT 24
Finished Apr 15 12:59:21 PM PDT 24
Peak memory 202564 kb
Host smart-9e8e8dd4-983a-45bd-b169-0c72df40a359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983956480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.983956480
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2310361008
Short name T541
Test name
Test status
Simulation time 46866131432 ps
CPU time 105.81 seconds
Started Apr 15 12:52:46 PM PDT 24
Finished Apr 15 12:54:32 PM PDT 24
Peak memory 202032 kb
Host smart-ba6a08ef-b6d2-4a73-83e0-036192fe5f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310361008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2310361008
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3087028157
Short name T119
Test name
Test status
Simulation time 4438760821 ps
CPU time 1.6 seconds
Started Apr 15 12:52:46 PM PDT 24
Finished Apr 15 12:52:48 PM PDT 24
Peak memory 202096 kb
Host smart-3a7c5dd2-f8ae-4888-897b-701315abb4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087028157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3087028157
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1413946780
Short name T740
Test name
Test status
Simulation time 5921448816 ps
CPU time 15.99 seconds
Started Apr 15 12:52:43 PM PDT 24
Finished Apr 15 12:52:59 PM PDT 24
Peak memory 202076 kb
Host smart-de12b214-12d3-4792-a018-6462c050a2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413946780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1413946780
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2818962035
Short name T604
Test name
Test status
Simulation time 317823162744 ps
CPU time 740.12 seconds
Started Apr 15 12:52:49 PM PDT 24
Finished Apr 15 01:05:10 PM PDT 24
Peak memory 202272 kb
Host smart-0c58f52e-bcfb-4371-a2bc-b3279cedbf8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818962035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2818962035
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2335678754
Short name T34
Test name
Test status
Simulation time 331113887680 ps
CPU time 247.37 seconds
Started Apr 15 12:52:51 PM PDT 24
Finished Apr 15 12:56:58 PM PDT 24
Peak memory 218108 kb
Host smart-94fbfa33-55b1-4557-8b6e-89380ddb0449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335678754 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2335678754
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1312287909
Short name T412
Test name
Test status
Simulation time 393741058 ps
CPU time 0.83 seconds
Started Apr 15 12:52:58 PM PDT 24
Finished Apr 15 12:52:59 PM PDT 24
Peak memory 201928 kb
Host smart-e45bcccd-462f-4a87-b7a2-f7d883062862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312287909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1312287909
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1703980029
Short name T330
Test name
Test status
Simulation time 555891256069 ps
CPU time 70.34 seconds
Started Apr 15 12:53:16 PM PDT 24
Finished Apr 15 12:54:27 PM PDT 24
Peak memory 202240 kb
Host smart-72d485c2-ea7e-4a31-9205-68bcc0c2f0da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703980029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1703980029
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1742198284
Short name T279
Test name
Test status
Simulation time 315058022610 ps
CPU time 407.2 seconds
Started Apr 15 12:52:51 PM PDT 24
Finished Apr 15 12:59:39 PM PDT 24
Peak memory 202188 kb
Host smart-5d23c617-d95f-4bfd-8b93-16397dd5d5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742198284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1742198284
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2811643304
Short name T401
Test name
Test status
Simulation time 166433064692 ps
CPU time 378.51 seconds
Started Apr 15 12:52:51 PM PDT 24
Finished Apr 15 12:59:10 PM PDT 24
Peak memory 202248 kb
Host smart-eda5c3d2-9a3d-432b-a0de-629ec97cc00d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811643304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2811643304
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2389847981
Short name T664
Test name
Test status
Simulation time 485139319878 ps
CPU time 1065.28 seconds
Started Apr 15 12:52:50 PM PDT 24
Finished Apr 15 01:10:36 PM PDT 24
Peak memory 202260 kb
Host smart-08cde3ce-1b5d-4f95-a2f3-8da4a657fba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389847981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2389847981
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.4142834452
Short name T595
Test name
Test status
Simulation time 161792418540 ps
CPU time 88.61 seconds
Started Apr 15 12:52:50 PM PDT 24
Finished Apr 15 12:54:19 PM PDT 24
Peak memory 202236 kb
Host smart-91438a67-5ab8-42f4-bf6b-2c69cb0e26e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142834452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.4142834452
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1697448150
Short name T776
Test name
Test status
Simulation time 582368940824 ps
CPU time 1273.4 seconds
Started Apr 15 12:52:50 PM PDT 24
Finished Apr 15 01:14:04 PM PDT 24
Peak memory 202344 kb
Host smart-e0d0deeb-01e2-43ba-bc95-db7d7fce3b30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697448150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1697448150
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1309384117
Short name T195
Test name
Test status
Simulation time 396226808806 ps
CPU time 488.25 seconds
Started Apr 15 12:52:55 PM PDT 24
Finished Apr 15 01:01:04 PM PDT 24
Peak memory 202208 kb
Host smart-feded141-6aa7-4013-874a-ab960fd85705
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309384117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1309384117
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3239127283
Short name T661
Test name
Test status
Simulation time 82982231322 ps
CPU time 427.88 seconds
Started Apr 15 12:52:56 PM PDT 24
Finished Apr 15 01:00:05 PM PDT 24
Peak memory 202676 kb
Host smart-3e8e0005-c61a-4470-b8a8-bf7e91fbb9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239127283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3239127283
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1666264788
Short name T527
Test name
Test status
Simulation time 42955580683 ps
CPU time 24.51 seconds
Started Apr 15 12:52:57 PM PDT 24
Finished Apr 15 12:53:22 PM PDT 24
Peak memory 202064 kb
Host smart-ba0902d3-f5e6-4aef-b8ec-058131f6c16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666264788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1666264788
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.22118726
Short name T749
Test name
Test status
Simulation time 5564344266 ps
CPU time 14.55 seconds
Started Apr 15 12:52:56 PM PDT 24
Finished Apr 15 12:53:11 PM PDT 24
Peak memory 202060 kb
Host smart-d8ad6f11-782e-4924-ae20-ceff63916f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22118726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.22118726
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2050138805
Short name T204
Test name
Test status
Simulation time 5976866261 ps
CPU time 2.9 seconds
Started Apr 15 12:52:50 PM PDT 24
Finished Apr 15 12:52:54 PM PDT 24
Peak memory 202104 kb
Host smart-f6910525-4135-47d4-bbb5-c1d71de50e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050138805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2050138805
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1705962381
Short name T278
Test name
Test status
Simulation time 212670975437 ps
CPU time 130.26 seconds
Started Apr 15 12:52:55 PM PDT 24
Finished Apr 15 12:55:06 PM PDT 24
Peak memory 202300 kb
Host smart-39da531f-9981-4f82-b2fa-295acd2ec479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705962381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1705962381
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.757053264
Short name T33
Test name
Test status
Simulation time 458191762423 ps
CPU time 786.9 seconds
Started Apr 15 12:52:56 PM PDT 24
Finished Apr 15 01:06:03 PM PDT 24
Peak memory 210904 kb
Host smart-7aef07d5-c590-4659-8621-09ae17ccc0ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757053264 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.757053264
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2732894164
Short name T430
Test name
Test status
Simulation time 281344719 ps
CPU time 1.25 seconds
Started Apr 15 12:53:06 PM PDT 24
Finished Apr 15 12:53:08 PM PDT 24
Peak memory 201972 kb
Host smart-6e8ac524-1233-4e1e-80c2-bc2d668358ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732894164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2732894164
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.811475286
Short name T343
Test name
Test status
Simulation time 373110110894 ps
CPU time 213.64 seconds
Started Apr 15 12:53:01 PM PDT 24
Finished Apr 15 12:56:36 PM PDT 24
Peak memory 202344 kb
Host smart-878a3be5-2578-4d4c-bf1e-60554b149c23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811475286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.811475286
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2514051810
Short name T272
Test name
Test status
Simulation time 390556051168 ps
CPU time 958.07 seconds
Started Apr 15 12:53:01 PM PDT 24
Finished Apr 15 01:09:00 PM PDT 24
Peak memory 202304 kb
Host smart-a3ba4223-c4b0-43b9-8bc5-96542144b052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514051810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2514051810
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.4225389426
Short name T787
Test name
Test status
Simulation time 340500648193 ps
CPU time 796.08 seconds
Started Apr 15 12:53:01 PM PDT 24
Finished Apr 15 01:06:17 PM PDT 24
Peak memory 202236 kb
Host smart-5d76fd98-7ecd-405f-91b1-dd20b8598e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225389426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.4225389426
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2432393723
Short name T642
Test name
Test status
Simulation time 167006861400 ps
CPU time 412.99 seconds
Started Apr 15 12:53:00 PM PDT 24
Finished Apr 15 12:59:53 PM PDT 24
Peak memory 202232 kb
Host smart-9c97cbb3-cc73-4cc1-822f-302ec9ba0afd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432393723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2432393723
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2181717597
Short name T319
Test name
Test status
Simulation time 163840312687 ps
CPU time 137.84 seconds
Started Apr 15 12:53:00 PM PDT 24
Finished Apr 15 12:55:18 PM PDT 24
Peak memory 202276 kb
Host smart-a6a4c15f-330d-4e8c-816b-a9857b504811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181717597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2181717597
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3478420865
Short name T414
Test name
Test status
Simulation time 163089583831 ps
CPU time 173.54 seconds
Started Apr 15 12:53:00 PM PDT 24
Finished Apr 15 12:55:54 PM PDT 24
Peak memory 202268 kb
Host smart-79d7839d-a073-4a9e-8582-849316b02728
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478420865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3478420865
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2103014829
Short name T271
Test name
Test status
Simulation time 262317541289 ps
CPU time 112.96 seconds
Started Apr 15 12:52:59 PM PDT 24
Finished Apr 15 12:54:52 PM PDT 24
Peak memory 202276 kb
Host smart-c9480e2c-7ef8-4c0f-af38-abc3b911ea3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103014829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2103014829
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2847699917
Short name T494
Test name
Test status
Simulation time 600303394494 ps
CPU time 728.18 seconds
Started Apr 15 12:53:00 PM PDT 24
Finished Apr 15 01:05:09 PM PDT 24
Peak memory 202248 kb
Host smart-6fd916db-6c98-4131-b41c-a117dd2394b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847699917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2847699917
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.648186155
Short name T214
Test name
Test status
Simulation time 108537872400 ps
CPU time 431.76 seconds
Started Apr 15 12:53:05 PM PDT 24
Finished Apr 15 01:00:17 PM PDT 24
Peak memory 202656 kb
Host smart-e6b05d86-ba04-416e-b635-a94baa0a5449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648186155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.648186155
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2477350403
Short name T467
Test name
Test status
Simulation time 37221107477 ps
CPU time 11.61 seconds
Started Apr 15 12:53:03 PM PDT 24
Finished Apr 15 12:53:15 PM PDT 24
Peak memory 202064 kb
Host smart-7b118dd8-8cf7-4edb-90be-602f085bc2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477350403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2477350403
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3905428595
Short name T400
Test name
Test status
Simulation time 2904211659 ps
CPU time 7.45 seconds
Started Apr 15 12:53:04 PM PDT 24
Finished Apr 15 12:53:11 PM PDT 24
Peak memory 202072 kb
Host smart-342ad9f4-5f9a-407c-83bb-5664d7141141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905428595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3905428595
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3245827795
Short name T558
Test name
Test status
Simulation time 5788409526 ps
CPU time 3.91 seconds
Started Apr 15 12:53:00 PM PDT 24
Finished Apr 15 12:53:04 PM PDT 24
Peak memory 202016 kb
Host smart-5774fb10-8751-42c3-831e-7f36044c1666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245827795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3245827795
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2646704126
Short name T170
Test name
Test status
Simulation time 371145249226 ps
CPU time 233.35 seconds
Started Apr 15 12:53:05 PM PDT 24
Finished Apr 15 12:56:59 PM PDT 24
Peak memory 202368 kb
Host smart-00d6ed4a-9d60-44a0-aee1-bc14c0eb76aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646704126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2646704126
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3434861498
Short name T421
Test name
Test status
Simulation time 26321370197 ps
CPU time 84.63 seconds
Started Apr 15 12:53:06 PM PDT 24
Finished Apr 15 12:54:31 PM PDT 24
Peak memory 210988 kb
Host smart-dd6f2ba1-e71a-4520-b82f-8f58bd76db37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434861498 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3434861498
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2963908096
Short name T367
Test name
Test status
Simulation time 413127862 ps
CPU time 1.6 seconds
Started Apr 15 12:53:15 PM PDT 24
Finished Apr 15 12:53:17 PM PDT 24
Peak memory 201928 kb
Host smart-e89a4e59-bd2a-40c7-aca7-d9759b5af01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963908096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2963908096
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1685034876
Short name T316
Test name
Test status
Simulation time 321286471966 ps
CPU time 651.21 seconds
Started Apr 15 12:53:10 PM PDT 24
Finished Apr 15 01:04:02 PM PDT 24
Peak memory 202344 kb
Host smart-a0a87a47-23c8-47ad-b5dc-5106ec59b60c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685034876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1685034876
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2129960352
Short name T783
Test name
Test status
Simulation time 166195732710 ps
CPU time 105.77 seconds
Started Apr 15 12:53:11 PM PDT 24
Finished Apr 15 12:54:57 PM PDT 24
Peak memory 202284 kb
Host smart-5ad62037-2f2a-47ae-9cba-36bb5b89ef17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129960352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2129960352
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3898242894
Short name T409
Test name
Test status
Simulation time 490066827218 ps
CPU time 653.61 seconds
Started Apr 15 12:53:11 PM PDT 24
Finished Apr 15 01:04:05 PM PDT 24
Peak memory 202216 kb
Host smart-be8b6718-9dc5-47d0-9164-d90947a2bd0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898242894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3898242894
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2758182003
Short name T704
Test name
Test status
Simulation time 336439180787 ps
CPU time 206.51 seconds
Started Apr 15 12:53:10 PM PDT 24
Finished Apr 15 12:56:38 PM PDT 24
Peak memory 202300 kb
Host smart-8c0b635b-56f4-4a80-9c87-55ba42849423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758182003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2758182003
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3899661602
Short name T793
Test name
Test status
Simulation time 164573231599 ps
CPU time 97.37 seconds
Started Apr 15 12:53:11 PM PDT 24
Finished Apr 15 12:54:49 PM PDT 24
Peak memory 202280 kb
Host smart-0121acdd-213d-47b3-ac46-80279885f0f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899661602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3899661602
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2358483310
Short name T735
Test name
Test status
Simulation time 413378088605 ps
CPU time 236.74 seconds
Started Apr 15 12:53:10 PM PDT 24
Finished Apr 15 12:57:07 PM PDT 24
Peak memory 202116 kb
Host smart-611a9276-5b0c-4863-9e12-d27c2326fd70
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358483310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2358483310
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4099048744
Short name T565
Test name
Test status
Simulation time 79331150366 ps
CPU time 452.26 seconds
Started Apr 15 12:53:10 PM PDT 24
Finished Apr 15 01:00:42 PM PDT 24
Peak memory 202576 kb
Host smart-5123df18-ded7-4d20-b07b-d45657d5cd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099048744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4099048744
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.941878370
Short name T784
Test name
Test status
Simulation time 42141520205 ps
CPU time 23.35 seconds
Started Apr 15 12:53:09 PM PDT 24
Finished Apr 15 12:53:33 PM PDT 24
Peak memory 202068 kb
Host smart-1e223d24-24c3-4690-868e-a183e83f72da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941878370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.941878370
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.6378651
Short name T755
Test name
Test status
Simulation time 5458731264 ps
CPU time 11.44 seconds
Started Apr 15 12:53:09 PM PDT 24
Finished Apr 15 12:53:21 PM PDT 24
Peak memory 202044 kb
Host smart-615377dc-2876-44ce-80bf-eab2c632a7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6378651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.6378651
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.515479608
Short name T663
Test name
Test status
Simulation time 5924857430 ps
CPU time 3.93 seconds
Started Apr 15 12:53:07 PM PDT 24
Finished Apr 15 12:53:11 PM PDT 24
Peak memory 201956 kb
Host smart-c2d141f8-0b9e-4866-82f8-69c782817ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515479608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.515479608
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.521384110
Short name T71
Test name
Test status
Simulation time 1546110455252 ps
CPU time 3593.46 seconds
Started Apr 15 12:53:10 PM PDT 24
Finished Apr 15 01:53:04 PM PDT 24
Peak memory 210640 kb
Host smart-076f378a-780f-4db6-8060-e09f357a5565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521384110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
521384110
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1646191298
Short name T771
Test name
Test status
Simulation time 501625097 ps
CPU time 1.8 seconds
Started Apr 15 12:53:23 PM PDT 24
Finished Apr 15 12:53:25 PM PDT 24
Peak memory 201968 kb
Host smart-eab6f9ef-210e-4c0b-b353-141aff530c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646191298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1646191298
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1521198397
Short name T566
Test name
Test status
Simulation time 161603404751 ps
CPU time 111.05 seconds
Started Apr 15 12:53:14 PM PDT 24
Finished Apr 15 12:55:06 PM PDT 24
Peak memory 202212 kb
Host smart-108f7289-6ff0-4c8f-bb26-1a166fb2247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521198397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1521198397
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1201182534
Short name T484
Test name
Test status
Simulation time 330357298439 ps
CPU time 205.57 seconds
Started Apr 15 12:53:16 PM PDT 24
Finished Apr 15 12:56:42 PM PDT 24
Peak memory 202236 kb
Host smart-714d8891-77ba-48af-9813-6910714c25c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201182534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1201182534
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.920036277
Short name T90
Test name
Test status
Simulation time 163705752493 ps
CPU time 97.41 seconds
Started Apr 15 12:53:15 PM PDT 24
Finished Apr 15 12:54:52 PM PDT 24
Peak memory 202204 kb
Host smart-b9b83aa7-0c44-4c70-95ae-795ca0c83f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920036277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.920036277
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3336048117
Short name T591
Test name
Test status
Simulation time 332000897814 ps
CPU time 755.86 seconds
Started Apr 15 12:53:15 PM PDT 24
Finished Apr 15 01:05:52 PM PDT 24
Peak memory 202244 kb
Host smart-77201302-5465-4fb3-8659-8d2f4926d49b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336048117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3336048117
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1080806944
Short name T200
Test name
Test status
Simulation time 398861709676 ps
CPU time 199.2 seconds
Started Apr 15 12:53:14 PM PDT 24
Finished Apr 15 12:56:34 PM PDT 24
Peak memory 202316 kb
Host smart-41e319d1-5ece-4ce8-92a2-cd684ac21e1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080806944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1080806944
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.97302209
Short name T799
Test name
Test status
Simulation time 196894066906 ps
CPU time 254.09 seconds
Started Apr 15 12:53:19 PM PDT 24
Finished Apr 15 12:57:34 PM PDT 24
Peak memory 202192 kb
Host smart-1cb174ef-d7a4-4342-960d-03629bc8640b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97302209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.a
dc_ctrl_filters_wakeup_fixed.97302209
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3501614666
Short name T219
Test name
Test status
Simulation time 110730591582 ps
CPU time 416.08 seconds
Started Apr 15 12:53:21 PM PDT 24
Finished Apr 15 01:00:18 PM PDT 24
Peak memory 202652 kb
Host smart-7031af81-ad56-4ee4-84d3-30b248d074c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501614666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3501614666
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2330357994
Short name T529
Test name
Test status
Simulation time 40787936246 ps
CPU time 48.2 seconds
Started Apr 15 12:53:19 PM PDT 24
Finished Apr 15 12:54:07 PM PDT 24
Peak memory 202064 kb
Host smart-ea3125a0-e8fd-4cbe-a36d-9be3251fbf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330357994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2330357994
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1697861352
Short name T647
Test name
Test status
Simulation time 4828870267 ps
CPU time 10.7 seconds
Started Apr 15 12:53:19 PM PDT 24
Finished Apr 15 12:53:30 PM PDT 24
Peak memory 202060 kb
Host smart-7067f566-4831-4722-9b32-c44d10c9e5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697861352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1697861352
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.943357541
Short name T435
Test name
Test status
Simulation time 5911419032 ps
CPU time 3.4 seconds
Started Apr 15 12:53:13 PM PDT 24
Finished Apr 15 12:53:17 PM PDT 24
Peak memory 202100 kb
Host smart-cc4e8f61-bcbb-4949-adcc-a9478622841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943357541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.943357541
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.4061486101
Short name T58
Test name
Test status
Simulation time 164742196945 ps
CPU time 96.72 seconds
Started Apr 15 12:53:24 PM PDT 24
Finished Apr 15 12:55:01 PM PDT 24
Peak memory 202268 kb
Host smart-c9ac99fe-8f37-476b-859b-0b881157e52f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061486101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.4061486101
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.152084908
Short name T766
Test name
Test status
Simulation time 385297263 ps
CPU time 1.09 seconds
Started Apr 15 12:53:32 PM PDT 24
Finished Apr 15 12:53:34 PM PDT 24
Peak memory 201976 kb
Host smart-196d0e3a-55c4-41a1-9d10-75b2edeb55ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152084908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.152084908
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.174207556
Short name T335
Test name
Test status
Simulation time 351718519200 ps
CPU time 231.46 seconds
Started Apr 15 12:53:27 PM PDT 24
Finished Apr 15 12:57:19 PM PDT 24
Peak memory 202300 kb
Host smart-59dacad5-f38b-47df-adcf-45df67bc84a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174207556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.174207556
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.4079825560
Short name T628
Test name
Test status
Simulation time 170839631265 ps
CPU time 108.44 seconds
Started Apr 15 12:53:29 PM PDT 24
Finished Apr 15 12:55:17 PM PDT 24
Peak memory 202284 kb
Host smart-aced4921-b4d0-4c8e-af78-fabe8725744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079825560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4079825560
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3081591814
Short name T692
Test name
Test status
Simulation time 482598563564 ps
CPU time 302.99 seconds
Started Apr 15 12:53:23 PM PDT 24
Finished Apr 15 12:58:26 PM PDT 24
Peak memory 202324 kb
Host smart-2b6902f3-bd48-4b5b-8c7d-53494937e017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081591814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3081591814
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.4013601820
Short name T649
Test name
Test status
Simulation time 497038578080 ps
CPU time 1152.82 seconds
Started Apr 15 12:53:23 PM PDT 24
Finished Apr 15 01:12:36 PM PDT 24
Peak memory 202292 kb
Host smart-72393a9e-ead6-450f-b500-e5ee17f8bb36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013601820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.4013601820
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2091626440
Short name T737
Test name
Test status
Simulation time 336001748295 ps
CPU time 409.76 seconds
Started Apr 15 12:53:24 PM PDT 24
Finished Apr 15 01:00:14 PM PDT 24
Peak memory 202268 kb
Host smart-2228305e-47fa-4c96-94bc-1e57b7735cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091626440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2091626440
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1339947640
Short name T4
Test name
Test status
Simulation time 164547113997 ps
CPU time 331.55 seconds
Started Apr 15 12:53:22 PM PDT 24
Finished Apr 15 12:58:54 PM PDT 24
Peak memory 202264 kb
Host smart-8b0c91f2-0181-40a9-a8ac-74215b1dc0ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339947640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1339947640
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1522148971
Short name T609
Test name
Test status
Simulation time 170441700944 ps
CPU time 384.3 seconds
Started Apr 15 12:53:27 PM PDT 24
Finished Apr 15 12:59:51 PM PDT 24
Peak memory 202244 kb
Host smart-2845dd0c-4193-488f-8b23-d0d031be6ac7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522148971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1522148971
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3223218196
Short name T508
Test name
Test status
Simulation time 205438981157 ps
CPU time 353.19 seconds
Started Apr 15 12:53:25 PM PDT 24
Finished Apr 15 12:59:18 PM PDT 24
Peak memory 202244 kb
Host smart-53aa8aee-7449-4952-9d43-f57550658427
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223218196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3223218196
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2175685112
Short name T485
Test name
Test status
Simulation time 43945699732 ps
CPU time 52.53 seconds
Started Apr 15 12:53:33 PM PDT 24
Finished Apr 15 12:54:26 PM PDT 24
Peak memory 202084 kb
Host smart-4049af2e-21ae-4a39-bb1f-a612e3ca8a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175685112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2175685112
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2568864168
Short name T425
Test name
Test status
Simulation time 2776192273 ps
CPU time 2.18 seconds
Started Apr 15 12:53:32 PM PDT 24
Finished Apr 15 12:53:34 PM PDT 24
Peak memory 202080 kb
Host smart-850b2554-d608-4b11-9720-a8eb6c325736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568864168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2568864168
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3431323926
Short name T751
Test name
Test status
Simulation time 5967396923 ps
CPU time 14.42 seconds
Started Apr 15 12:53:22 PM PDT 24
Finished Apr 15 12:53:36 PM PDT 24
Peak memory 202060 kb
Host smart-a9faa153-3378-4734-aaf8-5c2707709c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431323926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3431323926
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1852530605
Short name T247
Test name
Test status
Simulation time 196687625466 ps
CPU time 116.85 seconds
Started Apr 15 12:53:35 PM PDT 24
Finished Apr 15 12:55:33 PM PDT 24
Peak memory 202184 kb
Host smart-a85001a3-1695-4e31-b2be-5ecc73557d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852530605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1852530605
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2150697165
Short name T631
Test name
Test status
Simulation time 384554573 ps
CPU time 1.46 seconds
Started Apr 15 12:53:40 PM PDT 24
Finished Apr 15 12:53:42 PM PDT 24
Peak memory 201920 kb
Host smart-0a25479a-c8f4-4ad0-9189-193cf3f1a12b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150697165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2150697165
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2972782438
Short name T180
Test name
Test status
Simulation time 165270211179 ps
CPU time 96.82 seconds
Started Apr 15 12:53:36 PM PDT 24
Finished Apr 15 12:55:14 PM PDT 24
Peak memory 202084 kb
Host smart-e1096b89-efad-450f-b1f9-f937896f3b8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972782438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2972782438
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1876719164
Short name T159
Test name
Test status
Simulation time 325617448087 ps
CPU time 164.69 seconds
Started Apr 15 12:53:36 PM PDT 24
Finished Apr 15 12:56:21 PM PDT 24
Peak memory 202296 kb
Host smart-ad1f359a-03eb-433a-ae84-96c77b72581a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876719164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1876719164
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.458701906
Short name T551
Test name
Test status
Simulation time 162320386865 ps
CPU time 85.48 seconds
Started Apr 15 12:53:36 PM PDT 24
Finished Apr 15 12:55:02 PM PDT 24
Peak memory 202204 kb
Host smart-14c117af-871f-4873-86ca-33ce91cbc5ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=458701906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.458701906
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1870870294
Short name T331
Test name
Test status
Simulation time 489773688615 ps
CPU time 1094.49 seconds
Started Apr 15 12:53:37 PM PDT 24
Finished Apr 15 01:11:52 PM PDT 24
Peak memory 202232 kb
Host smart-10ea2026-ab4a-41c9-9049-9badc203edb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870870294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1870870294
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.4026574013
Short name T588
Test name
Test status
Simulation time 484455309189 ps
CPU time 957.54 seconds
Started Apr 15 12:53:36 PM PDT 24
Finished Apr 15 01:09:34 PM PDT 24
Peak memory 202176 kb
Host smart-9af17bef-369e-44d8-b46d-d71bdbbf06f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026574013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.4026574013
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1366423770
Short name T785
Test name
Test status
Simulation time 603587444016 ps
CPU time 332.97 seconds
Started Apr 15 12:53:38 PM PDT 24
Finished Apr 15 12:59:11 PM PDT 24
Peak memory 202200 kb
Host smart-d5e7a171-080e-4c93-915b-f3c6c5ab8459
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366423770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1366423770
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1548900074
Short name T462
Test name
Test status
Simulation time 43436070000 ps
CPU time 5.98 seconds
Started Apr 15 12:53:44 PM PDT 24
Finished Apr 15 12:53:50 PM PDT 24
Peak memory 202064 kb
Host smart-e2a228f1-78d6-426b-a033-c005d82c789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548900074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1548900074
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2886983555
Short name T705
Test name
Test status
Simulation time 3138103478 ps
CPU time 7.97 seconds
Started Apr 15 12:53:40 PM PDT 24
Finished Apr 15 12:53:48 PM PDT 24
Peak memory 202012 kb
Host smart-3be8fe3a-61e4-46aa-93f0-f0220825d25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886983555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2886983555
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1646679298
Short name T640
Test name
Test status
Simulation time 5864373177 ps
CPU time 1.7 seconds
Started Apr 15 12:53:33 PM PDT 24
Finished Apr 15 12:53:35 PM PDT 24
Peak memory 201948 kb
Host smart-0a9073b5-d17f-422f-a67d-53cda36ee1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646679298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1646679298
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1551586238
Short name T17
Test name
Test status
Simulation time 74164796470 ps
CPU time 167.49 seconds
Started Apr 15 12:53:39 PM PDT 24
Finished Apr 15 12:56:27 PM PDT 24
Peak memory 210596 kb
Host smart-f6669df3-cfff-4cff-a0a7-abdeaf74c454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551586238 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1551586238
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3748023517
Short name T544
Test name
Test status
Simulation time 308483948 ps
CPU time 0.97 seconds
Started Apr 15 12:53:51 PM PDT 24
Finished Apr 15 12:53:53 PM PDT 24
Peak memory 202000 kb
Host smart-035886f0-fb1d-4278-956c-238366ec82cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748023517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3748023517
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1125561162
Short name T300
Test name
Test status
Simulation time 567165888480 ps
CPU time 601.13 seconds
Started Apr 15 12:53:49 PM PDT 24
Finished Apr 15 01:03:51 PM PDT 24
Peak memory 202064 kb
Host smart-241f1a0d-76ad-48e0-9d93-a15bfbe88401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125561162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1125561162
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3199850839
Short name T676
Test name
Test status
Simulation time 168640365209 ps
CPU time 367.11 seconds
Started Apr 15 12:53:48 PM PDT 24
Finished Apr 15 12:59:56 PM PDT 24
Peak memory 202332 kb
Host smart-9407cff2-d2b0-443c-a5af-a125085f46c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199850839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3199850839
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2800772728
Short name T629
Test name
Test status
Simulation time 322758509577 ps
CPU time 197.64 seconds
Started Apr 15 12:53:46 PM PDT 24
Finished Apr 15 12:57:04 PM PDT 24
Peak memory 202228 kb
Host smart-c98a95ca-d8ff-499b-883f-b49147c623b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800772728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2800772728
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2970540221
Short name T548
Test name
Test status
Simulation time 488707984355 ps
CPU time 127.42 seconds
Started Apr 15 12:53:45 PM PDT 24
Finished Apr 15 12:55:53 PM PDT 24
Peak memory 202324 kb
Host smart-66da1abc-46c8-4f81-ac06-0a2c664e9e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970540221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2970540221
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1992722150
Short name T513
Test name
Test status
Simulation time 165288825427 ps
CPU time 189.94 seconds
Started Apr 15 12:53:45 PM PDT 24
Finished Apr 15 12:56:55 PM PDT 24
Peak memory 202248 kb
Host smart-16df8a9d-2a64-49fe-bc8a-4b81c1ccb52c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992722150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1992722150
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1209482328
Short name T284
Test name
Test status
Simulation time 340394948408 ps
CPU time 763.62 seconds
Started Apr 15 12:53:47 PM PDT 24
Finished Apr 15 01:06:31 PM PDT 24
Peak memory 202288 kb
Host smart-a9720799-b25e-4c26-9b55-972e5311646f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209482328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1209482328
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.60043411
Short name T371
Test name
Test status
Simulation time 404081633491 ps
CPU time 983.41 seconds
Started Apr 15 12:53:48 PM PDT 24
Finished Apr 15 01:10:12 PM PDT 24
Peak memory 202128 kb
Host smart-d3ac8576-43f6-46c4-b5b0-15672701ba4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60043411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.a
dc_ctrl_filters_wakeup_fixed.60043411
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.100670181
Short name T795
Test name
Test status
Simulation time 113382705130 ps
CPU time 357.59 seconds
Started Apr 15 12:53:50 PM PDT 24
Finished Apr 15 12:59:48 PM PDT 24
Peak memory 202552 kb
Host smart-042160b7-0d73-4db8-9e3a-68a2117f3ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100670181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.100670181
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3295387257
Short name T502
Test name
Test status
Simulation time 31204631802 ps
CPU time 5.64 seconds
Started Apr 15 12:53:52 PM PDT 24
Finished Apr 15 12:53:58 PM PDT 24
Peak memory 202024 kb
Host smart-cb5e9c03-8995-4f09-a608-a933f788ca5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295387257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3295387257
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.550307659
Short name T410
Test name
Test status
Simulation time 5032554754 ps
CPU time 9.27 seconds
Started Apr 15 12:53:55 PM PDT 24
Finished Apr 15 12:54:04 PM PDT 24
Peak memory 201976 kb
Host smart-e72f4915-7fff-4640-9283-151577374110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550307659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.550307659
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1015814664
Short name T779
Test name
Test status
Simulation time 5505131417 ps
CPU time 13.41 seconds
Started Apr 15 12:53:44 PM PDT 24
Finished Apr 15 12:53:57 PM PDT 24
Peak memory 202076 kb
Host smart-3f2c54b9-af1f-46ed-9d99-bda5454da118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015814664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1015814664
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2030307867
Short name T225
Test name
Test status
Simulation time 326576528807 ps
CPU time 735.15 seconds
Started Apr 15 12:53:50 PM PDT 24
Finished Apr 15 01:06:05 PM PDT 24
Peak memory 202332 kb
Host smart-ca9e49d7-8580-41d2-ac30-c4a9e27615c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030307867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2030307867
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2055869206
Short name T208
Test name
Test status
Simulation time 71808074873 ps
CPU time 89.33 seconds
Started Apr 15 12:53:51 PM PDT 24
Finished Apr 15 12:55:21 PM PDT 24
Peak memory 202452 kb
Host smart-e4ade977-0ea9-4cde-87ce-f9af136bb3f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055869206 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2055869206
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.424623903
Short name T602
Test name
Test status
Simulation time 346429303 ps
CPU time 0.99 seconds
Started Apr 15 12:50:49 PM PDT 24
Finished Apr 15 12:50:51 PM PDT 24
Peak memory 201960 kb
Host smart-db801624-21d0-4a5f-a86a-1c7a140b094c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424623903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.424623903
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3594729072
Short name T342
Test name
Test status
Simulation time 181127285567 ps
CPU time 197.96 seconds
Started Apr 15 12:50:48 PM PDT 24
Finished Apr 15 12:54:07 PM PDT 24
Peak memory 202272 kb
Host smart-69311ed2-1914-47bf-9ea7-6edf1528ef46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594729072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3594729072
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2359293850
Short name T719
Test name
Test status
Simulation time 264877790313 ps
CPU time 125.33 seconds
Started Apr 15 12:50:47 PM PDT 24
Finished Apr 15 12:52:53 PM PDT 24
Peak memory 202252 kb
Host smart-0bcefa13-8beb-42ea-8cd7-8bea952b7e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359293850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2359293850
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2248057179
Short name T172
Test name
Test status
Simulation time 328702214661 ps
CPU time 383.38 seconds
Started Apr 15 12:50:44 PM PDT 24
Finished Apr 15 12:57:08 PM PDT 24
Peak memory 202224 kb
Host smart-ceebcd00-c7b3-4ee8-81eb-a8759873780e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248057179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2248057179
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.107839622
Short name T161
Test name
Test status
Simulation time 328748818342 ps
CPU time 339.57 seconds
Started Apr 15 12:50:43 PM PDT 24
Finished Apr 15 12:56:23 PM PDT 24
Peak memory 202336 kb
Host smart-04b817ea-e4e9-40d7-8d1f-b3f95924ba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107839622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.107839622
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3148981890
Short name T716
Test name
Test status
Simulation time 164840446058 ps
CPU time 179.73 seconds
Started Apr 15 12:50:44 PM PDT 24
Finished Apr 15 12:53:44 PM PDT 24
Peak memory 202240 kb
Host smart-ef86c046-d0f8-4ba7-8c2f-931453a1713a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148981890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3148981890
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3428975052
Short name T447
Test name
Test status
Simulation time 189724847788 ps
CPU time 351.47 seconds
Started Apr 15 12:50:54 PM PDT 24
Finished Apr 15 12:56:46 PM PDT 24
Peak memory 201816 kb
Host smart-aa706a8c-3b27-4a75-88f9-862cfd8d93ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428975052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3428975052
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1492505973
Short name T617
Test name
Test status
Simulation time 75219372273 ps
CPU time 412.82 seconds
Started Apr 15 12:50:46 PM PDT 24
Finished Apr 15 12:57:40 PM PDT 24
Peak memory 202572 kb
Host smart-7ba20c43-4d12-48cf-b948-1ad434182d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492505973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1492505973
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.783913942
Short name T778
Test name
Test status
Simulation time 37967137760 ps
CPU time 17.29 seconds
Started Apr 15 12:50:55 PM PDT 24
Finished Apr 15 12:51:12 PM PDT 24
Peak memory 201936 kb
Host smart-158ce7a3-79e5-4991-909b-b023912bbddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783913942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.783913942
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.643337781
Short name T372
Test name
Test status
Simulation time 4007982325 ps
CPU time 1.97 seconds
Started Apr 15 12:50:49 PM PDT 24
Finished Apr 15 12:50:51 PM PDT 24
Peak memory 202096 kb
Host smart-2f79d903-4e17-4fe6-beab-611f888e860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643337781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.643337781
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1458311004
Short name T55
Test name
Test status
Simulation time 4170200430 ps
CPU time 9.55 seconds
Started Apr 15 12:50:47 PM PDT 24
Finished Apr 15 12:50:57 PM PDT 24
Peak memory 217804 kb
Host smart-2ea72ca3-cb17-4f15-a169-e21fdff5076e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458311004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1458311004
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.836735097
Short name T483
Test name
Test status
Simulation time 6133549461 ps
CPU time 8.72 seconds
Started Apr 15 12:50:45 PM PDT 24
Finished Apr 15 12:50:54 PM PDT 24
Peak memory 202080 kb
Host smart-ea0635b6-4541-4eba-90cd-55e016aaae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836735097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.836735097
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.6149713
Short name T710
Test name
Test status
Simulation time 50070818985 ps
CPU time 30.24 seconds
Started Apr 15 12:50:52 PM PDT 24
Finished Apr 15 12:51:23 PM PDT 24
Peak memory 202096 kb
Host smart-f7ec046d-3632-4e72-9c11-3d6e11ab9231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6149713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.6149713
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1573851326
Short name T763
Test name
Test status
Simulation time 249144802664 ps
CPU time 129.18 seconds
Started Apr 15 12:50:48 PM PDT 24
Finished Apr 15 12:52:57 PM PDT 24
Peak memory 210896 kb
Host smart-56a2bd5e-fa5a-420a-b946-8854b97ebfcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573851326 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1573851326
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2475310215
Short name T74
Test name
Test status
Simulation time 349844080 ps
CPU time 1.38 seconds
Started Apr 15 12:54:00 PM PDT 24
Finished Apr 15 12:54:02 PM PDT 24
Peak memory 201920 kb
Host smart-8b35ba00-1c5b-41fd-9df4-133e155c957e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475310215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2475310215
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3300777772
Short name T732
Test name
Test status
Simulation time 157807845300 ps
CPU time 105.24 seconds
Started Apr 15 12:53:55 PM PDT 24
Finished Apr 15 12:55:41 PM PDT 24
Peak memory 202216 kb
Host smart-d3ab0217-e9f4-4f14-b56d-1ac6f2426b19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300777772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3300777772
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1290534933
Short name T468
Test name
Test status
Simulation time 363317163326 ps
CPU time 230.56 seconds
Started Apr 15 12:53:58 PM PDT 24
Finished Apr 15 12:57:49 PM PDT 24
Peak memory 202236 kb
Host smart-980364d9-717e-48be-a1b0-a44ed6ec70dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290534933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1290534933
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3241572703
Short name T7
Test name
Test status
Simulation time 505238484099 ps
CPU time 1099.13 seconds
Started Apr 15 12:53:57 PM PDT 24
Finished Apr 15 01:12:17 PM PDT 24
Peak memory 202160 kb
Host smart-833f1602-5a94-4ab4-94eb-5a275d70e301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241572703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3241572703
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2676861455
Short name T574
Test name
Test status
Simulation time 159654024861 ps
CPU time 207.82 seconds
Started Apr 15 12:53:57 PM PDT 24
Finished Apr 15 12:57:26 PM PDT 24
Peak memory 202124 kb
Host smart-8518f712-1462-4e79-9540-09b57ade3da2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676861455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2676861455
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2474055201
Short name T167
Test name
Test status
Simulation time 495686802037 ps
CPU time 293.71 seconds
Started Apr 15 12:53:49 PM PDT 24
Finished Apr 15 12:58:44 PM PDT 24
Peak memory 202296 kb
Host smart-04427da0-763a-4cf1-bc4c-27d335509fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474055201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2474055201
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3396357919
Short name T512
Test name
Test status
Simulation time 323420604774 ps
CPU time 143.52 seconds
Started Apr 15 12:53:53 PM PDT 24
Finished Apr 15 12:56:16 PM PDT 24
Peak memory 202120 kb
Host smart-e078689f-ac6d-4ef6-9cb6-ab96366887de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396357919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3396357919
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2260945465
Short name T145
Test name
Test status
Simulation time 355991269742 ps
CPU time 843.26 seconds
Started Apr 15 12:53:57 PM PDT 24
Finished Apr 15 01:08:00 PM PDT 24
Peak memory 202160 kb
Host smart-dfe72bd6-f739-4e8c-9b17-17c0ee85b7b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260945465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2260945465
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1201012513
Short name T496
Test name
Test status
Simulation time 197945803695 ps
CPU time 458.66 seconds
Started Apr 15 12:53:53 PM PDT 24
Finished Apr 15 01:01:32 PM PDT 24
Peak memory 202224 kb
Host smart-ff2a5efe-9868-4544-b193-16dba072faff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201012513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1201012513
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.148519010
Short name T354
Test name
Test status
Simulation time 73226217981 ps
CPU time 356.67 seconds
Started Apr 15 12:53:59 PM PDT 24
Finished Apr 15 12:59:56 PM PDT 24
Peak memory 202588 kb
Host smart-2f1889eb-6d28-4f02-85ef-3cb80acb8704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148519010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.148519010
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3639133881
Short name T364
Test name
Test status
Simulation time 41032684118 ps
CPU time 24.53 seconds
Started Apr 15 12:53:54 PM PDT 24
Finished Apr 15 12:54:18 PM PDT 24
Peak memory 202112 kb
Host smart-cb271fce-c5d3-4b5d-9cf0-83edb1184323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639133881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3639133881
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2408087710
Short name T444
Test name
Test status
Simulation time 4918303750 ps
CPU time 6.45 seconds
Started Apr 15 12:53:54 PM PDT 24
Finished Apr 15 12:54:00 PM PDT 24
Peak memory 202104 kb
Host smart-a6eec886-d65a-4507-8c9f-a4d8d1ad1431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408087710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2408087710
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2087954658
Short name T197
Test name
Test status
Simulation time 5834334925 ps
CPU time 2.9 seconds
Started Apr 15 12:53:54 PM PDT 24
Finished Apr 15 12:53:58 PM PDT 24
Peak memory 202076 kb
Host smart-3444ee1a-e495-44de-b873-243a1f80e770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087954658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2087954658
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3486434470
Short name T493
Test name
Test status
Simulation time 269133817194 ps
CPU time 161.06 seconds
Started Apr 15 12:53:59 PM PDT 24
Finished Apr 15 12:56:41 PM PDT 24
Peak memory 202244 kb
Host smart-e2908a09-334e-4116-924a-4763ddbbdce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486434470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3486434470
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2784396392
Short name T31
Test name
Test status
Simulation time 61288277994 ps
CPU time 207.01 seconds
Started Apr 15 12:54:00 PM PDT 24
Finished Apr 15 12:57:27 PM PDT 24
Peak memory 218328 kb
Host smart-bfebc972-7d17-4136-9939-68e318e51ac2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784396392 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2784396392
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2043355961
Short name T554
Test name
Test status
Simulation time 370242300 ps
CPU time 0.82 seconds
Started Apr 15 12:54:08 PM PDT 24
Finished Apr 15 12:54:09 PM PDT 24
Peak memory 201992 kb
Host smart-af54a54e-8be8-476f-88b9-c982e2a6273c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043355961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2043355961
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1617047600
Short name T233
Test name
Test status
Simulation time 518801576030 ps
CPU time 435.32 seconds
Started Apr 15 12:54:08 PM PDT 24
Finished Apr 15 01:01:23 PM PDT 24
Peak memory 202264 kb
Host smart-977c6ca8-300b-425c-b038-259a67093bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617047600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1617047600
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.573995303
Short name T262
Test name
Test status
Simulation time 162761262629 ps
CPU time 106 seconds
Started Apr 15 12:54:06 PM PDT 24
Finished Apr 15 12:55:52 PM PDT 24
Peak memory 202316 kb
Host smart-40b76cd4-7728-45b6-b801-2254913cd1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573995303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.573995303
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.657704202
Short name T619
Test name
Test status
Simulation time 157096873835 ps
CPU time 363.47 seconds
Started Apr 15 12:54:04 PM PDT 24
Finished Apr 15 01:00:08 PM PDT 24
Peak memory 202368 kb
Host smart-26d32168-90d5-45db-afdb-6769984ced7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=657704202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.657704202
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1254750912
Short name T341
Test name
Test status
Simulation time 490220945578 ps
CPU time 1196.21 seconds
Started Apr 15 12:54:05 PM PDT 24
Finished Apr 15 01:14:02 PM PDT 24
Peak memory 202260 kb
Host smart-12eed2e5-d541-48ac-a155-2f9fc75970a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254750912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1254750912
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1792669145
Short name T733
Test name
Test status
Simulation time 163993585022 ps
CPU time 188.93 seconds
Started Apr 15 12:54:03 PM PDT 24
Finished Apr 15 12:57:12 PM PDT 24
Peak memory 202228 kb
Host smart-28c3f57a-bd06-4161-b402-81d095aa92a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792669145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1792669145
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1470140154
Short name T146
Test name
Test status
Simulation time 362872735282 ps
CPU time 835.17 seconds
Started Apr 15 12:54:04 PM PDT 24
Finished Apr 15 01:08:00 PM PDT 24
Peak memory 202272 kb
Host smart-c0075415-e6f4-46a3-a623-af8bc7b4e430
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470140154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1470140154
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2642956366
Short name T454
Test name
Test status
Simulation time 400191899013 ps
CPU time 56.35 seconds
Started Apr 15 12:54:04 PM PDT 24
Finished Apr 15 12:55:01 PM PDT 24
Peak memory 202300 kb
Host smart-04dec905-4a4e-4a62-a4f4-894c8482e755
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642956366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2642956366
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.4289098937
Short name T428
Test name
Test status
Simulation time 111889928654 ps
CPU time 614.91 seconds
Started Apr 15 12:54:11 PM PDT 24
Finished Apr 15 01:04:27 PM PDT 24
Peak memory 202568 kb
Host smart-bc2ec97d-2fd5-49da-991e-3a1094e5c31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289098937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.4289098937
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1002249740
Short name T616
Test name
Test status
Simulation time 41335490531 ps
CPU time 47.62 seconds
Started Apr 15 12:54:07 PM PDT 24
Finished Apr 15 12:54:55 PM PDT 24
Peak memory 202080 kb
Host smart-975832c2-acb1-4c7b-90b2-7a150d737674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002249740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1002249740
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3081524098
Short name T696
Test name
Test status
Simulation time 4454256470 ps
CPU time 2.81 seconds
Started Apr 15 12:54:10 PM PDT 24
Finished Apr 15 12:54:13 PM PDT 24
Peak memory 202076 kb
Host smart-edeffcb4-2681-4c21-9b40-b7bb1e1a0cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081524098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3081524098
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1516952655
Short name T381
Test name
Test status
Simulation time 6125343567 ps
CPU time 5.3 seconds
Started Apr 15 12:54:03 PM PDT 24
Finished Apr 15 12:54:08 PM PDT 24
Peak memory 202028 kb
Host smart-eddc9455-c0f8-4117-9790-486cb25fe97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516952655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1516952655
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2745326139
Short name T156
Test name
Test status
Simulation time 175387517500 ps
CPU time 379.67 seconds
Started Apr 15 12:54:09 PM PDT 24
Finished Apr 15 01:00:29 PM PDT 24
Peak memory 202344 kb
Host smart-0c52e0ba-3ac0-46bc-a7ff-8c82a30429fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745326139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2745326139
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1621565712
Short name T349
Test name
Test status
Simulation time 25294234024 ps
CPU time 75.11 seconds
Started Apr 15 12:54:09 PM PDT 24
Finished Apr 15 12:55:24 PM PDT 24
Peak memory 210916 kb
Host smart-b6b493ec-621f-43d9-ad0d-8c5755f792b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621565712 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1621565712
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1731174478
Short name T491
Test name
Test status
Simulation time 518623239 ps
CPU time 0.93 seconds
Started Apr 15 12:54:18 PM PDT 24
Finished Apr 15 12:54:20 PM PDT 24
Peak memory 201948 kb
Host smart-180f6bcb-f319-483b-8c96-3fef9154b9a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731174478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1731174478
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3921639132
Short name T260
Test name
Test status
Simulation time 164902040936 ps
CPU time 122.39 seconds
Started Apr 15 12:54:16 PM PDT 24
Finished Apr 15 12:56:19 PM PDT 24
Peak memory 202324 kb
Host smart-fbdb4b3e-099a-47d8-834c-d17a7d13c925
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921639132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3921639132
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2456003122
Short name T169
Test name
Test status
Simulation time 499872582286 ps
CPU time 159.84 seconds
Started Apr 15 12:54:11 PM PDT 24
Finished Apr 15 12:56:51 PM PDT 24
Peak memory 202256 kb
Host smart-76fc05b4-da6e-4077-85c4-33af3f0aba9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456003122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2456003122
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3808647485
Short name T23
Test name
Test status
Simulation time 329827155898 ps
CPU time 391.14 seconds
Started Apr 15 12:54:09 PM PDT 24
Finished Apr 15 01:00:40 PM PDT 24
Peak memory 202164 kb
Host smart-5d5dd8c8-8445-4980-bd06-2e46475e19ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808647485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3808647485
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3716362945
Short name T130
Test name
Test status
Simulation time 488753051339 ps
CPU time 288.92 seconds
Started Apr 15 12:54:09 PM PDT 24
Finished Apr 15 12:58:58 PM PDT 24
Peak memory 202268 kb
Host smart-1428414d-b34c-47a9-a248-2700cc762bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716362945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3716362945
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.492384143
Short name T528
Test name
Test status
Simulation time 335681608186 ps
CPU time 409.15 seconds
Started Apr 15 12:54:07 PM PDT 24
Finished Apr 15 01:00:57 PM PDT 24
Peak memory 202272 kb
Host smart-dc0ea077-f0fc-4b3e-8390-9cae75e0081a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=492384143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.492384143
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.289889847
Short name T298
Test name
Test status
Simulation time 549402329503 ps
CPU time 334.9 seconds
Started Apr 15 12:54:12 PM PDT 24
Finished Apr 15 12:59:47 PM PDT 24
Peak memory 202260 kb
Host smart-2f6e8617-83eb-4540-bec0-fb02137741cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289889847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.289889847
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1490740157
Short name T681
Test name
Test status
Simulation time 212857818763 ps
CPU time 506.35 seconds
Started Apr 15 12:54:13 PM PDT 24
Finished Apr 15 01:02:40 PM PDT 24
Peak memory 202196 kb
Host smart-e877ac8b-bd7d-40e1-bea8-7bb90f41f674
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490740157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1490740157
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2719581131
Short name T42
Test name
Test status
Simulation time 85894769548 ps
CPU time 357.26 seconds
Started Apr 15 12:54:18 PM PDT 24
Finished Apr 15 01:00:16 PM PDT 24
Peak memory 202552 kb
Host smart-ace42092-5916-47dc-a073-e568170366fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719581131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2719581131
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3658025083
Short name T686
Test name
Test status
Simulation time 33135189915 ps
CPU time 19.28 seconds
Started Apr 15 12:54:17 PM PDT 24
Finished Apr 15 12:54:36 PM PDT 24
Peak memory 202100 kb
Host smart-8b68e726-745a-4e01-ab26-5c40b035b6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658025083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3658025083
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2121981170
Short name T397
Test name
Test status
Simulation time 5432957068 ps
CPU time 12.66 seconds
Started Apr 15 12:54:17 PM PDT 24
Finished Apr 15 12:54:30 PM PDT 24
Peak memory 202064 kb
Host smart-02bc5c37-937f-4858-a8a7-3cd5b632e712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121981170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2121981170
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2326600683
Short name T115
Test name
Test status
Simulation time 5605296850 ps
CPU time 13.61 seconds
Started Apr 15 12:54:09 PM PDT 24
Finished Apr 15 12:54:23 PM PDT 24
Peak memory 202080 kb
Host smart-3db06b3c-9335-4332-bda8-637e96bf9524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326600683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2326600683
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1826620001
Short name T322
Test name
Test status
Simulation time 190538662232 ps
CPU time 123.59 seconds
Started Apr 15 12:54:19 PM PDT 24
Finished Apr 15 12:56:23 PM PDT 24
Peak memory 202520 kb
Host smart-baad498b-c6ad-4070-b2f3-621b7cf2a37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826620001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1826620001
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1240244799
Short name T257
Test name
Test status
Simulation time 57777503344 ps
CPU time 123.83 seconds
Started Apr 15 12:54:18 PM PDT 24
Finished Apr 15 12:56:22 PM PDT 24
Peak memory 218716 kb
Host smart-d140d199-adce-4939-9151-2f2a315be98e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240244799 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1240244799
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3386524744
Short name T748
Test name
Test status
Simulation time 487960756 ps
CPU time 1.67 seconds
Started Apr 15 12:54:28 PM PDT 24
Finished Apr 15 12:54:30 PM PDT 24
Peak memory 202000 kb
Host smart-aec7ba40-ba5f-4dd8-97bf-f52dc2534df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386524744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3386524744
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2466703441
Short name T254
Test name
Test status
Simulation time 497120181672 ps
CPU time 1118.33 seconds
Started Apr 15 12:54:22 PM PDT 24
Finished Apr 15 01:13:01 PM PDT 24
Peak memory 202296 kb
Host smart-9cd32218-18da-46e6-a2ac-94f2749425d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466703441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2466703441
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.331762545
Short name T560
Test name
Test status
Simulation time 161622283190 ps
CPU time 177.94 seconds
Started Apr 15 12:54:43 PM PDT 24
Finished Apr 15 12:57:41 PM PDT 24
Peak memory 202160 kb
Host smart-1f925f20-3cc4-41a1-bddc-c025b874d97f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=331762545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.331762545
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.924806008
Short name T138
Test name
Test status
Simulation time 320685416243 ps
CPU time 51.82 seconds
Started Apr 15 12:54:18 PM PDT 24
Finished Apr 15 12:55:10 PM PDT 24
Peak memory 202340 kb
Host smart-51313555-b58c-4ca5-84ae-fafca57139b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924806008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.924806008
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.4134754659
Short name T539
Test name
Test status
Simulation time 158765216208 ps
CPU time 361.12 seconds
Started Apr 15 12:54:18 PM PDT 24
Finished Apr 15 01:00:20 PM PDT 24
Peak memory 202252 kb
Host smart-e92b1db2-64ef-4fe0-be7d-b4cd1441cf50
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134754659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.4134754659
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.83577922
Short name T149
Test name
Test status
Simulation time 539783820335 ps
CPU time 1230.72 seconds
Started Apr 15 12:54:23 PM PDT 24
Finished Apr 15 01:14:54 PM PDT 24
Peak memory 202212 kb
Host smart-e902a123-e14a-4b0b-ac56-909fc266c6db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83577922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_w
akeup.83577922
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1752743078
Short name T573
Test name
Test status
Simulation time 400565866727 ps
CPU time 933.29 seconds
Started Apr 15 12:54:21 PM PDT 24
Finished Apr 15 01:09:55 PM PDT 24
Peak memory 202312 kb
Host smart-59801fd5-6eb2-4377-b8da-548c8ff89893
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752743078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1752743078
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1473551454
Short name T564
Test name
Test status
Simulation time 31526356431 ps
CPU time 76.61 seconds
Started Apr 15 12:54:22 PM PDT 24
Finished Apr 15 12:55:39 PM PDT 24
Peak memory 201988 kb
Host smart-56731bf2-c66d-4bc0-a08a-0d23ea7f3790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473551454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1473551454
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1515987544
Short name T431
Test name
Test status
Simulation time 2785790280 ps
CPU time 2.33 seconds
Started Apr 15 12:54:21 PM PDT 24
Finished Apr 15 12:54:24 PM PDT 24
Peak memory 202064 kb
Host smart-b4ccfcd4-7f70-4661-9d40-45de2c92089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515987544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1515987544
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1681738760
Short name T174
Test name
Test status
Simulation time 5959619707 ps
CPU time 3.96 seconds
Started Apr 15 12:54:18 PM PDT 24
Finished Apr 15 12:54:23 PM PDT 24
Peak memory 202076 kb
Host smart-72856a72-a838-4fa1-9b62-ffc68818a1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681738760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1681738760
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2845343915
Short name T29
Test name
Test status
Simulation time 519125615024 ps
CPU time 238.79 seconds
Started Apr 15 12:54:27 PM PDT 24
Finished Apr 15 12:58:27 PM PDT 24
Peak memory 202280 kb
Host smart-0308d9aa-dcec-4d65-8dd1-eae403f82d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845343915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2845343915
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1650039013
Short name T323
Test name
Test status
Simulation time 235528024770 ps
CPU time 439.44 seconds
Started Apr 15 12:54:27 PM PDT 24
Finished Apr 15 01:01:47 PM PDT 24
Peak memory 210908 kb
Host smart-c2e369fc-6941-49e7-ae33-6278d4b6caec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650039013 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1650039013
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2647243326
Short name T469
Test name
Test status
Simulation time 479781603 ps
CPU time 1.61 seconds
Started Apr 15 12:54:37 PM PDT 24
Finished Apr 15 12:54:39 PM PDT 24
Peak memory 201972 kb
Host smart-3c2b636d-038e-4a79-9a3a-dda9b76b3ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647243326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2647243326
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1105984097
Short name T345
Test name
Test status
Simulation time 162076620036 ps
CPU time 368.53 seconds
Started Apr 15 12:54:30 PM PDT 24
Finished Apr 15 01:00:39 PM PDT 24
Peak memory 202348 kb
Host smart-cdb05077-26d2-4d12-b93e-867c9e881b86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105984097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1105984097
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1980353743
Short name T280
Test name
Test status
Simulation time 341601254366 ps
CPU time 413.76 seconds
Started Apr 15 12:54:37 PM PDT 24
Finished Apr 15 01:01:31 PM PDT 24
Peak memory 202248 kb
Host smart-477dd4de-aea7-4077-b09a-f4d2999f08ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980353743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1980353743
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.203840426
Short name T192
Test name
Test status
Simulation time 163413228946 ps
CPU time 100.42 seconds
Started Apr 15 12:54:33 PM PDT 24
Finished Apr 15 12:56:14 PM PDT 24
Peak memory 202536 kb
Host smart-1f6517d8-3b56-4cab-8971-b34c91a6b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203840426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.203840426
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1949786246
Short name T377
Test name
Test status
Simulation time 487365265059 ps
CPU time 332.09 seconds
Started Apr 15 12:54:32 PM PDT 24
Finished Apr 15 01:00:05 PM PDT 24
Peak memory 202184 kb
Host smart-e5fc1946-cad2-4d16-8588-13d779dab857
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949786246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1949786246
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3609427933
Short name T227
Test name
Test status
Simulation time 329076746205 ps
CPU time 400.29 seconds
Started Apr 15 12:54:31 PM PDT 24
Finished Apr 15 01:01:12 PM PDT 24
Peak memory 202328 kb
Host smart-1dd6fe64-71c3-4d25-ad98-fa8a7bc9d712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609427933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3609427933
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3118194666
Short name T613
Test name
Test status
Simulation time 170503071369 ps
CPU time 84.68 seconds
Started Apr 15 12:54:30 PM PDT 24
Finished Apr 15 12:55:56 PM PDT 24
Peak memory 202184 kb
Host smart-a2f7148c-288c-4188-a553-0962ffc126fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118194666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3118194666
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1895387242
Short name T618
Test name
Test status
Simulation time 514095556313 ps
CPU time 313.97 seconds
Started Apr 15 12:54:32 PM PDT 24
Finished Apr 15 12:59:46 PM PDT 24
Peak memory 202204 kb
Host smart-2959c732-619d-47f2-b42d-7a2e3b25ed66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895387242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1895387242
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2317135956
Short name T672
Test name
Test status
Simulation time 611852813188 ps
CPU time 762.18 seconds
Started Apr 15 12:54:32 PM PDT 24
Finished Apr 15 01:07:15 PM PDT 24
Peak memory 202184 kb
Host smart-c738dad7-058c-45c6-978c-ad1039337b56
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317135956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2317135956
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4187456782
Short name T220
Test name
Test status
Simulation time 92887370349 ps
CPU time 519.72 seconds
Started Apr 15 12:54:36 PM PDT 24
Finished Apr 15 01:03:16 PM PDT 24
Peak memory 202600 kb
Host smart-65ce7561-28ad-456d-8b57-2d4e4008c031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187456782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4187456782
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.4020384750
Short name T675
Test name
Test status
Simulation time 27551001605 ps
CPU time 16.89 seconds
Started Apr 15 12:54:36 PM PDT 24
Finished Apr 15 12:54:53 PM PDT 24
Peak memory 202092 kb
Host smart-6f05524a-c038-44b1-b587-bbc0d5ca73dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020384750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.4020384750
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.799100736
Short name T582
Test name
Test status
Simulation time 4188804994 ps
CPU time 3.56 seconds
Started Apr 15 12:54:36 PM PDT 24
Finished Apr 15 12:54:40 PM PDT 24
Peak memory 202060 kb
Host smart-4b981b4e-817b-4144-be05-49ba9584ba74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799100736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.799100736
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.39338266
Short name T460
Test name
Test status
Simulation time 5859425229 ps
CPU time 4.52 seconds
Started Apr 15 12:54:28 PM PDT 24
Finished Apr 15 12:54:33 PM PDT 24
Peak memory 202016 kb
Host smart-31ed3ff4-04af-4fc5-b642-dc020b40e5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39338266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.39338266
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1822651577
Short name T670
Test name
Test status
Simulation time 288855773 ps
CPU time 0.97 seconds
Started Apr 15 12:54:42 PM PDT 24
Finished Apr 15 12:54:43 PM PDT 24
Peak memory 201992 kb
Host smart-8c510696-5b63-4aec-a67e-acd2058f0e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822651577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1822651577
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3993488757
Short name T224
Test name
Test status
Simulation time 194753652055 ps
CPU time 461.7 seconds
Started Apr 15 12:54:44 PM PDT 24
Finished Apr 15 01:02:26 PM PDT 24
Peak memory 202296 kb
Host smart-fb17c81a-6604-4b25-88af-7806a425bc6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993488757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3993488757
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3429250592
Short name T646
Test name
Test status
Simulation time 162413659851 ps
CPU time 99.87 seconds
Started Apr 15 12:54:42 PM PDT 24
Finished Apr 15 12:56:22 PM PDT 24
Peak memory 202196 kb
Host smart-67ed06e5-66ec-42fb-af91-5d582c8f336e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429250592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3429250592
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3416956370
Short name T685
Test name
Test status
Simulation time 322215004756 ps
CPU time 76.94 seconds
Started Apr 15 12:54:41 PM PDT 24
Finished Apr 15 12:55:58 PM PDT 24
Peak memory 202200 kb
Host smart-edf83219-8652-49d2-8a2b-74b2534576e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416956370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3416956370
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1279900153
Short name T714
Test name
Test status
Simulation time 326775565235 ps
CPU time 181.36 seconds
Started Apr 15 12:54:41 PM PDT 24
Finished Apr 15 12:57:43 PM PDT 24
Peak memory 202236 kb
Host smart-ed1af60a-8bc3-45d5-9654-1a2501f6fd4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279900153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1279900153
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.136906937
Short name T658
Test name
Test status
Simulation time 603709720922 ps
CPU time 790.26 seconds
Started Apr 15 12:54:40 PM PDT 24
Finished Apr 15 01:07:51 PM PDT 24
Peak memory 202096 kb
Host smart-346fce54-672f-47b1-b80b-2986419fc0f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136906937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.136906937
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1566666081
Short name T432
Test name
Test status
Simulation time 91179631447 ps
CPU time 306.19 seconds
Started Apr 15 12:54:43 PM PDT 24
Finished Apr 15 12:59:50 PM PDT 24
Peak memory 202668 kb
Host smart-9dd7c2dc-99fc-43c0-9b2a-0c30a8ccedc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566666081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1566666081
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3077509787
Short name T549
Test name
Test status
Simulation time 43460276636 ps
CPU time 96.26 seconds
Started Apr 15 12:54:44 PM PDT 24
Finished Apr 15 12:56:20 PM PDT 24
Peak memory 202024 kb
Host smart-244f07dc-116a-40a8-9c81-a5a2e8d9b23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077509787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3077509787
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1077836066
Short name T376
Test name
Test status
Simulation time 3500435176 ps
CPU time 2.65 seconds
Started Apr 15 12:54:44 PM PDT 24
Finished Apr 15 12:54:47 PM PDT 24
Peak memory 202048 kb
Host smart-ed69e94a-6e8b-49a6-9bdd-c1d37332220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077836066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1077836066
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.198401057
Short name T481
Test name
Test status
Simulation time 6084923896 ps
CPU time 1.85 seconds
Started Apr 15 12:54:34 PM PDT 24
Finished Apr 15 12:54:36 PM PDT 24
Peak memory 202076 kb
Host smart-f781dd7f-066c-4d2f-949e-a4bd7e0c75d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198401057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.198401057
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3309530140
Short name T457
Test name
Test status
Simulation time 53060118846 ps
CPU time 112.09 seconds
Started Apr 15 12:54:43 PM PDT 24
Finished Apr 15 12:56:36 PM PDT 24
Peak memory 201980 kb
Host smart-26f75ddd-9ce9-4937-adca-42c5c7c6e2f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309530140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3309530140
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3024906142
Short name T486
Test name
Test status
Simulation time 395601283 ps
CPU time 1.23 seconds
Started Apr 15 12:54:56 PM PDT 24
Finished Apr 15 12:54:58 PM PDT 24
Peak memory 201980 kb
Host smart-9ddc5f4d-a2ca-481c-9263-fcbf3eddb45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024906142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3024906142
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.439585593
Short name T142
Test name
Test status
Simulation time 516094798665 ps
CPU time 85.77 seconds
Started Apr 15 12:54:55 PM PDT 24
Finished Apr 15 12:56:21 PM PDT 24
Peak memory 202340 kb
Host smart-6694b2f9-eef1-4cbd-bf69-9972b414eebf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439585593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.439585593
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3529616434
Short name T702
Test name
Test status
Simulation time 180392107265 ps
CPU time 27.99 seconds
Started Apr 15 12:54:56 PM PDT 24
Finished Apr 15 12:55:24 PM PDT 24
Peak memory 202248 kb
Host smart-ff64b05f-7efe-4747-ae5e-a210227307b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529616434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3529616434
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.94332827
Short name T313
Test name
Test status
Simulation time 325837863961 ps
CPU time 746.89 seconds
Started Apr 15 12:54:56 PM PDT 24
Finished Apr 15 01:07:23 PM PDT 24
Peak memory 202344 kb
Host smart-8c5518bd-01e4-441f-8373-f8bb3d39e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94332827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.94332827
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2761081040
Short name T555
Test name
Test status
Simulation time 493311320612 ps
CPU time 1208.16 seconds
Started Apr 15 12:54:54 PM PDT 24
Finished Apr 15 01:15:02 PM PDT 24
Peak memory 202252 kb
Host smart-a3600c45-2df6-4e7e-be74-9b62622433a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761081040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2761081040
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3777995400
Short name T603
Test name
Test status
Simulation time 489947539945 ps
CPU time 1079.06 seconds
Started Apr 15 12:54:48 PM PDT 24
Finished Apr 15 01:12:48 PM PDT 24
Peak memory 202252 kb
Host smart-ed5d5bb8-1aba-45de-b928-1a14b1dd9bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777995400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3777995400
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2982303415
Short name T557
Test name
Test status
Simulation time 326002487087 ps
CPU time 225.91 seconds
Started Apr 15 12:54:48 PM PDT 24
Finished Apr 15 12:58:34 PM PDT 24
Peak memory 202228 kb
Host smart-87447398-d63b-4e34-9115-406e3d5470ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982303415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2982303415
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1741175161
Short name T451
Test name
Test status
Simulation time 195366813639 ps
CPU time 109.16 seconds
Started Apr 15 12:54:54 PM PDT 24
Finished Apr 15 12:56:43 PM PDT 24
Peak memory 202244 kb
Host smart-5c625eb7-f6b7-4966-a611-29246551e555
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741175161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1741175161
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3121618254
Short name T522
Test name
Test status
Simulation time 39037224788 ps
CPU time 17.2 seconds
Started Apr 15 12:54:53 PM PDT 24
Finished Apr 15 12:55:10 PM PDT 24
Peak memory 202060 kb
Host smart-bd03ab24-4477-4ec0-b648-f94507595cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121618254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3121618254
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3315839861
Short name T644
Test name
Test status
Simulation time 5590425428 ps
CPU time 7 seconds
Started Apr 15 12:54:54 PM PDT 24
Finished Apr 15 12:55:01 PM PDT 24
Peak memory 201940 kb
Host smart-d8b9ccbc-b47c-43f7-b599-e254b8aede1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315839861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3315839861
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3451380798
Short name T769
Test name
Test status
Simulation time 5727314611 ps
CPU time 4.24 seconds
Started Apr 15 12:54:49 PM PDT 24
Finished Apr 15 12:54:54 PM PDT 24
Peak memory 202112 kb
Host smart-c30c1945-698c-45fb-abfc-cb17995938d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451380798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3451380798
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2847100417
Short name T466
Test name
Test status
Simulation time 346795507073 ps
CPU time 68.3 seconds
Started Apr 15 12:54:53 PM PDT 24
Finished Apr 15 12:56:02 PM PDT 24
Peak memory 202316 kb
Host smart-5336192f-7db7-4bc7-b607-8ee31708976b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847100417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2847100417
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2567905007
Short name T579
Test name
Test status
Simulation time 41260532019 ps
CPU time 92.8 seconds
Started Apr 15 12:54:55 PM PDT 24
Finished Apr 15 12:56:28 PM PDT 24
Peak memory 202464 kb
Host smart-aa570f3e-873c-4bd9-9afb-2eaeab538732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567905007 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2567905007
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.71720399
Short name T648
Test name
Test status
Simulation time 365268245 ps
CPU time 0.98 seconds
Started Apr 15 12:55:07 PM PDT 24
Finished Apr 15 12:55:08 PM PDT 24
Peak memory 201968 kb
Host smart-99fae305-079b-43dd-b579-bece25937fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71720399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.71720399
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.53933705
Short name T151
Test name
Test status
Simulation time 169099635831 ps
CPU time 377.47 seconds
Started Apr 15 12:54:56 PM PDT 24
Finished Apr 15 01:01:14 PM PDT 24
Peak memory 202344 kb
Host smart-2a189b87-d664-4c7c-865d-32dc8f215f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53933705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.53933705
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2743151751
Short name T497
Test name
Test status
Simulation time 320083555760 ps
CPU time 201.95 seconds
Started Apr 15 12:54:59 PM PDT 24
Finished Apr 15 12:58:21 PM PDT 24
Peak memory 202264 kb
Host smart-d78e3e5b-0c11-40eb-ab2c-d0252bee40db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743151751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2743151751
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1599334924
Short name T166
Test name
Test status
Simulation time 329675330308 ps
CPU time 197.1 seconds
Started Apr 15 12:54:57 PM PDT 24
Finished Apr 15 12:58:15 PM PDT 24
Peak memory 202228 kb
Host smart-5a54b183-a506-4841-9efc-7b4a54c5aded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599334924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1599334924
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2692909718
Short name T479
Test name
Test status
Simulation time 493289359689 ps
CPU time 1194.87 seconds
Started Apr 15 12:54:57 PM PDT 24
Finished Apr 15 01:14:53 PM PDT 24
Peak memory 202312 kb
Host smart-325547d8-34a7-434a-bd14-59931debf64b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692909718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2692909718
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.143720075
Short name T707
Test name
Test status
Simulation time 465975623322 ps
CPU time 477.78 seconds
Started Apr 15 12:54:57 PM PDT 24
Finished Apr 15 01:02:56 PM PDT 24
Peak memory 202360 kb
Host smart-d82ab443-5e83-41aa-844c-548cc9c830ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143720075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.143720075
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3639449956
Short name T630
Test name
Test status
Simulation time 196126011108 ps
CPU time 211.94 seconds
Started Apr 15 12:55:01 PM PDT 24
Finished Apr 15 12:58:34 PM PDT 24
Peak memory 202240 kb
Host smart-1c2dc2ca-bc53-42d3-9f04-765a035467b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639449956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3639449956
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3667075740
Short name T389
Test name
Test status
Simulation time 35552325844 ps
CPU time 82.82 seconds
Started Apr 15 12:55:01 PM PDT 24
Finished Apr 15 12:56:24 PM PDT 24
Peak memory 202088 kb
Host smart-84cb2d06-2963-4c11-afdb-1568d516b6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667075740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3667075740
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.953032698
Short name T688
Test name
Test status
Simulation time 3970724978 ps
CPU time 2.73 seconds
Started Apr 15 12:55:00 PM PDT 24
Finished Apr 15 12:55:03 PM PDT 24
Peak memory 202072 kb
Host smart-5bf343ac-5992-427a-bfb1-20aa7f946782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953032698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.953032698
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2441282359
Short name T394
Test name
Test status
Simulation time 5693802804 ps
CPU time 13.94 seconds
Started Apr 15 12:54:55 PM PDT 24
Finished Apr 15 12:55:10 PM PDT 24
Peak memory 202044 kb
Host smart-564631e3-4465-4883-8fac-6466856e9ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441282359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2441282359
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3537147690
Short name T321
Test name
Test status
Simulation time 182348058447 ps
CPU time 50.69 seconds
Started Apr 15 12:55:06 PM PDT 24
Finished Apr 15 12:55:57 PM PDT 24
Peak memory 202260 kb
Host smart-6eb2ae9b-160d-4109-ba4f-507dc6a2ec18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537147690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3537147690
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1840523225
Short name T27
Test name
Test status
Simulation time 700524613202 ps
CPU time 226.6 seconds
Started Apr 15 12:55:05 PM PDT 24
Finished Apr 15 12:58:52 PM PDT 24
Peak memory 218544 kb
Host smart-a4790246-be88-4a11-b718-8f373e3d6a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840523225 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1840523225
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2533827503
Short name T745
Test name
Test status
Simulation time 491926842 ps
CPU time 1.52 seconds
Started Apr 15 12:55:13 PM PDT 24
Finished Apr 15 12:55:15 PM PDT 24
Peak memory 201972 kb
Host smart-7f07273b-80a5-476a-94c1-a8e60dbbea4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533827503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2533827503
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1400105267
Short name T258
Test name
Test status
Simulation time 488110092101 ps
CPU time 1154.01 seconds
Started Apr 15 12:55:08 PM PDT 24
Finished Apr 15 01:14:23 PM PDT 24
Peak memory 202320 kb
Host smart-089d06ab-e156-4290-8929-fddd0e84e2c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400105267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1400105267
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1539870258
Short name T792
Test name
Test status
Simulation time 500951397831 ps
CPU time 1044.26 seconds
Started Apr 15 12:55:09 PM PDT 24
Finished Apr 15 01:12:34 PM PDT 24
Peak memory 202264 kb
Host smart-8b4626c1-2c02-4dae-920e-5682ed745254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539870258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1539870258
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1252329220
Short name T583
Test name
Test status
Simulation time 158632668675 ps
CPU time 97.55 seconds
Started Apr 15 12:55:06 PM PDT 24
Finished Apr 15 12:56:44 PM PDT 24
Peak memory 202340 kb
Host smart-b1519e1c-cae0-4a85-bc5d-25a9e53163d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252329220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1252329220
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2133873018
Short name T423
Test name
Test status
Simulation time 162247635795 ps
CPU time 199.3 seconds
Started Apr 15 12:55:06 PM PDT 24
Finished Apr 15 12:58:26 PM PDT 24
Peak memory 202248 kb
Host smart-e7dd042a-ca8d-48a2-9c68-f9ca150e4f21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133873018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2133873018
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2153697953
Short name T162
Test name
Test status
Simulation time 331452754885 ps
CPU time 45.25 seconds
Started Apr 15 12:55:06 PM PDT 24
Finished Apr 15 12:55:51 PM PDT 24
Peak memory 202260 kb
Host smart-3b297e2b-de1e-42ff-b0ce-f5d6c360d178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153697953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2153697953
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1166588425
Short name T399
Test name
Test status
Simulation time 328399269697 ps
CPU time 185.38 seconds
Started Apr 15 12:55:05 PM PDT 24
Finished Apr 15 12:58:11 PM PDT 24
Peak memory 202268 kb
Host smart-f325cd7f-6775-4813-ac05-75613731a12a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166588425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1166588425
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3370391664
Short name T246
Test name
Test status
Simulation time 513822896147 ps
CPU time 337.7 seconds
Started Apr 15 12:55:11 PM PDT 24
Finished Apr 15 01:00:50 PM PDT 24
Peak memory 202280 kb
Host smart-195a6f8f-6dbf-4b74-a5e9-9f8575877393
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370391664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3370391664
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3238179453
Short name T403
Test name
Test status
Simulation time 200067983709 ps
CPU time 80.92 seconds
Started Apr 15 12:55:10 PM PDT 24
Finished Apr 15 12:56:31 PM PDT 24
Peak memory 202240 kb
Host smart-9fc6748c-70f8-4042-b5af-46089c430025
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238179453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3238179453
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.36737225
Short name T88
Test name
Test status
Simulation time 72724591989 ps
CPU time 364.43 seconds
Started Apr 15 12:55:13 PM PDT 24
Finished Apr 15 01:01:17 PM PDT 24
Peak memory 202508 kb
Host smart-931b794d-8618-4271-bda6-b523fcc8754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36737225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.36737225
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3213309039
Short name T487
Test name
Test status
Simulation time 26078078942 ps
CPU time 30.08 seconds
Started Apr 15 12:55:08 PM PDT 24
Finished Apr 15 12:55:39 PM PDT 24
Peak memory 202012 kb
Host smart-f4604def-d575-4801-8277-8bb256272e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213309039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3213309039
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.825605569
Short name T683
Test name
Test status
Simulation time 3219920286 ps
CPU time 4.11 seconds
Started Apr 15 12:55:10 PM PDT 24
Finished Apr 15 12:55:14 PM PDT 24
Peak memory 202040 kb
Host smart-0dbe1794-ce77-47ba-86e9-22dd19519d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825605569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.825605569
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2060759454
Short name T392
Test name
Test status
Simulation time 5821243874 ps
CPU time 13.71 seconds
Started Apr 15 12:55:06 PM PDT 24
Finished Apr 15 12:55:20 PM PDT 24
Peak memory 202076 kb
Host smart-c5ee7520-dde9-4137-9fbe-5922822726fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060759454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2060759454
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3859697257
Short name T282
Test name
Test status
Simulation time 337254534510 ps
CPU time 792.61 seconds
Started Apr 15 12:55:15 PM PDT 24
Finished Apr 15 01:08:28 PM PDT 24
Peak memory 202212 kb
Host smart-4d2bdefe-bbbd-4f9a-af12-c059670e2bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859697257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3859697257
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3356401001
Short name T650
Test name
Test status
Simulation time 37297045660 ps
CPU time 44.65 seconds
Started Apr 15 12:55:09 PM PDT 24
Finished Apr 15 12:55:54 PM PDT 24
Peak memory 210596 kb
Host smart-aba731bc-a99c-41a4-ac63-4fbb306867ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356401001 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3356401001
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.4171911496
Short name T387
Test name
Test status
Simulation time 422562860 ps
CPU time 0.89 seconds
Started Apr 15 12:55:25 PM PDT 24
Finished Apr 15 12:55:26 PM PDT 24
Peak memory 201916 kb
Host smart-3d5b64bd-d4e1-4a68-b20d-b8dd85b875c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171911496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4171911496
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2806758104
Short name T128
Test name
Test status
Simulation time 173163196411 ps
CPU time 85 seconds
Started Apr 15 12:55:17 PM PDT 24
Finished Apr 15 12:56:43 PM PDT 24
Peak memory 202448 kb
Host smart-e4b55d0e-26b9-4f2d-967c-49d12496a7d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806758104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2806758104
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1814541261
Short name T673
Test name
Test status
Simulation time 166167785503 ps
CPU time 271.32 seconds
Started Apr 15 12:55:20 PM PDT 24
Finished Apr 15 12:59:52 PM PDT 24
Peak memory 202288 kb
Host smart-5eb40a5f-c48c-4b75-8163-de4a586d8f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814541261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1814541261
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2193906785
Short name T89
Test name
Test status
Simulation time 166741244199 ps
CPU time 101.6 seconds
Started Apr 15 12:55:14 PM PDT 24
Finished Apr 15 12:56:56 PM PDT 24
Peak memory 202256 kb
Host smart-24d7232d-0666-4e30-be02-1f92d0b880c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193906785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2193906785
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3455262088
Short name T386
Test name
Test status
Simulation time 488572130670 ps
CPU time 76.46 seconds
Started Apr 15 12:55:18 PM PDT 24
Finished Apr 15 12:56:35 PM PDT 24
Peak memory 202240 kb
Host smart-266762a0-8a65-4335-9e15-03ac958cf983
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455262088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3455262088
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.4083925907
Short name T26
Test name
Test status
Simulation time 163031430287 ps
CPU time 382.85 seconds
Started Apr 15 12:55:14 PM PDT 24
Finished Apr 15 01:01:37 PM PDT 24
Peak memory 202356 kb
Host smart-b4eac2e0-4c23-4134-a331-c04d05a9f077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083925907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.4083925907
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1335160311
Short name T415
Test name
Test status
Simulation time 165537067564 ps
CPU time 388.44 seconds
Started Apr 15 12:55:14 PM PDT 24
Finished Apr 15 01:01:43 PM PDT 24
Peak memory 202240 kb
Host smart-5a082045-3d50-4052-ae67-226146b11a29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335160311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1335160311
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2343267451
Short name T289
Test name
Test status
Simulation time 569754821158 ps
CPU time 1374.6 seconds
Started Apr 15 12:55:18 PM PDT 24
Finished Apr 15 01:18:13 PM PDT 24
Peak memory 202352 kb
Host smart-cb6ef33f-6b42-4e2a-b324-7d035262bf6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343267451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2343267451
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1696032345
Short name T615
Test name
Test status
Simulation time 396096207202 ps
CPU time 496.67 seconds
Started Apr 15 12:55:19 PM PDT 24
Finished Apr 15 01:03:36 PM PDT 24
Peak memory 202152 kb
Host smart-d74a7655-ef17-4dc4-8e83-2c3b0f0048f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696032345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1696032345
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.653997693
Short name T734
Test name
Test status
Simulation time 85738358822 ps
CPU time 378.63 seconds
Started Apr 15 12:55:24 PM PDT 24
Finished Apr 15 01:01:43 PM PDT 24
Peak memory 202616 kb
Host smart-453ac4d8-f866-4b96-aed8-67700f76f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653997693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.653997693
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.596684213
Short name T458
Test name
Test status
Simulation time 40505376737 ps
CPU time 89.97 seconds
Started Apr 15 12:55:24 PM PDT 24
Finished Apr 15 12:56:54 PM PDT 24
Peak memory 202060 kb
Host smart-91731270-8d35-4ddb-9ac8-a1cfc3c7f335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596684213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.596684213
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1605898387
Short name T519
Test name
Test status
Simulation time 3293057246 ps
CPU time 4.44 seconds
Started Apr 15 12:55:24 PM PDT 24
Finished Apr 15 12:55:29 PM PDT 24
Peak memory 202016 kb
Host smart-cce64edb-8947-41d4-92d9-a22969a825a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605898387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1605898387
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3660804273
Short name T73
Test name
Test status
Simulation time 5818906044 ps
CPU time 7.72 seconds
Started Apr 15 12:55:17 PM PDT 24
Finished Apr 15 12:55:25 PM PDT 24
Peak memory 202020 kb
Host smart-db833202-d907-459f-8293-518295d01198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660804273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3660804273
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3248630061
Short name T209
Test name
Test status
Simulation time 197521219188 ps
CPU time 281.08 seconds
Started Apr 15 12:55:23 PM PDT 24
Finished Apr 15 01:00:05 PM PDT 24
Peak memory 202188 kb
Host smart-718d1e8a-4d3e-4122-8457-9931c1f306a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248630061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3248630061
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.499779147
Short name T475
Test name
Test status
Simulation time 480673867 ps
CPU time 1.17 seconds
Started Apr 15 12:50:57 PM PDT 24
Finished Apr 15 12:50:59 PM PDT 24
Peak memory 201832 kb
Host smart-c01ec5fb-23c1-4c7e-aa6e-97594ef4bed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499779147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.499779147
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2165541174
Short name T577
Test name
Test status
Simulation time 537505707000 ps
CPU time 451.3 seconds
Started Apr 15 12:50:50 PM PDT 24
Finished Apr 15 12:58:22 PM PDT 24
Peak memory 202220 kb
Host smart-20a1dce7-7a98-4c4d-b75e-67e4b74a91ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165541174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2165541174
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3279307523
Short name T757
Test name
Test status
Simulation time 166621974747 ps
CPU time 44.16 seconds
Started Apr 15 12:50:53 PM PDT 24
Finished Apr 15 12:51:38 PM PDT 24
Peak memory 202300 kb
Host smart-0a4d8a80-d795-4e7c-b22b-9d40848fed1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279307523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3279307523
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3414115782
Short name T489
Test name
Test status
Simulation time 163288775690 ps
CPU time 340.54 seconds
Started Apr 15 12:50:54 PM PDT 24
Finished Apr 15 12:56:35 PM PDT 24
Peak memory 202064 kb
Host smart-310e98c7-13c4-4707-8214-b4a01e090805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414115782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3414115782
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1085433230
Short name T67
Test name
Test status
Simulation time 331998099679 ps
CPU time 189.53 seconds
Started Apr 15 12:50:49 PM PDT 24
Finished Apr 15 12:53:59 PM PDT 24
Peak memory 202176 kb
Host smart-f65a933a-b160-481c-95f2-598286b65ec7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085433230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1085433230
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3296333813
Short name T10
Test name
Test status
Simulation time 328154147434 ps
CPU time 196.29 seconds
Started Apr 15 12:50:48 PM PDT 24
Finished Apr 15 12:54:04 PM PDT 24
Peak memory 202272 kb
Host smart-2b33b2b1-1b4c-40eb-91c2-887de003f63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296333813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3296333813
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1407301237
Short name T422
Test name
Test status
Simulation time 484496857000 ps
CPU time 1023.11 seconds
Started Apr 15 12:50:54 PM PDT 24
Finished Apr 15 01:07:57 PM PDT 24
Peak memory 202284 kb
Host smart-dab7a801-54a8-4d20-8ad3-92b8491863df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407301237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1407301237
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3015103344
Short name T283
Test name
Test status
Simulation time 181553811425 ps
CPU time 403.37 seconds
Started Apr 15 12:50:51 PM PDT 24
Finished Apr 15 12:57:34 PM PDT 24
Peak memory 202284 kb
Host smart-baa9971f-5191-41df-948d-65a387e18d8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015103344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3015103344
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2342626051
Short name T21
Test name
Test status
Simulation time 616501440883 ps
CPU time 348.83 seconds
Started Apr 15 12:51:04 PM PDT 24
Finished Apr 15 12:56:53 PM PDT 24
Peak memory 202300 kb
Host smart-ddbc17b7-c90c-489f-988f-56dc80e77026
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342626051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2342626051
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2832655724
Short name T215
Test name
Test status
Simulation time 128006347071 ps
CPU time 706.96 seconds
Started Apr 15 12:50:52 PM PDT 24
Finished Apr 15 01:02:40 PM PDT 24
Peak memory 202632 kb
Host smart-ee5172a2-6fac-4a1f-8b28-c6fc1285ffb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832655724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2832655724
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1005594445
Short name T424
Test name
Test status
Simulation time 36020951047 ps
CPU time 20.34 seconds
Started Apr 15 12:50:54 PM PDT 24
Finished Apr 15 12:51:15 PM PDT 24
Peak memory 201964 kb
Host smart-1dd9d682-aa6a-4c84-855a-e4816ba8380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005594445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1005594445
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2731517613
Short name T117
Test name
Test status
Simulation time 3795881187 ps
CPU time 3.88 seconds
Started Apr 15 12:50:51 PM PDT 24
Finished Apr 15 12:50:55 PM PDT 24
Peak memory 202016 kb
Host smart-106f9058-83ee-48ba-8c0c-b85ae0587802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731517613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2731517613
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3303607778
Short name T64
Test name
Test status
Simulation time 8273054372 ps
CPU time 18.3 seconds
Started Apr 15 12:50:57 PM PDT 24
Finished Apr 15 12:51:16 PM PDT 24
Peak memory 218932 kb
Host smart-387b3659-6162-418c-a011-4b434d79b500
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303607778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3303607778
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1140493896
Short name T388
Test name
Test status
Simulation time 6071263596 ps
CPU time 2.77 seconds
Started Apr 15 12:50:49 PM PDT 24
Finished Apr 15 12:50:52 PM PDT 24
Peak memory 202064 kb
Host smart-5e7a80cc-1dc2-4e9e-8038-0971e2cc97b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140493896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1140493896
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1725342136
Short name T226
Test name
Test status
Simulation time 326716956390 ps
CPU time 746.74 seconds
Started Apr 15 12:50:58 PM PDT 24
Finished Apr 15 01:03:26 PM PDT 24
Peak memory 202268 kb
Host smart-a0ba1a20-85c1-47b4-9c72-267fff7b9007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725342136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1725342136
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1218428883
Short name T659
Test name
Test status
Simulation time 469819744 ps
CPU time 1.16 seconds
Started Apr 15 12:55:35 PM PDT 24
Finished Apr 15 12:55:36 PM PDT 24
Peak memory 202016 kb
Host smart-351b791b-af3c-44ef-a138-d0922fb961de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218428883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1218428883
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.4236282885
Short name T266
Test name
Test status
Simulation time 340055865318 ps
CPU time 81.85 seconds
Started Apr 15 12:55:27 PM PDT 24
Finished Apr 15 12:56:49 PM PDT 24
Peak memory 202268 kb
Host smart-5a46a14f-1c29-4b4c-a3dd-56f7a5562fc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236282885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.4236282885
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1145815379
Short name T309
Test name
Test status
Simulation time 414751408205 ps
CPU time 283.34 seconds
Started Apr 15 12:55:31 PM PDT 24
Finished Apr 15 01:00:14 PM PDT 24
Peak memory 202304 kb
Host smart-9f551724-031b-4819-a110-6ea5a5e5651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145815379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1145815379
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3015788348
Short name T753
Test name
Test status
Simulation time 161078135727 ps
CPU time 392.44 seconds
Started Apr 15 12:55:29 PM PDT 24
Finished Apr 15 01:02:01 PM PDT 24
Peak memory 202240 kb
Host smart-7b4b0b8a-5cc6-4bfd-9cc8-a0a007c16517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015788348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3015788348
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2125425308
Short name T9
Test name
Test status
Simulation time 164332609951 ps
CPU time 380.86 seconds
Started Apr 15 12:55:25 PM PDT 24
Finished Apr 15 01:01:46 PM PDT 24
Peak memory 202224 kb
Host smart-f9287d05-6357-41ad-94f9-d757e2d8388f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125425308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2125425308
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3695689842
Short name T150
Test name
Test status
Simulation time 334627053210 ps
CPU time 189.06 seconds
Started Apr 15 12:55:27 PM PDT 24
Finished Apr 15 12:58:37 PM PDT 24
Peak memory 202252 kb
Host smart-ebc904e3-2b43-4856-9da1-90437aa0aa7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695689842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3695689842
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3009790747
Short name T87
Test name
Test status
Simulation time 181702932190 ps
CPU time 107.5 seconds
Started Apr 15 12:55:25 PM PDT 24
Finished Apr 15 12:57:13 PM PDT 24
Peak memory 202256 kb
Host smart-7fd451f3-ccb6-4e6c-a43d-dcf4e9bd0460
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009790747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3009790747
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2279535987
Short name T575
Test name
Test status
Simulation time 605201552541 ps
CPU time 1404.96 seconds
Started Apr 15 12:55:26 PM PDT 24
Finished Apr 15 01:18:52 PM PDT 24
Peak memory 202248 kb
Host smart-55020f90-adb0-46da-b1f5-ec05a7b4a6ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279535987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2279535987
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3658522040
Short name T41
Test name
Test status
Simulation time 133031458811 ps
CPU time 695.89 seconds
Started Apr 15 12:55:40 PM PDT 24
Finished Apr 15 01:07:17 PM PDT 24
Peak memory 202604 kb
Host smart-32fd1888-62cc-4ffd-b283-e8d59f46664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658522040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3658522040
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4162833097
Short name T448
Test name
Test status
Simulation time 36508671768 ps
CPU time 42.08 seconds
Started Apr 15 12:55:31 PM PDT 24
Finished Apr 15 12:56:14 PM PDT 24
Peak memory 202072 kb
Host smart-a255fe02-e46a-46e0-9e52-e1f1d998cea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162833097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4162833097
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2388505658
Short name T80
Test name
Test status
Simulation time 3915776520 ps
CPU time 2.04 seconds
Started Apr 15 12:55:30 PM PDT 24
Finished Apr 15 12:55:32 PM PDT 24
Peak memory 202088 kb
Host smart-0fc23a15-e358-4a9e-96b5-8659f3b05f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388505658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2388505658
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3548340834
Short name T114
Test name
Test status
Simulation time 5828170452 ps
CPU time 8.28 seconds
Started Apr 15 12:55:28 PM PDT 24
Finished Apr 15 12:55:37 PM PDT 24
Peak memory 202092 kb
Host smart-58fcbba7-e57e-48dc-8378-f9ee8851d156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548340834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3548340834
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3924274995
Short name T498
Test name
Test status
Simulation time 303905219004 ps
CPU time 339.89 seconds
Started Apr 15 12:55:35 PM PDT 24
Finished Apr 15 01:01:15 PM PDT 24
Peak memory 210780 kb
Host smart-a3597a53-4ba5-47ff-95c7-659b3bf95025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924274995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3924274995
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.897406870
Short name T638
Test name
Test status
Simulation time 65417977760 ps
CPU time 63.42 seconds
Started Apr 15 12:55:36 PM PDT 24
Finished Apr 15 12:56:40 PM PDT 24
Peak memory 202324 kb
Host smart-27541f75-bac5-430f-aa24-fd4258420232
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897406870 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.897406870
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3104262642
Short name T726
Test name
Test status
Simulation time 410931449 ps
CPU time 1.6 seconds
Started Apr 15 12:55:46 PM PDT 24
Finished Apr 15 12:55:49 PM PDT 24
Peak memory 201984 kb
Host smart-df2f388a-ba05-41cb-bc94-230895868d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104262642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3104262642
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1588529052
Short name T165
Test name
Test status
Simulation time 330118909421 ps
CPU time 111 seconds
Started Apr 15 12:55:43 PM PDT 24
Finished Apr 15 12:57:35 PM PDT 24
Peak memory 202316 kb
Host smart-4259f64a-7747-47eb-8156-6623a1e4dbf4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588529052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1588529052
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.445175908
Short name T758
Test name
Test status
Simulation time 373400909131 ps
CPU time 835.44 seconds
Started Apr 15 12:55:39 PM PDT 24
Finished Apr 15 01:09:35 PM PDT 24
Peak memory 202288 kb
Host smart-2970bb90-9b23-45bd-ade1-402993b7a546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445175908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.445175908
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1328230421
Short name T698
Test name
Test status
Simulation time 163244233990 ps
CPU time 349.62 seconds
Started Apr 15 12:55:38 PM PDT 24
Finished Apr 15 01:01:28 PM PDT 24
Peak memory 202272 kb
Host smart-7671cbe8-ce95-4150-9af7-82063bb18948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328230421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1328230421
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1085163883
Short name T206
Test name
Test status
Simulation time 167551389165 ps
CPU time 234.09 seconds
Started Apr 15 12:55:36 PM PDT 24
Finished Apr 15 12:59:31 PM PDT 24
Peak memory 202300 kb
Host smart-f249309e-bf07-48fc-8342-b639e28e1342
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085163883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1085163883
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.4105640254
Short name T249
Test name
Test status
Simulation time 329810851351 ps
CPU time 703.36 seconds
Started Apr 15 12:55:38 PM PDT 24
Finished Apr 15 01:07:22 PM PDT 24
Peak memory 202448 kb
Host smart-7f909db8-d463-4de3-8d2b-bf79fdb183f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105640254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.4105640254
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1901183273
Short name T550
Test name
Test status
Simulation time 488833346666 ps
CPU time 105.49 seconds
Started Apr 15 12:55:36 PM PDT 24
Finished Apr 15 12:57:22 PM PDT 24
Peak memory 202228 kb
Host smart-2e722044-d87e-4513-9a81-0eeb02c57470
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901183273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1901183273
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2183474965
Short name T202
Test name
Test status
Simulation time 519199406245 ps
CPU time 121.72 seconds
Started Apr 15 12:55:35 PM PDT 24
Finished Apr 15 12:57:37 PM PDT 24
Peak memory 202268 kb
Host smart-cc7db122-2e1c-4f94-b1ad-63527a1274ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183474965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2183474965
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3653197005
Short name T245
Test name
Test status
Simulation time 200729935977 ps
CPU time 433.43 seconds
Started Apr 15 12:55:36 PM PDT 24
Finished Apr 15 01:02:50 PM PDT 24
Peak memory 202112 kb
Host smart-b1dcc714-ae6f-442a-a736-2270f49d453c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653197005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3653197005
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3440794596
Short name T358
Test name
Test status
Simulation time 92583823862 ps
CPU time 285.36 seconds
Started Apr 15 12:55:47 PM PDT 24
Finished Apr 15 01:00:33 PM PDT 24
Peak memory 202580 kb
Host smart-4bdae8db-c3fd-490d-a00d-2ee20dc0cad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440794596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3440794596
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3668298849
Short name T524
Test name
Test status
Simulation time 22054954266 ps
CPU time 12.24 seconds
Started Apr 15 12:55:46 PM PDT 24
Finished Apr 15 12:55:59 PM PDT 24
Peak memory 202084 kb
Host smart-cbef009b-662d-404c-93bd-99b30900399e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668298849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3668298849
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1891097527
Short name T606
Test name
Test status
Simulation time 4382070639 ps
CPU time 11.91 seconds
Started Apr 15 12:55:41 PM PDT 24
Finished Apr 15 12:55:54 PM PDT 24
Peak memory 202012 kb
Host smart-defefcc2-1b57-41a6-9d07-2ef384f97339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891097527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1891097527
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2308087797
Short name T365
Test name
Test status
Simulation time 6150251913 ps
CPU time 2.62 seconds
Started Apr 15 12:55:36 PM PDT 24
Finished Apr 15 12:55:39 PM PDT 24
Peak memory 202100 kb
Host smart-f79165cf-2ce2-4f70-9859-6e7a19bf1fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308087797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2308087797
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2769920831
Short name T147
Test name
Test status
Simulation time 482096153034 ps
CPU time 866.29 seconds
Started Apr 15 12:55:41 PM PDT 24
Finished Apr 15 01:10:08 PM PDT 24
Peak memory 202528 kb
Host smart-141fd631-33d3-4475-b880-808d448da1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769920831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2769920831
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.961790591
Short name T12
Test name
Test status
Simulation time 96474065285 ps
CPU time 304.9 seconds
Started Apr 15 12:55:40 PM PDT 24
Finished Apr 15 01:00:45 PM PDT 24
Peak memory 218248 kb
Host smart-ba4e7733-4406-40e6-91e4-db86eab60732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961790591 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.961790591
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.693258050
Short name T61
Test name
Test status
Simulation time 512983612 ps
CPU time 1.16 seconds
Started Apr 15 12:55:48 PM PDT 24
Finished Apr 15 12:55:50 PM PDT 24
Peak memory 201916 kb
Host smart-57c6939f-3c15-44dd-ac68-12feb4e20781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693258050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.693258050
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.984937898
Short name T693
Test name
Test status
Simulation time 167859256580 ps
CPU time 100.91 seconds
Started Apr 15 12:55:51 PM PDT 24
Finished Apr 15 12:57:32 PM PDT 24
Peak memory 202244 kb
Host smart-0d8ee3af-2a6e-49de-a517-5a3089046460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984937898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.984937898
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4048747779
Short name T427
Test name
Test status
Simulation time 328730168741 ps
CPU time 390.59 seconds
Started Apr 15 12:55:51 PM PDT 24
Finished Apr 15 01:02:22 PM PDT 24
Peak memory 202224 kb
Host smart-46ae08be-82ae-40d0-881f-3793c6716153
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048747779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4048747779
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.851399599
Short name T347
Test name
Test status
Simulation time 488911027845 ps
CPU time 1160.5 seconds
Started Apr 15 12:55:49 PM PDT 24
Finished Apr 15 01:15:10 PM PDT 24
Peak memory 202348 kb
Host smart-0d0b3b6b-0d9f-4f13-9931-0d5c16c65e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851399599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.851399599
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.130203015
Short name T744
Test name
Test status
Simulation time 166715988295 ps
CPU time 402.71 seconds
Started Apr 15 12:55:47 PM PDT 24
Finished Apr 15 01:02:30 PM PDT 24
Peak memory 202248 kb
Host smart-d897239c-50c6-4309-b99d-04f0e0a4ff97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=130203015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.130203015
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2222535699
Short name T518
Test name
Test status
Simulation time 174239365582 ps
CPU time 116 seconds
Started Apr 15 12:55:43 PM PDT 24
Finished Apr 15 12:57:40 PM PDT 24
Peak memory 202204 kb
Host smart-d27afb15-209a-4848-b78e-34b98c802e13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222535699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2222535699
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2609101121
Short name T141
Test name
Test status
Simulation time 397747296812 ps
CPU time 213.45 seconds
Started Apr 15 12:55:44 PM PDT 24
Finished Apr 15 12:59:17 PM PDT 24
Peak memory 202232 kb
Host smart-3594292c-b78f-41ff-bb91-96c35e310b47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609101121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2609101121
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2439502076
Short name T426
Test name
Test status
Simulation time 104665882978 ps
CPU time 576.7 seconds
Started Apr 15 12:55:47 PM PDT 24
Finished Apr 15 01:05:24 PM PDT 24
Peak memory 202580 kb
Host smart-be191300-9dc4-4ff3-87b7-500031a7e30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439502076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2439502076
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3395116633
Short name T706
Test name
Test status
Simulation time 39256900355 ps
CPU time 87.84 seconds
Started Apr 15 12:55:48 PM PDT 24
Finished Apr 15 12:57:16 PM PDT 24
Peak memory 202096 kb
Host smart-f01aab5d-64db-4d9c-b696-d300269363fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395116633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3395116633
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3562400853
Short name T362
Test name
Test status
Simulation time 3177911921 ps
CPU time 7.69 seconds
Started Apr 15 12:55:47 PM PDT 24
Finished Apr 15 12:55:56 PM PDT 24
Peak memory 202104 kb
Host smart-8bc226e0-b87c-4254-9720-ea0125fa53de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562400853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3562400853
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.220820592
Short name T731
Test name
Test status
Simulation time 5957130986 ps
CPU time 4.98 seconds
Started Apr 15 12:55:50 PM PDT 24
Finished Apr 15 12:55:56 PM PDT 24
Peak memory 202072 kb
Host smart-8da07153-5ff6-4fa5-bde4-7a2b3a319f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220820592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.220820592
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.41877464
Short name T746
Test name
Test status
Simulation time 172388030350 ps
CPU time 316.02 seconds
Started Apr 15 12:55:51 PM PDT 24
Finished Apr 15 01:01:08 PM PDT 24
Peak memory 202240 kb
Host smart-9c2f804c-6aaa-4ce2-8643-944c70156fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41877464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.41877464
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2882214075
Short name T533
Test name
Test status
Simulation time 118725218482 ps
CPU time 42.21 seconds
Started Apr 15 12:55:48 PM PDT 24
Finished Apr 15 12:56:31 PM PDT 24
Peak memory 210912 kb
Host smart-b8846fe3-e7e6-4f9b-82de-6c6f5a61ddbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882214075 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2882214075
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3108782369
Short name T537
Test name
Test status
Simulation time 542352574 ps
CPU time 0.86 seconds
Started Apr 15 12:55:58 PM PDT 24
Finished Apr 15 12:56:00 PM PDT 24
Peak memory 201980 kb
Host smart-c8a62ec3-8339-4f13-9625-1b094b5ad18e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108782369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3108782369
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.314030714
Short name T292
Test name
Test status
Simulation time 167113447796 ps
CPU time 4.66 seconds
Started Apr 15 12:55:57 PM PDT 24
Finished Apr 15 12:56:03 PM PDT 24
Peak memory 202072 kb
Host smart-bffd01fa-b9fe-4176-bcea-ada2ecababd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314030714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.314030714
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3801820953
Short name T238
Test name
Test status
Simulation time 162319002292 ps
CPU time 402.28 seconds
Started Apr 15 12:55:55 PM PDT 24
Finished Apr 15 01:02:38 PM PDT 24
Peak memory 202160 kb
Host smart-01eac1b1-c56e-4c72-b33c-9709e366be3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801820953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3801820953
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1303504708
Short name T500
Test name
Test status
Simulation time 486362997889 ps
CPU time 1168.43 seconds
Started Apr 15 12:55:53 PM PDT 24
Finished Apr 15 01:15:22 PM PDT 24
Peak memory 202216 kb
Host smart-dd6ad25c-f1e3-4650-974d-f77eaf08c2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303504708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1303504708
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3877275279
Short name T782
Test name
Test status
Simulation time 490030427095 ps
CPU time 557.42 seconds
Started Apr 15 12:55:52 PM PDT 24
Finished Apr 15 01:05:10 PM PDT 24
Peak memory 202288 kb
Host smart-3783c233-bd29-47ff-9f5e-501691225588
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877275279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3877275279
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.633411682
Short name T148
Test name
Test status
Simulation time 491881937429 ps
CPU time 159.5 seconds
Started Apr 15 12:55:47 PM PDT 24
Finished Apr 15 12:58:27 PM PDT 24
Peak memory 202232 kb
Host smart-1c8f4fb1-bea4-4efc-a54b-f732215e1823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633411682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.633411682
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2807250362
Short name T725
Test name
Test status
Simulation time 490040081295 ps
CPU time 1081.14 seconds
Started Apr 15 12:55:52 PM PDT 24
Finished Apr 15 01:13:54 PM PDT 24
Peak memory 202208 kb
Host smart-8317bacd-11f8-491f-9d77-a4bca8ebca2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807250362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2807250362
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.983985944
Short name T269
Test name
Test status
Simulation time 184791819270 ps
CPU time 37.41 seconds
Started Apr 15 12:55:52 PM PDT 24
Finished Apr 15 12:56:30 PM PDT 24
Peak memory 202376 kb
Host smart-57bafcb1-b2af-4236-adcc-7e0c232517ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983985944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.983985944
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1986801955
Short name T179
Test name
Test status
Simulation time 609813600925 ps
CPU time 328.76 seconds
Started Apr 15 12:55:58 PM PDT 24
Finished Apr 15 01:01:27 PM PDT 24
Peak memory 202268 kb
Host smart-bfc51021-cd81-4daf-90bf-c217d4985a90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986801955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1986801955
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3625942807
Short name T593
Test name
Test status
Simulation time 84809217779 ps
CPU time 330.35 seconds
Started Apr 15 12:55:58 PM PDT 24
Finished Apr 15 01:01:29 PM PDT 24
Peak memory 202584 kb
Host smart-271ee57b-b116-41da-9072-046a03fc0c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625942807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3625942807
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2621920222
Short name T391
Test name
Test status
Simulation time 31891414862 ps
CPU time 20.03 seconds
Started Apr 15 12:55:56 PM PDT 24
Finished Apr 15 12:56:17 PM PDT 24
Peak memory 202272 kb
Host smart-3e98d22b-8f5f-4f8a-91ed-f36be8aa17b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621920222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2621920222
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3275561657
Short name T442
Test name
Test status
Simulation time 5586250905 ps
CPU time 3.8 seconds
Started Apr 15 12:55:56 PM PDT 24
Finished Apr 15 12:56:00 PM PDT 24
Peak memory 202064 kb
Host smart-bd455604-8c86-4d31-a8de-a014fd140ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275561657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3275561657
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.4188796307
Short name T611
Test name
Test status
Simulation time 6138225830 ps
CPU time 14.5 seconds
Started Apr 15 12:55:51 PM PDT 24
Finished Apr 15 12:56:06 PM PDT 24
Peak memory 202080 kb
Host smart-b087ca05-9ed1-4f3a-a486-89130492f75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188796307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.4188796307
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3063626952
Short name T798
Test name
Test status
Simulation time 577382247271 ps
CPU time 599.17 seconds
Started Apr 15 12:55:57 PM PDT 24
Finished Apr 15 01:05:56 PM PDT 24
Peak memory 210844 kb
Host smart-4d3bc798-292f-4dbb-ae60-424d4c710e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063626952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3063626952
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2025650725
Short name T30
Test name
Test status
Simulation time 20851755578 ps
CPU time 28.82 seconds
Started Apr 15 12:55:56 PM PDT 24
Finished Apr 15 12:56:25 PM PDT 24
Peak memory 219016 kb
Host smart-125c617b-b687-43f5-b641-e08dcc2c36a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025650725 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2025650725
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2067702432
Short name T762
Test name
Test status
Simulation time 422805073 ps
CPU time 1.6 seconds
Started Apr 15 12:56:11 PM PDT 24
Finished Apr 15 12:56:13 PM PDT 24
Peak memory 202012 kb
Host smart-e1ac27d9-2848-4d88-8322-e73f9715229e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067702432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2067702432
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3724784234
Short name T526
Test name
Test status
Simulation time 494514259051 ps
CPU time 243.62 seconds
Started Apr 15 12:56:05 PM PDT 24
Finished Apr 15 01:00:09 PM PDT 24
Peak memory 202272 kb
Host smart-7a10b4bb-b590-4018-a8d1-1db3073a9237
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724784234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3724784234
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3700070669
Short name T240
Test name
Test status
Simulation time 181380523248 ps
CPU time 114.2 seconds
Started Apr 15 12:56:04 PM PDT 24
Finished Apr 15 12:57:59 PM PDT 24
Peak memory 202264 kb
Host smart-64f99859-4f1d-4772-bbd9-de0ee880ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700070669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3700070669
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1170056413
Short name T545
Test name
Test status
Simulation time 326174433405 ps
CPU time 248.34 seconds
Started Apr 15 12:56:02 PM PDT 24
Finished Apr 15 01:00:10 PM PDT 24
Peak memory 202312 kb
Host smart-e0139441-0d8e-4fc9-a811-95f46b880b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170056413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1170056413
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3918808263
Short name T660
Test name
Test status
Simulation time 166364729273 ps
CPU time 93.85 seconds
Started Apr 15 12:56:01 PM PDT 24
Finished Apr 15 12:57:35 PM PDT 24
Peak memory 202244 kb
Host smart-e8885692-cb72-4d9f-ad42-c1904df79c60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918808263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3918808263
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.554861314
Short name T437
Test name
Test status
Simulation time 507160860088 ps
CPU time 633.9 seconds
Started Apr 15 12:56:00 PM PDT 24
Finished Apr 15 01:06:34 PM PDT 24
Peak memory 202528 kb
Host smart-44f09c69-4016-4aea-a8c8-2144fd8c589e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554861314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.554861314
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2359670711
Short name T559
Test name
Test status
Simulation time 159816254594 ps
CPU time 355.89 seconds
Started Apr 15 12:56:01 PM PDT 24
Finished Apr 15 01:01:57 PM PDT 24
Peak memory 202220 kb
Host smart-76cfe4ca-f7d4-4b12-a47b-6d8b233909b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359670711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2359670711
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.4202354731
Short name T189
Test name
Test status
Simulation time 349395735613 ps
CPU time 107.86 seconds
Started Apr 15 12:56:07 PM PDT 24
Finished Apr 15 12:57:55 PM PDT 24
Peak memory 202316 kb
Host smart-669c2c31-140e-4482-a85e-516e593d7ca6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202354731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.4202354731
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3070899422
Short name T461
Test name
Test status
Simulation time 586379048468 ps
CPU time 111.66 seconds
Started Apr 15 12:56:03 PM PDT 24
Finished Apr 15 12:57:55 PM PDT 24
Peak memory 202208 kb
Host smart-4b0e0205-1dd9-43aa-85fe-d4357e6f5b35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070899422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3070899422
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3279525351
Short name T212
Test name
Test status
Simulation time 87740275122 ps
CPU time 279.05 seconds
Started Apr 15 12:56:04 PM PDT 24
Finished Apr 15 01:00:44 PM PDT 24
Peak memory 202508 kb
Host smart-29a828ee-799b-4326-9450-f3f582865799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279525351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3279525351
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.4128530791
Short name T585
Test name
Test status
Simulation time 31744109977 ps
CPU time 72.15 seconds
Started Apr 15 12:56:06 PM PDT 24
Finished Apr 15 12:57:19 PM PDT 24
Peak memory 202096 kb
Host smart-537269df-37fe-4fc7-838a-e806344dc2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128530791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4128530791
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1636342551
Short name T723
Test name
Test status
Simulation time 4197102648 ps
CPU time 2.55 seconds
Started Apr 15 12:56:03 PM PDT 24
Finished Apr 15 12:56:06 PM PDT 24
Peak memory 202092 kb
Host smart-aba58b49-5340-44c7-9651-c792cc1b0017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636342551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1636342551
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.313939944
Short name T495
Test name
Test status
Simulation time 5526434069 ps
CPU time 13.99 seconds
Started Apr 15 12:56:05 PM PDT 24
Finished Apr 15 12:56:19 PM PDT 24
Peak memory 202088 kb
Host smart-c72a6d35-55e2-4b50-9d5d-11846c6962d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313939944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.313939944
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3711935032
Short name T158
Test name
Test status
Simulation time 169331028556 ps
CPU time 116.9 seconds
Started Apr 15 12:56:08 PM PDT 24
Finished Apr 15 12:58:05 PM PDT 24
Peak memory 202332 kb
Host smart-33c052e8-49e9-45d3-a995-63a4ed4e6dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711935032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3711935032
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3402213003
Short name T305
Test name
Test status
Simulation time 153051500011 ps
CPU time 486.72 seconds
Started Apr 15 12:56:06 PM PDT 24
Finished Apr 15 01:04:13 PM PDT 24
Peak memory 210964 kb
Host smart-09d5884d-2cba-4c12-8f06-06b46d6fbcdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402213003 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3402213003
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2702446888
Short name T534
Test name
Test status
Simulation time 638869364 ps
CPU time 0.71 seconds
Started Apr 15 12:56:17 PM PDT 24
Finished Apr 15 12:56:18 PM PDT 24
Peak memory 201880 kb
Host smart-a196eba2-300e-4213-8af8-7ef6e90a9867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702446888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2702446888
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1190494084
Short name T768
Test name
Test status
Simulation time 375719330383 ps
CPU time 220.35 seconds
Started Apr 15 12:56:12 PM PDT 24
Finished Apr 15 12:59:53 PM PDT 24
Peak memory 202204 kb
Host smart-8ad5da38-b946-49eb-b208-b78a568e137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190494084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1190494084
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.149814543
Short name T594
Test name
Test status
Simulation time 487239614859 ps
CPU time 1038.48 seconds
Started Apr 15 12:56:08 PM PDT 24
Finished Apr 15 01:13:27 PM PDT 24
Peak memory 202344 kb
Host smart-a0b60653-88df-43d2-8593-b5ba195fe9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149814543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.149814543
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1730777772
Short name T520
Test name
Test status
Simulation time 318922546496 ps
CPU time 467.33 seconds
Started Apr 15 12:56:09 PM PDT 24
Finished Apr 15 01:03:57 PM PDT 24
Peak memory 202236 kb
Host smart-60a73ef8-aae4-434e-b6f3-1740a58ca13c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730777772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1730777772
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.816513138
Short name T344
Test name
Test status
Simulation time 494707971900 ps
CPU time 276.13 seconds
Started Apr 15 12:56:10 PM PDT 24
Finished Apr 15 01:00:47 PM PDT 24
Peak memory 202284 kb
Host smart-5ae881af-0333-46db-a5db-8a1a769bd603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816513138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.816513138
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1213339592
Short name T416
Test name
Test status
Simulation time 495864747156 ps
CPU time 946.88 seconds
Started Apr 15 12:56:10 PM PDT 24
Finished Apr 15 01:11:58 PM PDT 24
Peak memory 202196 kb
Host smart-df0ad9cf-dc3f-421d-998d-1b7ed2502a0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213339592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1213339592
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1800437648
Short name T244
Test name
Test status
Simulation time 188681157193 ps
CPU time 457.92 seconds
Started Apr 15 12:56:14 PM PDT 24
Finished Apr 15 01:03:52 PM PDT 24
Peak memory 202364 kb
Host smart-65fca168-73be-4afa-b0fa-b6b70b2a9014
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800437648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1800437648
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.138759134
Short name T176
Test name
Test status
Simulation time 596843698724 ps
CPU time 1461.49 seconds
Started Apr 15 12:56:14 PM PDT 24
Finished Apr 15 01:20:36 PM PDT 24
Peak memory 202332 kb
Host smart-273cc527-d494-481f-8f13-3f5058601f61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138759134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.138759134
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1450096124
Short name T355
Test name
Test status
Simulation time 97784258589 ps
CPU time 282.55 seconds
Started Apr 15 12:56:14 PM PDT 24
Finished Apr 15 01:00:57 PM PDT 24
Peak memory 202476 kb
Host smart-5320ff5c-074f-4fe6-8b95-c0ebd85166c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450096124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1450096124
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2083933697
Short name T477
Test name
Test status
Simulation time 27647181001 ps
CPU time 67.62 seconds
Started Apr 15 12:56:14 PM PDT 24
Finished Apr 15 12:57:22 PM PDT 24
Peak memory 202120 kb
Host smart-2e85906e-d80d-4026-b653-4967fc4f520b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083933697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2083933697
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4135517042
Short name T636
Test name
Test status
Simulation time 4361868596 ps
CPU time 10.41 seconds
Started Apr 15 12:56:13 PM PDT 24
Finished Apr 15 12:56:24 PM PDT 24
Peak memory 202108 kb
Host smart-1c8db5e2-01b7-4f9e-b9de-06e4c1678ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135517042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4135517042
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.4022456531
Short name T701
Test name
Test status
Simulation time 5863091834 ps
CPU time 15.39 seconds
Started Apr 15 12:56:10 PM PDT 24
Finished Apr 15 12:56:26 PM PDT 24
Peak memory 202056 kb
Host smart-857a08c1-2e00-4322-bd38-fbe8ce4a3d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022456531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.4022456531
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3076229270
Short name T691
Test name
Test status
Simulation time 102733355199 ps
CPU time 59 seconds
Started Apr 15 12:56:16 PM PDT 24
Finished Apr 15 12:57:15 PM PDT 24
Peak memory 210624 kb
Host smart-92b1894c-7493-4e85-a438-3acd7aefa318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076229270 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3076229270
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3402999604
Short name T507
Test name
Test status
Simulation time 327442774 ps
CPU time 0.99 seconds
Started Apr 15 12:56:25 PM PDT 24
Finished Apr 15 12:56:27 PM PDT 24
Peak memory 201984 kb
Host smart-e5567294-aac2-4dc7-9d8d-09883d731102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402999604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3402999604
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2217200445
Short name T482
Test name
Test status
Simulation time 163775930566 ps
CPU time 115.42 seconds
Started Apr 15 12:56:22 PM PDT 24
Finished Apr 15 12:58:18 PM PDT 24
Peak memory 202140 kb
Host smart-ea242b8c-397a-4a39-b500-72f148050d9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217200445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2217200445
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.601278574
Short name T123
Test name
Test status
Simulation time 354762632261 ps
CPU time 775.96 seconds
Started Apr 15 12:56:27 PM PDT 24
Finished Apr 15 01:09:23 PM PDT 24
Peak memory 202192 kb
Host smart-4b633738-e85e-4dea-b687-322380f26203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601278574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.601278574
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2210543682
Short name T317
Test name
Test status
Simulation time 490122795792 ps
CPU time 582.13 seconds
Started Apr 15 12:56:22 PM PDT 24
Finished Apr 15 01:06:05 PM PDT 24
Peak memory 202344 kb
Host smart-29098d6a-33bf-4711-b422-f527614f01d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210543682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2210543682
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2444914737
Short name T600
Test name
Test status
Simulation time 158048021920 ps
CPU time 174.27 seconds
Started Apr 15 12:56:22 PM PDT 24
Finished Apr 15 12:59:17 PM PDT 24
Peak memory 202220 kb
Host smart-b75dc4ff-9ed2-4148-822e-f44384481cc2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444914737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2444914737
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3047088439
Short name T199
Test name
Test status
Simulation time 480992231549 ps
CPU time 297.62 seconds
Started Apr 15 12:56:16 PM PDT 24
Finished Apr 15 01:01:14 PM PDT 24
Peak memory 202228 kb
Host smart-fa70703f-fd98-4c10-860f-3413315aae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047088439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3047088439
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1003510776
Short name T369
Test name
Test status
Simulation time 167113522476 ps
CPU time 383.69 seconds
Started Apr 15 12:56:22 PM PDT 24
Finished Apr 15 01:02:46 PM PDT 24
Peak memory 202320 kb
Host smart-bf94e57d-6844-440f-b7d8-ce20489a1cc1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003510776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1003510776
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2408200838
Short name T413
Test name
Test status
Simulation time 194471787540 ps
CPU time 71.41 seconds
Started Apr 15 12:56:22 PM PDT 24
Finished Apr 15 12:57:34 PM PDT 24
Peak memory 202212 kb
Host smart-6ae704a6-633b-424c-9876-a7c917946a5b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408200838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2408200838
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1112592809
Short name T191
Test name
Test status
Simulation time 95655524268 ps
CPU time 530.16 seconds
Started Apr 15 12:56:25 PM PDT 24
Finished Apr 15 01:05:16 PM PDT 24
Peak memory 202588 kb
Host smart-a0677d2b-15d7-42c1-831a-96d3b9a499ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112592809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1112592809
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2837381347
Short name T517
Test name
Test status
Simulation time 30742633125 ps
CPU time 68.37 seconds
Started Apr 15 12:56:26 PM PDT 24
Finished Apr 15 12:57:35 PM PDT 24
Peak memory 202076 kb
Host smart-ceef1e31-2ca3-43fb-931b-cf891ff3827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837381347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2837381347
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3360509173
Short name T118
Test name
Test status
Simulation time 3547762509 ps
CPU time 3 seconds
Started Apr 15 12:56:26 PM PDT 24
Finished Apr 15 12:56:29 PM PDT 24
Peak memory 202128 kb
Host smart-0f119540-65b4-4888-853f-c2b44bd451d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360509173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3360509173
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1297448518
Short name T791
Test name
Test status
Simulation time 5932595568 ps
CPU time 14.73 seconds
Started Apr 15 12:56:16 PM PDT 24
Finished Apr 15 12:56:31 PM PDT 24
Peak memory 202020 kb
Host smart-d8ee12df-5ecf-43fd-bc18-5d9b2ca60802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297448518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1297448518
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3240650648
Short name T336
Test name
Test status
Simulation time 201008999371 ps
CPU time 209.91 seconds
Started Apr 15 12:56:25 PM PDT 24
Finished Apr 15 12:59:56 PM PDT 24
Peak memory 202208 kb
Host smart-0c0efdd0-e673-4da1-a99d-4ca3753db6dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240650648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3240650648
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1850543791
Short name T561
Test name
Test status
Simulation time 48427409504 ps
CPU time 117.07 seconds
Started Apr 15 12:56:28 PM PDT 24
Finished Apr 15 12:58:25 PM PDT 24
Peak memory 202484 kb
Host smart-4503d921-e70b-44c0-8f9c-e06bb43df175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850543791 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1850543791
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3443625005
Short name T83
Test name
Test status
Simulation time 363673700 ps
CPU time 1.45 seconds
Started Apr 15 12:56:33 PM PDT 24
Finished Apr 15 12:56:34 PM PDT 24
Peak memory 201932 kb
Host smart-21025b48-f72f-481a-86db-b453b880a19b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443625005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3443625005
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2462570522
Short name T168
Test name
Test status
Simulation time 498385244154 ps
CPU time 321.61 seconds
Started Apr 15 12:56:28 PM PDT 24
Finished Apr 15 01:01:50 PM PDT 24
Peak memory 202388 kb
Host smart-cf57fb7d-5ce7-4145-9645-54f7ead03f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462570522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2462570522
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3148928163
Short name T739
Test name
Test status
Simulation time 492477008328 ps
CPU time 1156.9 seconds
Started Apr 15 12:56:25 PM PDT 24
Finished Apr 15 01:15:43 PM PDT 24
Peak memory 202228 kb
Host smart-ce9ddfad-f98a-4541-85d7-e15c0fb71b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148928163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3148928163
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.352227959
Short name T418
Test name
Test status
Simulation time 491017739649 ps
CPU time 592.21 seconds
Started Apr 15 12:56:28 PM PDT 24
Finished Apr 15 01:06:21 PM PDT 24
Peak memory 202240 kb
Host smart-e842d261-257f-493b-b0e9-399c27c5ec1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=352227959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.352227959
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.199815740
Short name T449
Test name
Test status
Simulation time 164473866046 ps
CPU time 194.43 seconds
Started Apr 15 12:56:27 PM PDT 24
Finished Apr 15 12:59:41 PM PDT 24
Peak memory 202256 kb
Host smart-7cdb5a73-29c5-4a00-868b-0d4e103ada16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=199815740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.199815740
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1357912779
Short name T708
Test name
Test status
Simulation time 266673205602 ps
CPU time 668.47 seconds
Started Apr 15 12:56:39 PM PDT 24
Finished Apr 15 01:07:48 PM PDT 24
Peak memory 202244 kb
Host smart-c22ed04e-3bf1-442f-a9f6-ddb3a05932a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357912779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1357912779
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.782597157
Short name T459
Test name
Test status
Simulation time 209221438152 ps
CPU time 37.67 seconds
Started Apr 15 12:56:30 PM PDT 24
Finished Apr 15 12:57:09 PM PDT 24
Peak memory 202212 kb
Host smart-740ff4f9-2322-4721-8a8b-c7ff55de39d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782597157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.782597157
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3061184687
Short name T452
Test name
Test status
Simulation time 120639891261 ps
CPU time 479.34 seconds
Started Apr 15 12:56:33 PM PDT 24
Finished Apr 15 01:04:33 PM PDT 24
Peak memory 202668 kb
Host smart-2e517b16-130c-46fe-b16a-e3fd70a72876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061184687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3061184687
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1090688122
Short name T738
Test name
Test status
Simulation time 35913309863 ps
CPU time 79.21 seconds
Started Apr 15 12:56:36 PM PDT 24
Finished Apr 15 12:57:56 PM PDT 24
Peak memory 202092 kb
Host smart-7c7aaaf8-de01-44f4-9b93-cdceed10bc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090688122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1090688122
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2591502186
Short name T687
Test name
Test status
Simulation time 3292254119 ps
CPU time 2.59 seconds
Started Apr 15 12:56:31 PM PDT 24
Finished Apr 15 12:56:34 PM PDT 24
Peak memory 202020 kb
Host smart-2a3b4e0d-aa46-41b8-8d8a-b58bb765d895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591502186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2591502186
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1517006395
Short name T378
Test name
Test status
Simulation time 5814901383 ps
CPU time 8.13 seconds
Started Apr 15 12:56:24 PM PDT 24
Finished Apr 15 12:56:32 PM PDT 24
Peak memory 202088 kb
Host smart-695e31b1-85fe-4633-ada9-d7999e36bef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517006395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1517006395
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3546019853
Short name T134
Test name
Test status
Simulation time 312161344488 ps
CPU time 83.59 seconds
Started Apr 15 12:56:34 PM PDT 24
Finished Apr 15 12:57:58 PM PDT 24
Peak memory 212784 kb
Host smart-d9f475be-f3de-4b9d-bcdc-f62d6c07f6f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546019853 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3546019853
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2926807092
Short name T668
Test name
Test status
Simulation time 372206867 ps
CPU time 0.83 seconds
Started Apr 15 12:56:42 PM PDT 24
Finished Apr 15 12:56:43 PM PDT 24
Peak memory 201980 kb
Host smart-8f28b7df-ff3d-441c-9a32-864a50b6a9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926807092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2926807092
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1728974284
Short name T201
Test name
Test status
Simulation time 497454831414 ps
CPU time 229.98 seconds
Started Apr 15 12:56:40 PM PDT 24
Finished Apr 15 01:00:30 PM PDT 24
Peak memory 202240 kb
Host smart-ba78da8e-1f0d-458e-a44b-2ee43c471719
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728974284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1728974284
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.4117113233
Short name T669
Test name
Test status
Simulation time 184385861742 ps
CPU time 154.68 seconds
Started Apr 15 12:56:37 PM PDT 24
Finished Apr 15 12:59:12 PM PDT 24
Peak memory 202248 kb
Host smart-a999c75e-f527-40d1-8fd3-a2ff64811114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117113233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.4117113233
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.578735842
Short name T251
Test name
Test status
Simulation time 164561158273 ps
CPU time 186.33 seconds
Started Apr 15 12:56:34 PM PDT 24
Finished Apr 15 12:59:41 PM PDT 24
Peak memory 202388 kb
Host smart-d5ec3571-6305-4abd-a38d-65d7a82bdb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578735842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.578735842
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.803897410
Short name T405
Test name
Test status
Simulation time 163056567030 ps
CPU time 30.25 seconds
Started Apr 15 12:56:34 PM PDT 24
Finished Apr 15 12:57:05 PM PDT 24
Peak memory 202204 kb
Host smart-33a91242-419c-4bd8-8262-82e78dd7d5c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=803897410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.803897410
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1682849022
Short name T523
Test name
Test status
Simulation time 332402863176 ps
CPU time 388.21 seconds
Started Apr 15 12:56:33 PM PDT 24
Finished Apr 15 01:03:02 PM PDT 24
Peak memory 202316 kb
Host smart-d973a981-34ae-4627-8b55-775928efbe59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682849022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1682849022
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.193055651
Short name T635
Test name
Test status
Simulation time 173037338952 ps
CPU time 391.23 seconds
Started Apr 15 12:56:34 PM PDT 24
Finished Apr 15 01:03:06 PM PDT 24
Peak memory 202280 kb
Host smart-8b30665a-b456-4366-8fa9-89048e796451
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193055651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.193055651
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2837253034
Short name T463
Test name
Test status
Simulation time 588555344088 ps
CPU time 679.91 seconds
Started Apr 15 12:56:41 PM PDT 24
Finished Apr 15 01:08:02 PM PDT 24
Peak memory 202264 kb
Host smart-81e8df01-8270-4d2e-b052-bc2c1664a87c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837253034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2837253034
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3903421236
Short name T356
Test name
Test status
Simulation time 133447529657 ps
CPU time 733.5 seconds
Started Apr 15 12:56:36 PM PDT 24
Finished Apr 15 01:08:50 PM PDT 24
Peak memory 202676 kb
Host smart-6e5a2fdd-f285-46ff-9b6f-aea3f98bd7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903421236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3903421236
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2370954818
Short name T569
Test name
Test status
Simulation time 46171439534 ps
CPU time 99.76 seconds
Started Apr 15 12:56:40 PM PDT 24
Finished Apr 15 12:58:20 PM PDT 24
Peak memory 202092 kb
Host smart-239b7f4b-758e-4aee-a1a6-9d7f9a021f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370954818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2370954818
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2467404950
Short name T612
Test name
Test status
Simulation time 4908510207 ps
CPU time 6.38 seconds
Started Apr 15 12:56:42 PM PDT 24
Finished Apr 15 12:56:48 PM PDT 24
Peak memory 201880 kb
Host smart-aebe307d-aaca-41b9-8da5-53f815494640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467404950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2467404950
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3403363311
Short name T505
Test name
Test status
Simulation time 5744118753 ps
CPU time 3.76 seconds
Started Apr 15 12:56:34 PM PDT 24
Finished Apr 15 12:56:38 PM PDT 24
Peak memory 202076 kb
Host smart-566c9dfe-4d14-4c40-8818-8d4735b2e5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403363311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3403363311
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3030737601
Short name T546
Test name
Test status
Simulation time 166512830890 ps
CPU time 869.17 seconds
Started Apr 15 12:56:40 PM PDT 24
Finished Apr 15 01:11:10 PM PDT 24
Peak memory 202572 kb
Host smart-20aadcbd-d211-400c-88ee-d9647357bfa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030737601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3030737601
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1167993912
Short name T721
Test name
Test status
Simulation time 6400506551 ps
CPU time 22.49 seconds
Started Apr 15 12:56:42 PM PDT 24
Finished Apr 15 12:57:04 PM PDT 24
Peak memory 202492 kb
Host smart-c935a065-4d67-4a1a-b125-d683fc046abd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167993912 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1167993912
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1304707739
Short name T81
Test name
Test status
Simulation time 464765870 ps
CPU time 1.18 seconds
Started Apr 15 12:56:53 PM PDT 24
Finished Apr 15 12:56:55 PM PDT 24
Peak memory 202000 kb
Host smart-7f5fa96c-008a-4a85-9a7e-704d914ee7b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304707739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1304707739
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1306178678
Short name T295
Test name
Test status
Simulation time 165995777147 ps
CPU time 94.82 seconds
Started Apr 15 12:56:47 PM PDT 24
Finished Apr 15 12:58:22 PM PDT 24
Peak memory 202320 kb
Host smart-b073e6ac-6c4f-4d25-ac79-4929a114fb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306178678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1306178678
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.78765159
Short name T788
Test name
Test status
Simulation time 326768832228 ps
CPU time 403.52 seconds
Started Apr 15 12:56:47 PM PDT 24
Finished Apr 15 01:03:31 PM PDT 24
Peak memory 202340 kb
Host smart-1e8596d1-b870-48ee-bf4f-dc3567c87261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78765159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.78765159
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2189529781
Short name T641
Test name
Test status
Simulation time 495336695337 ps
CPU time 277.97 seconds
Started Apr 15 12:56:48 PM PDT 24
Finished Apr 15 01:01:26 PM PDT 24
Peak memory 202220 kb
Host smart-9cf4f888-ee75-47c5-8c57-9e64d6d2b399
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189529781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2189529781
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.4273787662
Short name T315
Test name
Test status
Simulation time 160825265229 ps
CPU time 193.94 seconds
Started Apr 15 12:56:42 PM PDT 24
Finished Apr 15 12:59:56 PM PDT 24
Peak memory 202208 kb
Host smart-83d754d9-c6f6-4e12-8d82-041050242b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273787662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.4273787662
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4260341792
Short name T682
Test name
Test status
Simulation time 494709903142 ps
CPU time 1187.76 seconds
Started Apr 15 12:56:43 PM PDT 24
Finished Apr 15 01:16:31 PM PDT 24
Peak memory 202260 kb
Host smart-1f5bf51a-f1ef-4704-a9c9-00d3e7206caf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260341792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4260341792
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2476201967
Short name T241
Test name
Test status
Simulation time 193156731700 ps
CPU time 95.22 seconds
Started Apr 15 12:56:48 PM PDT 24
Finished Apr 15 12:58:23 PM PDT 24
Peak memory 202264 kb
Host smart-ff0ea253-7250-467b-b41c-dea5ce71de4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476201967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2476201967
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.156570629
Short name T538
Test name
Test status
Simulation time 600365620094 ps
CPU time 357.24 seconds
Started Apr 15 12:56:52 PM PDT 24
Finished Apr 15 01:02:50 PM PDT 24
Peak memory 202340 kb
Host smart-f42e8c06-b92e-4b44-beab-c7a3d0bd779e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156570629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.156570629
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1193841527
Short name T592
Test name
Test status
Simulation time 64201729240 ps
CPU time 348.74 seconds
Started Apr 15 12:56:50 PM PDT 24
Finished Apr 15 01:02:39 PM PDT 24
Peak memory 202680 kb
Host smart-836bd667-fb33-43fe-8abb-45c2c838c806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193841527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1193841527
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2851551080
Short name T532
Test name
Test status
Simulation time 25436890309 ps
CPU time 58.19 seconds
Started Apr 15 12:56:50 PM PDT 24
Finished Apr 15 12:57:49 PM PDT 24
Peak memory 202104 kb
Host smart-6ee50530-40e8-42aa-92c2-46c08332d2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851551080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2851551080
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.977230677
Short name T703
Test name
Test status
Simulation time 4086682281 ps
CPU time 4.6 seconds
Started Apr 15 12:56:47 PM PDT 24
Finished Apr 15 12:56:52 PM PDT 24
Peak memory 202068 kb
Host smart-7e56e13c-ac8c-4c2f-ad7c-3247006c34f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977230677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.977230677
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.310766616
Short name T656
Test name
Test status
Simulation time 5905893519 ps
CPU time 7.41 seconds
Started Apr 15 12:56:44 PM PDT 24
Finished Apr 15 12:56:52 PM PDT 24
Peak memory 202016 kb
Host smart-8296d278-825a-417e-9af9-b325b3cc3fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310766616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.310766616
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.296416562
Short name T643
Test name
Test status
Simulation time 274369746978 ps
CPU time 203.61 seconds
Started Apr 15 12:56:52 PM PDT 24
Finished Apr 15 01:00:16 PM PDT 24
Peak memory 210856 kb
Host smart-8fa06a02-b7e0-4b7b-a532-4f392da12ee6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296416562 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.296416562
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2487557343
Short name T695
Test name
Test status
Simulation time 296146556 ps
CPU time 1.25 seconds
Started Apr 15 12:50:59 PM PDT 24
Finished Apr 15 12:51:01 PM PDT 24
Peak memory 201960 kb
Host smart-894334bb-2c89-4e0f-9e33-939b7b1a368a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487557343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2487557343
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.849848969
Short name T610
Test name
Test status
Simulation time 159526134398 ps
CPU time 208.41 seconds
Started Apr 15 12:50:59 PM PDT 24
Finished Apr 15 12:54:28 PM PDT 24
Peak memory 202336 kb
Host smart-091697e4-2c3e-4838-a74b-82ecfbf17cfc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849848969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.849848969
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3579336931
Short name T163
Test name
Test status
Simulation time 522694188770 ps
CPU time 656.1 seconds
Started Apr 15 12:50:57 PM PDT 24
Finished Apr 15 01:01:54 PM PDT 24
Peak memory 202248 kb
Host smart-074d9e1b-d6ee-42d7-812e-e661dd6709cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579336931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3579336931
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2919131077
Short name T277
Test name
Test status
Simulation time 482118693816 ps
CPU time 1148.58 seconds
Started Apr 15 12:50:58 PM PDT 24
Finished Apr 15 01:10:07 PM PDT 24
Peak memory 202260 kb
Host smart-420036d8-1a58-4b88-a609-17dae0013446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919131077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2919131077
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2660656557
Short name T470
Test name
Test status
Simulation time 490657791381 ps
CPU time 219.35 seconds
Started Apr 15 12:51:00 PM PDT 24
Finished Apr 15 12:54:40 PM PDT 24
Peak memory 202316 kb
Host smart-fa9f05c3-f7b4-4390-b249-2679cd20d57c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660656557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2660656557
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1662955849
Short name T184
Test name
Test status
Simulation time 504335858687 ps
CPU time 327.71 seconds
Started Apr 15 12:50:58 PM PDT 24
Finished Apr 15 12:56:26 PM PDT 24
Peak memory 202336 kb
Host smart-52c0fef7-84f3-49be-af23-2a3801677192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662955849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1662955849
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1407078446
Short name T530
Test name
Test status
Simulation time 162422923593 ps
CPU time 168.58 seconds
Started Apr 15 12:50:56 PM PDT 24
Finished Apr 15 12:53:45 PM PDT 24
Peak memory 202168 kb
Host smart-bd7ccf26-ff34-4cb1-95fc-ab85fbf47ecd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407078446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1407078446
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2197965837
Short name T346
Test name
Test status
Simulation time 520341741403 ps
CPU time 1224.64 seconds
Started Apr 15 12:50:58 PM PDT 24
Finished Apr 15 01:11:23 PM PDT 24
Peak memory 202328 kb
Host smart-a6c0df4d-8e84-45eb-8b76-dac4bb17c7e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197965837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2197965837
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.146047832
Short name T742
Test name
Test status
Simulation time 605193806055 ps
CPU time 1438.94 seconds
Started Apr 15 12:51:00 PM PDT 24
Finished Apr 15 01:15:00 PM PDT 24
Peak memory 202248 kb
Host smart-704ebc6c-f0d3-4688-8c1e-5ee19f29f8de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146047832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.146047832
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2342571997
Short name T764
Test name
Test status
Simulation time 128915160619 ps
CPU time 408.38 seconds
Started Apr 15 12:50:55 PM PDT 24
Finished Apr 15 12:57:44 PM PDT 24
Peak memory 202628 kb
Host smart-849d8e36-6210-48dd-9f36-a93c4fe8188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342571997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2342571997
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1942416796
Short name T370
Test name
Test status
Simulation time 35153356459 ps
CPU time 41.45 seconds
Started Apr 15 12:50:59 PM PDT 24
Finished Apr 15 12:51:41 PM PDT 24
Peak memory 202032 kb
Host smart-3fcfd647-adab-4cc3-8af3-1ebf98af8f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942416796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1942416796
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2661601787
Short name T438
Test name
Test status
Simulation time 5327764325 ps
CPU time 3.59 seconds
Started Apr 15 12:50:55 PM PDT 24
Finished Apr 15 12:50:59 PM PDT 24
Peak memory 202048 kb
Host smart-6dd4f089-6dff-4f80-a5e4-1c5c93657d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661601787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2661601787
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3890986496
Short name T406
Test name
Test status
Simulation time 5854076424 ps
CPU time 13.13 seconds
Started Apr 15 12:50:57 PM PDT 24
Finished Apr 15 12:51:11 PM PDT 24
Peak memory 202076 kb
Host smart-f6b609f8-030f-4dca-81ea-dc9784228409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890986496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3890986496
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3404274415
Short name T40
Test name
Test status
Simulation time 225132220924 ps
CPU time 803.67 seconds
Started Apr 15 12:51:01 PM PDT 24
Finished Apr 15 01:04:26 PM PDT 24
Peak memory 202572 kb
Host smart-24e60570-56a7-4ca4-befa-7aca4f8aad32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404274415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3404274415
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3283278330
Short name T651
Test name
Test status
Simulation time 85799416518 ps
CPU time 215.13 seconds
Started Apr 15 12:50:56 PM PDT 24
Finished Apr 15 12:54:32 PM PDT 24
Peak memory 219076 kb
Host smart-0a5162cb-c521-47cc-bb50-3f28fc31bbe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283278330 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3283278330
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.873607660
Short name T492
Test name
Test status
Simulation time 476704799 ps
CPU time 1.95 seconds
Started Apr 15 12:51:01 PM PDT 24
Finished Apr 15 12:51:04 PM PDT 24
Peak memory 201972 kb
Host smart-79b20479-b423-4c33-aa9b-bf43de6f8fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873607660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.873607660
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3367765903
Short name T501
Test name
Test status
Simulation time 162327438835 ps
CPU time 61.72 seconds
Started Apr 15 12:50:59 PM PDT 24
Finished Apr 15 12:52:01 PM PDT 24
Peak memory 202280 kb
Host smart-fb51af1b-bba6-4b39-b4ba-a1c143fcd67c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367765903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3367765903
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1510649688
Short name T82
Test name
Test status
Simulation time 361741013312 ps
CPU time 866.81 seconds
Started Apr 15 12:51:01 PM PDT 24
Finished Apr 15 01:05:28 PM PDT 24
Peak memory 202304 kb
Host smart-f6648e0b-df1e-496c-b575-5f18d205d866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510649688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1510649688
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3476067269
Short name T181
Test name
Test status
Simulation time 490633321606 ps
CPU time 135.03 seconds
Started Apr 15 12:51:01 PM PDT 24
Finished Apr 15 12:53:17 PM PDT 24
Peak memory 202208 kb
Host smart-cf68f30d-7f2f-48ee-b900-cf20fd4a3bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476067269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3476067269
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.542124302
Short name T2
Test name
Test status
Simulation time 159228656471 ps
CPU time 95.69 seconds
Started Apr 15 12:51:01 PM PDT 24
Finished Apr 15 12:52:37 PM PDT 24
Peak memory 202244 kb
Host smart-bf489ebf-90aa-48ed-8355-84b8dfb81061
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=542124302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.542124302
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.4971024
Short name T715
Test name
Test status
Simulation time 497568093384 ps
CPU time 309.08 seconds
Started Apr 15 12:51:01 PM PDT 24
Finished Apr 15 12:56:10 PM PDT 24
Peak memory 202260 kb
Host smart-f9b31ebc-f8e8-48a7-98d2-c353d995316b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4971024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.4971024
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3524953488
Short name T126
Test name
Test status
Simulation time 330862470842 ps
CPU time 92.86 seconds
Started Apr 15 12:51:00 PM PDT 24
Finished Apr 15 12:52:33 PM PDT 24
Peak memory 202252 kb
Host smart-a8e7cda4-8ff7-408b-b494-30d6a218a545
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524953488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3524953488
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.832596351
Short name T511
Test name
Test status
Simulation time 418373934027 ps
CPU time 489.32 seconds
Started Apr 15 12:51:01 PM PDT 24
Finished Apr 15 12:59:11 PM PDT 24
Peak memory 202204 kb
Host smart-d84e4473-b4ce-4517-9d3c-2c146fd94bf9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832596351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.832596351
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3188252454
Short name T480
Test name
Test status
Simulation time 127922824001 ps
CPU time 490.9 seconds
Started Apr 15 12:51:03 PM PDT 24
Finished Apr 15 12:59:15 PM PDT 24
Peak memory 202596 kb
Host smart-968bd3b5-ea96-4968-b759-e1cfe854db22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188252454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3188252454
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.262690673
Short name T759
Test name
Test status
Simulation time 32908598531 ps
CPU time 75.3 seconds
Started Apr 15 12:51:04 PM PDT 24
Finished Apr 15 12:52:19 PM PDT 24
Peak memory 202092 kb
Host smart-dbe8ecc2-3b7f-4edc-9d22-039ef3ad2be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262690673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.262690673
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.734048816
Short name T366
Test name
Test status
Simulation time 3122631757 ps
CPU time 4.54 seconds
Started Apr 15 12:51:02 PM PDT 24
Finished Apr 15 12:51:07 PM PDT 24
Peak memory 202076 kb
Host smart-9ed16941-08c8-4700-8a09-acf0929bd5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734048816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.734048816
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.938175911
Short name T713
Test name
Test status
Simulation time 5798030569 ps
CPU time 7.55 seconds
Started Apr 15 12:50:59 PM PDT 24
Finished Apr 15 12:51:07 PM PDT 24
Peak memory 202104 kb
Host smart-4eba968f-196c-4769-a23d-2e72965e1bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938175911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.938175911
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4109405276
Short name T207
Test name
Test status
Simulation time 321264929094 ps
CPU time 188.21 seconds
Started Apr 15 12:51:00 PM PDT 24
Finished Apr 15 12:54:09 PM PDT 24
Peak memory 202224 kb
Host smart-13172c19-10e8-442d-83e1-139e3a94151d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109405276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4109405276
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.4004618332
Short name T133
Test name
Test status
Simulation time 434999320257 ps
CPU time 130.56 seconds
Started Apr 15 12:51:00 PM PDT 24
Finished Apr 15 12:53:11 PM PDT 24
Peak memory 213008 kb
Host smart-ec0a16e6-8a1c-4a94-8b24-6c4353e3241d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004618332 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.4004618332
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2789680272
Short name T597
Test name
Test status
Simulation time 292261165 ps
CPU time 0.98 seconds
Started Apr 15 12:51:07 PM PDT 24
Finished Apr 15 12:51:08 PM PDT 24
Peak memory 202000 kb
Host smart-7d4ebc75-e284-4486-9d96-561b9c6a2c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789680272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2789680272
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.907782228
Short name T324
Test name
Test status
Simulation time 362398784970 ps
CPU time 686.87 seconds
Started Apr 15 12:51:08 PM PDT 24
Finished Apr 15 01:02:35 PM PDT 24
Peak memory 202268 kb
Host smart-e63eff48-1188-4c41-95ba-c973e1e64dc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907782228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.907782228
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.4067889066
Short name T139
Test name
Test status
Simulation time 338652440746 ps
CPU time 79.63 seconds
Started Apr 15 12:51:05 PM PDT 24
Finished Apr 15 12:52:25 PM PDT 24
Peak memory 202132 kb
Host smart-8eefbb1e-80d4-4ffd-8820-aefd3f565ab1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067889066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.4067889066
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1441365097
Short name T567
Test name
Test status
Simulation time 327402965792 ps
CPU time 376.17 seconds
Started Apr 15 12:51:00 PM PDT 24
Finished Apr 15 12:57:17 PM PDT 24
Peak memory 202316 kb
Host smart-f6ba9631-f96b-4c49-a922-fc77a899d9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441365097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1441365097
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.672688579
Short name T655
Test name
Test status
Simulation time 501732323913 ps
CPU time 282.73 seconds
Started Apr 15 12:51:09 PM PDT 24
Finished Apr 15 12:55:52 PM PDT 24
Peak memory 202232 kb
Host smart-6943da5e-c887-4257-9c49-098a22e27523
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=672688579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.672688579
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2485791791
Short name T665
Test name
Test status
Simulation time 178302485989 ps
CPU time 432.73 seconds
Started Apr 15 12:51:10 PM PDT 24
Finished Apr 15 12:58:24 PM PDT 24
Peak memory 202276 kb
Host smart-d9d40e51-fc80-4be8-b192-bd908b2922f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485791791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2485791791
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.564752585
Short name T368
Test name
Test status
Simulation time 397915088162 ps
CPU time 161.67 seconds
Started Apr 15 12:51:04 PM PDT 24
Finished Apr 15 12:53:46 PM PDT 24
Peak memory 202308 kb
Host smart-69d356a4-6052-4577-89fe-3ed323384ebd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564752585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.564752585
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.4005769639
Short name T531
Test name
Test status
Simulation time 71666141091 ps
CPU time 314.19 seconds
Started Apr 15 12:51:05 PM PDT 24
Finished Apr 15 12:56:19 PM PDT 24
Peak memory 202684 kb
Host smart-e73c1e10-86a5-4838-b21a-15cfe7720d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005769639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.4005769639
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2218366182
Short name T443
Test name
Test status
Simulation time 30247928477 ps
CPU time 69.93 seconds
Started Apr 15 12:51:06 PM PDT 24
Finished Apr 15 12:52:16 PM PDT 24
Peak memory 202088 kb
Host smart-59ef686d-5859-41f3-a925-e3a3d9256ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218366182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2218366182
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3866359557
Short name T786
Test name
Test status
Simulation time 2823162461 ps
CPU time 4.02 seconds
Started Apr 15 12:51:04 PM PDT 24
Finished Apr 15 12:51:09 PM PDT 24
Peak memory 202076 kb
Host smart-1e5fb4c3-9d62-4679-8bed-58ae83aaf26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866359557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3866359557
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1633531086
Short name T380
Test name
Test status
Simulation time 6139381819 ps
CPU time 4.33 seconds
Started Apr 15 12:51:02 PM PDT 24
Finished Apr 15 12:51:07 PM PDT 24
Peak memory 202092 kb
Host smart-40ca2c6d-4b10-49bd-9086-47893b075607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633531086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1633531086
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1889334494
Short name T24
Test name
Test status
Simulation time 466448657 ps
CPU time 0.91 seconds
Started Apr 15 12:51:16 PM PDT 24
Finished Apr 15 12:51:17 PM PDT 24
Peak memory 201864 kb
Host smart-4bcdf42b-8acf-4eac-9591-a2c17fc7c368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889334494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1889334494
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.9385658
Short name T718
Test name
Test status
Simulation time 172254390633 ps
CPU time 346.52 seconds
Started Apr 15 12:51:10 PM PDT 24
Finished Apr 15 12:56:57 PM PDT 24
Peak memory 202236 kb
Host smart-a2562343-6bd1-470e-bef7-492602ba0864
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9385658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating.9385658
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2242480848
Short name T297
Test name
Test status
Simulation time 328854674780 ps
CPU time 761.42 seconds
Started Apr 15 12:51:09 PM PDT 24
Finished Apr 15 01:03:50 PM PDT 24
Peak memory 202196 kb
Host smart-5c2361ed-902e-4707-8202-2ba97b8cb76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242480848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2242480848
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1485002446
Short name T294
Test name
Test status
Simulation time 490803344197 ps
CPU time 560.54 seconds
Started Apr 15 12:51:11 PM PDT 24
Finished Apr 15 01:00:32 PM PDT 24
Peak memory 202272 kb
Host smart-82cfeb99-1afb-43f7-886a-65856eeca578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485002446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1485002446
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3449209437
Short name T382
Test name
Test status
Simulation time 324984758066 ps
CPU time 180.34 seconds
Started Apr 15 12:51:10 PM PDT 24
Finished Apr 15 12:54:11 PM PDT 24
Peak memory 202160 kb
Host smart-7fb8ce66-0aec-43ac-b8f0-ada72b233f04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449209437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3449209437
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2893591222
Short name T684
Test name
Test status
Simulation time 162126034491 ps
CPU time 102.79 seconds
Started Apr 15 12:51:04 PM PDT 24
Finished Apr 15 12:52:47 PM PDT 24
Peak memory 202280 kb
Host smart-150b8ee6-1f0f-4b05-977f-eb047d6b51e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893591222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2893591222
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3590236547
Short name T429
Test name
Test status
Simulation time 164875448588 ps
CPU time 378.08 seconds
Started Apr 15 12:51:11 PM PDT 24
Finished Apr 15 12:57:29 PM PDT 24
Peak memory 202228 kb
Host smart-6114a209-451d-4603-acd4-7ebefdb1d69b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590236547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3590236547
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.90848683
Short name T222
Test name
Test status
Simulation time 542542658898 ps
CPU time 189.73 seconds
Started Apr 15 12:51:11 PM PDT 24
Finished Apr 15 12:54:21 PM PDT 24
Peak memory 202260 kb
Host smart-298cdec8-a7b1-46c6-a907-24a9e95dd9c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90848683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_wa
keup.90848683
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3000653306
Short name T434
Test name
Test status
Simulation time 602117096052 ps
CPU time 1380.29 seconds
Started Apr 15 12:51:16 PM PDT 24
Finished Apr 15 01:14:17 PM PDT 24
Peak memory 202200 kb
Host smart-13bb0ddf-4f31-43b8-b47e-a4355a982cf7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000653306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3000653306
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1086785980
Short name T359
Test name
Test status
Simulation time 136904923881 ps
CPU time 721.51 seconds
Started Apr 15 12:51:08 PM PDT 24
Finished Apr 15 01:03:10 PM PDT 24
Peak memory 202516 kb
Host smart-ed16e2c7-5067-48aa-817c-59dfabb3d449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086785980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1086785980
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3609523416
Short name T440
Test name
Test status
Simulation time 44621331155 ps
CPU time 50 seconds
Started Apr 15 12:51:16 PM PDT 24
Finished Apr 15 12:52:06 PM PDT 24
Peak memory 202100 kb
Host smart-03be1bb6-b6df-46dc-a778-339f5659262b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609523416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3609523416
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.695947450
Short name T116
Test name
Test status
Simulation time 5937544238 ps
CPU time 14.56 seconds
Started Apr 15 12:51:09 PM PDT 24
Finished Apr 15 12:51:24 PM PDT 24
Peak memory 202076 kb
Host smart-92d746c4-f220-46e9-9aba-8fc4b7874d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695947450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.695947450
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2954877301
Short name T84
Test name
Test status
Simulation time 5841393740 ps
CPU time 14.84 seconds
Started Apr 15 12:51:03 PM PDT 24
Finished Apr 15 12:51:19 PM PDT 24
Peak memory 202096 kb
Host smart-7b921c46-6dd4-45ba-b785-eb8745f494a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954877301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2954877301
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2300243918
Short name T155
Test name
Test status
Simulation time 323282552380 ps
CPU time 714.36 seconds
Started Apr 15 12:51:15 PM PDT 24
Finished Apr 15 01:03:10 PM PDT 24
Peak memory 202368 kb
Host smart-000fec8f-9c57-4e5b-94cd-46025a3f9884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300243918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2300243918
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3999041144
Short name T601
Test name
Test status
Simulation time 37195487923 ps
CPU time 88.58 seconds
Started Apr 15 12:51:23 PM PDT 24
Finished Apr 15 12:52:53 PM PDT 24
Peak memory 210688 kb
Host smart-cf2c8fa7-75a3-4a3f-bd05-46a6ac02aea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999041144 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3999041144
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2573363299
Short name T699
Test name
Test status
Simulation time 306558385 ps
CPU time 0.83 seconds
Started Apr 15 12:51:19 PM PDT 24
Finished Apr 15 12:51:21 PM PDT 24
Peak memory 201972 kb
Host smart-a9625b8a-31e5-482e-8832-d9f96661159e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573363299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2573363299
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.112262321
Short name T796
Test name
Test status
Simulation time 501685039274 ps
CPU time 517.63 seconds
Started Apr 15 12:51:19 PM PDT 24
Finished Apr 15 12:59:57 PM PDT 24
Peak memory 202364 kb
Host smart-a9aabb32-e32f-4b42-8d52-4afdd874c33e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112262321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.112262321
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.4002776595
Short name T268
Test name
Test status
Simulation time 165919125537 ps
CPU time 396.34 seconds
Started Apr 15 12:51:20 PM PDT 24
Finished Apr 15 12:57:57 PM PDT 24
Peak memory 202304 kb
Host smart-f2d1c772-35b8-4145-93f6-076d78c0539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002776595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.4002776595
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1515874055
Short name T781
Test name
Test status
Simulation time 163335306970 ps
CPU time 34.76 seconds
Started Apr 15 12:51:19 PM PDT 24
Finished Apr 15 12:51:54 PM PDT 24
Peak memory 202124 kb
Host smart-58e25776-6549-4abc-ba14-e5c7cfa131e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515874055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1515874055
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3453000360
Short name T773
Test name
Test status
Simulation time 166913289178 ps
CPU time 106.09 seconds
Started Apr 15 12:51:15 PM PDT 24
Finished Apr 15 12:53:02 PM PDT 24
Peak memory 202068 kb
Host smart-e5dec8dd-f9d9-4f47-be6a-4f8367fb771b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453000360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3453000360
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.267442980
Short name T363
Test name
Test status
Simulation time 333122746392 ps
CPU time 792.97 seconds
Started Apr 15 12:51:18 PM PDT 24
Finished Apr 15 01:04:31 PM PDT 24
Peak memory 202232 kb
Host smart-4a834d7c-dce6-43d7-bdc5-a9ca3a29887d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=267442980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.267442980
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2031342822
Short name T274
Test name
Test status
Simulation time 538919847527 ps
CPU time 1247.73 seconds
Started Apr 15 12:51:21 PM PDT 24
Finished Apr 15 01:12:10 PM PDT 24
Peak memory 202348 kb
Host smart-9dd73684-cb66-4393-95b0-c2893999764b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031342822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2031342822
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2942336798
Short name T375
Test name
Test status
Simulation time 600061848810 ps
CPU time 1451.77 seconds
Started Apr 15 12:51:20 PM PDT 24
Finished Apr 15 01:15:32 PM PDT 24
Peak memory 202316 kb
Host smart-c532b8b0-2fd1-44e3-b9a3-0c6381baa639
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942336798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2942336798
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3919960203
Short name T361
Test name
Test status
Simulation time 134741829814 ps
CPU time 475.68 seconds
Started Apr 15 12:51:20 PM PDT 24
Finished Apr 15 12:59:17 PM PDT 24
Peak memory 202580 kb
Host smart-120c18be-759f-494c-9fc3-9e27d67a1ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919960203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3919960203
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.975853176
Short name T516
Test name
Test status
Simulation time 29987005803 ps
CPU time 20 seconds
Started Apr 15 12:51:22 PM PDT 24
Finished Apr 15 12:51:42 PM PDT 24
Peak memory 202048 kb
Host smart-856ac079-c391-417b-925a-f0491c2aaf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975853176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.975853176
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3391113356
Short name T37
Test name
Test status
Simulation time 3864957375 ps
CPU time 9.36 seconds
Started Apr 15 12:51:22 PM PDT 24
Finished Apr 15 12:51:32 PM PDT 24
Peak memory 202056 kb
Host smart-a5eeca9c-bddf-4647-b6cc-0799956b9a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391113356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3391113356
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3876548950
Short name T553
Test name
Test status
Simulation time 6110059009 ps
CPU time 11.98 seconds
Started Apr 15 12:51:16 PM PDT 24
Finished Apr 15 12:51:28 PM PDT 24
Peak memory 202080 kb
Host smart-e649b5d4-c92a-47c2-9687-563db61810d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876548950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3876548950
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2856319802
Short name T38
Test name
Test status
Simulation time 166574414651 ps
CPU time 789.07 seconds
Started Apr 15 12:51:18 PM PDT 24
Finished Apr 15 01:04:28 PM PDT 24
Peak memory 210852 kb
Host smart-6c9b1313-31d7-4268-b116-b326f08235c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856319802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2856319802
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.539751487
Short name T581
Test name
Test status
Simulation time 49489181400 ps
CPU time 116.87 seconds
Started Apr 15 12:51:20 PM PDT 24
Finished Apr 15 12:53:18 PM PDT 24
Peak memory 210924 kb
Host smart-b7ef64e1-7403-4426-9f97-7f2e27dd64a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539751487 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.539751487
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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