Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7016	1			T5	54		T6	8		T10	20
testmodes[AdcCtrlTestmodeNormal]	5845	1			T1	1		T2	2		T5	41
testmodes[AdcCtrlTestmodeLowpower]	5935	1			T3	2		T5	46		T9	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3709	1			T5	24		T6	6		T10	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1825	1			T5	14		T6	2		T11	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1367	1			T5	16		T11	3		T13	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1821	1			T5	16		T6	1		T11	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2186	1			T2	1		T5	13		T6	8
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1496	1			T5	12		T9	1		T11	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1373	1			T5	14		T13	3		T59	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1483	1			T5	13		T11	3		T13	5
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2836	1			T3	1		T5	18		T11	12