Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23078

1

T2

25

T3

3

T5

141

auto[ADC_CTRL_FILTER_COND_OUT]

3324

1

T1

13

T3

10

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20844

1

T3

3

T5

141

T6

18

auto[1]

5558

1

T1

13

T2

25

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	18	1			T132	6		T17	3		T216	9
values[0]	66	1			T178	8		T217	13		T218	9
values[1]	704	1			T3	3		T43	1		T37	6
values[2]	2852	1			T2	25		T8	1		T12	20
values[3]	590	1			T7	4		T85	9		T159	6
values[4]	767	1			T7	16		T49	1		T61	14
values[5]	596	1			T7	11		T13	3		T36	1
values[6]	580	1			T11	2		T49	1		T156	32
values[7]	652	1			T62	28		T47	12		T189	10
values[8]	685	1			T9	8		T11	3		T49	1
values[9]	1012	1			T1	13		T3	10		T9	25
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	826	1			T3	3		T43	1		T37	6
values[1]	2892	1			T2	25		T7	4		T8	1
values[2]	735	1			T49	1		T61	14		T219	11
values[3]	609	1			T7	16		T212	17		T213	12
values[4]	549	1			T7	11		T13	3		T49	1
values[5]	743	1			T11	2		T156	32		T159	13
values[6]	546	1			T9	8		T11	3		T62	28
values[7]	778	1			T1	13		T49	1		T56	1
values[8]	573	1			T3	10		T61	7		T219	1
values[9]	257	1			T9	25		T85	1		T220	1
minimum	17894	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	3		T37	1		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T43	1		T48	2		T72	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T2	2		T7	1		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	11		T173	19		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T49	1		T61	14		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T219	1		T164	5		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	1		T212	17		T31	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T213	3		T38	17		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T49	1		T211	9		T29	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	1		T13	2		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	1		T156	12		T221	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T156	3		T159	1		T211	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	8		T11	2		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T62	16		T71	13		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T56	1		T60	9		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	9		T49	1		T61	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T61	7		T219	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	10		T167	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T9	13		T53	2		T222	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T85	1		T220	1		T162	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17767	1			T5	141		T6	18		T10	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T37	5		T121	5		T168	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T48	3		T72	1		T164	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T2	23		T7	3		T57	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	9		T173	17		T159	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T85	8		T166	6		T223	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T219	10		T164	2		T29	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	15		T110	10		T215	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T213	9		T38	9		T122	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T29	10		T121	5		T122	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	10		T13	1		T71	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	1		T156	13		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T156	4		T159	12		T50	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	1		T47	11		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T62	12		T71	11		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T60	8		T72	1		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	4		T161	2		T162	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T159	10		T166	4		T15	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T167	10		T132	5		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T9	12		T53	1		T222	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T162	8		T33	6		T226	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T132	1		T17	3		T216	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T217	1		T227	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T178	8		T218	7		T228	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	3		T37	1		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T43	1		T48	2		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T2	2		T8	1		T54	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	11		T173	19		T72	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	1		T85	1		T166	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T159	1		T164	5		T127	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T7	1		T49	1		T61	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T219	1		T160	1		T213	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	10		T121	1		T122	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	1		T13	2		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	1		T49	1		T156	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T156	3		T159	1		T211	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T47	1		T189	10		T212	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T62	16		T166	1		T32	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	8		T11	2		T60	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T49	1		T61	5		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	13		T56	1		T61	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T1	9		T3	10		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T132	5		T216	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T217	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T218	2		T228	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T37	5		T121	5		T168	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T48	3		T72	1		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T2	23		T57	13		T58	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	9		T173	17		T72	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	3		T85	8		T166	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T159	5		T164	2		T127	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	15		T26	5		T229	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T219	10		T213	9		T29	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T29	10		T121	5		T122	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	10		T13	1		T71	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	1		T156	13		T230	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T156	4		T159	12		T231	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	11		T38	4		T221	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T62	12		T32	6		T174	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	1		T60	8		T72	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T71	11		T161	2		T162	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	12		T159	10		T166	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T1	4		T162	8		T167	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T3	1		T37	6		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T43	1		T48	5		T72	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T2	25		T7	4		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	10		T173	18		T159	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T49	1		T61	1		T85	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T219	11		T164	3		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	16		T212	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T213	10		T38	10		T122	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T49	1		T211	1		T29	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	11		T13	2		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	2		T156	14		T221	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T156	5		T159	13		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T11	3		T47	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T62	13		T71	12		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T56	1		T60	9		T72	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	5		T49	1		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T61	1		T219	1		T159	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T167	11		T132	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T9	13		T53	2		T222	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T85	1		T220	1		T162	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17881	1			T5	141		T6	18		T10	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	2		T134	5		T168	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T164	9		T221	13		T175	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T54	33		T41	13		T199	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	10		T173	18		T72	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T61	13		T166	9		T26	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T164	4		T29	14		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T212	16		T31	6		T110	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T213	2		T38	16		T127	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T211	8		T29	9		T122	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	1		T38	13		T211	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T156	11		T221	10		T31	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T156	2		T211	11		T50	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	7		T189	9		T212	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T62	15		T71	12		T32	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T60	8		T224	9		T167	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	8		T61	4		T189	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T61	6		T166	4		T15	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	9		T232	8		T209	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T9	12		T53	1		T186	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T162	6		T33	3		T226	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T31	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T132	6		T17	3		T216	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T217	13		T227	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T178	1		T218	3		T228	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	1		T37	6		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T43	1		T48	5		T72	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T2	25		T8	1		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	10		T173	18		T72	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	4		T85	9		T166	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T159	6		T164	3		T127	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	16		T49	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T219	11		T160	1		T213	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T29	11		T121	6		T122	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	11		T13	2		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	2		T49	1		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T156	5		T159	13		T211	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T47	12		T189	1		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T62	13		T166	1		T32	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	1		T11	3		T60	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T49	1		T61	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T9	13		T56	1		T61	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T1	5		T3	1		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T216	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T227	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T178	7		T218	6		T228	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	2		T134	5		T31	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T164	9		T221	13		T233	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T54	33		T41	13		T199	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	10		T173	18		T72	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T166	9		T212	22		T214	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T164	4		T127	14		T168	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T61	13		T26	4		T31	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T213	2		T29	14		T108	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T29	9		T122	17		T110	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	1		T38	29		T50	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T156	11		T211	8		T108	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T156	2		T211	18		T234	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T189	9		T212	17		T38	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T62	15		T32	2		T214	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	7		T60	8		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T61	4		T189	9		T71	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T9	12		T61	6		T166	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T1	8		T3	9		T189	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23297

1

T2

25

T3

13

T5

141

auto[ADC_CTRL_FILTER_COND_OUT]

3105

1

T1

13

T7

15

T9

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20972

1

T3

13

T5

141

T6

18

auto[1]

5430

1

T1

13

T2

25

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T61	14		T235	1		T236	10
values[0]	33	1			T176	15		T208	1		T237	9
values[1]	533	1			T11	3		T12	20		T219	1
values[2]	778	1			T13	3		T49	1		T36	1
values[3]	576	1			T3	3		T9	8		T41	28
values[4]	759	1			T7	11		T49	1		T156	25
values[5]	734	1			T3	10		T7	16		T61	12
values[6]	674	1			T11	2		T71	2		T159	11
values[7]	757	1			T9	25		T56	1		T60	17
values[8]	2716	1			T1	13		T2	25		T8	1
values[9]	934	1			T7	4		T85	1		T37	6
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	819	1			T11	3		T12	20		T219	1
values[1]	671	1			T13	3		T49	1		T36	1
values[2]	613	1			T3	3		T9	8		T49	1
values[3]	698	1			T7	11		T189	13		T220	1
values[4]	747	1			T3	10		T7	16		T11	2
values[5]	767	1			T189	10		T173	36		T159	11
values[6]	2830	1			T1	13		T2	25		T8	1
values[7]	549	1			T37	6		T159	13		T72	2
values[8]	613	1			T7	4		T220	1		T166	25
values[9]	212	1			T61	14		T85	1		T162	26
minimum	17883	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T85	1		T238	1		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	2		T12	11		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	1		T36	1		T164	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	2		T72	15		T164	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	3		T189	10		T156	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	8		T49	1		T41	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T189	13		T224	10		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	1		T220	1		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	10		T7	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T61	12		T71	14		T238	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T189	10		T72	1		T31	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T173	19		T159	1		T212	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T2	2		T8	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	9		T9	13		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T72	1		T127	15		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T37	1		T159	1		T221	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T166	10		T212	17		T167	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	1		T220	1		T166	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T61	14		T85	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T162	12		T231	2		T185	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17756	1			T5	141		T6	18		T10	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T85	8		T170	9		T162	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	1		T12	9		T62	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T164	2		T213	9		T26	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	1		T72	12		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T156	13		T38	11		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	14		T161	2		T29	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T224	9		T133	9		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	10		T223	4		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	15		T11	1		T47	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T71	12		T15	6		T114	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T72	1		T120	9		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T173	17		T159	10		T121	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T2	23		T57	13		T58	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	4		T9	12		T60	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T72	1		T127	16		T225	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T37	5		T159	12		T221	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T166	6		T167	13		T239	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T7	3		T166	4		T122	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T174	1		T240	13		T201	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T162	14		T231	1		T185	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T61	14		T235	1		T241	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T236	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T242	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T176	1		T208	1		T237	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T85	1		T238	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	2		T12	11		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	1		T36	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T13	2		T72	15		T164	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	3		T189	10		T164	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	8		T41	14		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T156	12		T224	10		T38	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	1		T49	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	10		T7	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T61	12		T71	13		T173	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	1		T72	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T71	1		T159	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T56	1		T189	10		T212	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	13		T60	9		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T2	2		T8	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T1	9		T159	2		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T85	1		T166	10		T167	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	1		T37	1		T220	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T241	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T236	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T176	14		T237	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T85	8		T132	3		T168	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	1		T12	9		T62	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T170	9		T213	9		T162	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	1		T72	12		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T164	2		T110	10		T230	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T41	14		T223	4		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T156	13		T224	9		T38	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	10		T29	12		T52	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	15		T47	11		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T71	11		T173	17		T15	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T11	1		T72	1		T167	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T71	1		T159	10		T50	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T221	9		T225	9		T243	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	12		T60	8		T219	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T2	23		T57	13		T58	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T1	4		T159	17		T132	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T166	6		T167	3		T244	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	3		T37	5		T166	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1