Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23095

1

T2

25

T3

3

T5

141

auto[ADC_CTRL_FILTER_COND_OUT]

3307

1

T1

13

T3

10

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20766

1

T3

3

T5

141

T6

18

auto[1]

5636

1

T1

13

T2

25

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	211	1			T220	1		T15	14		T215	11
values[0]	15	1			T315	2		T316	1		T227	12
values[1]	700	1			T3	3		T43	1		T37	6
values[2]	2878	1			T2	25		T8	1		T12	20
values[3]	597	1			T7	4		T85	9		T159	6
values[4]	768	1			T7	16		T49	1		T61	14
values[5]	603	1			T7	11		T13	3		T36	1
values[6]	575	1			T11	2		T49	1		T156	32
values[7]	634	1			T62	28		T47	12		T189	10
values[8]	687	1			T9	8		T11	3		T49	1
values[9]	854	1			T1	13		T3	10		T9	25
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	617	1			T43	1		T37	6		T220	1
values[1]	2924	1			T2	25		T7	4		T8	1
values[2]	738	1			T49	1		T61	14		T219	11
values[3]	661	1			T7	16		T212	17		T213	12
values[4]	537	1			T7	11		T13	3		T49	1
values[5]	663	1			T11	2		T156	32		T159	13
values[6]	571	1			T11	3		T62	28		T47	12
values[7]	718	1			T1	13		T9	8		T49	1
values[8]	737	1			T3	10		T61	7		T219	1
values[9]	158	1			T9	25		T220	1		T162	15
minimum	18078	1			T3	3		T5	141		T6	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T37	1		T220	1		T134	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T43	1		T72	1		T164	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1496	1			T2	2		T7	1		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	11		T173	19		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T49	1		T61	14		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T219	1		T164	5		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	1		T212	17		T31	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T213	3		T38	17		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T49	1		T211	9		T29	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T13	2		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T156	12		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T156	3		T159	1		T211	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	2		T47	1		T189	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T62	16		T71	13		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	8		T56	1		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	9		T49	1		T61	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T61	7		T219	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	10		T85	1		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T9	13		T222	2		T186	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T220	1		T162	7		T33	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17828	1			T3	3		T5	141		T6	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T48	2		T184	19		T305	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	5		T121	5		T168	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T72	1		T164	9		T221	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T2	23		T7	3		T57	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	9		T173	17		T159	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T85	8		T166	6		T223	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T219	10		T164	2		T29	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T7	15		T110	10		T215	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T213	9		T38	9		T122	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T29	10		T121	5		T122	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	10		T13	1		T71	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	1		T156	13		T132	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T156	4		T159	12		T50	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T47	11		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T62	12		T71	11		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T60	8		T72	1		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	4		T161	2		T162	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T159	10		T166	4		T15	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T167	10		T132	5		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T9	12		T222	2		T317	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T162	8		T33	6		T318	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	2		T13	3		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T48	3		T184	11		T305	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T15	8		T319	1		T320	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T220	1		T215	1		T17	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T315	1		T227	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T316	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	3		T37	1		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	1		T48	2		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T2	2		T8	1		T54	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	11		T173	19		T72	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T85	1		T166	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T159	1		T164	5		T168	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T7	1		T49	1		T61	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T219	1		T160	1		T213	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T29	10		T121	1		T122	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	1		T13	2		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	1		T49	1		T156	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T156	3		T159	1		T211	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T47	1		T189	10		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T62	16		T166	1		T32	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	8		T11	2		T60	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T49	1		T61	5		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	13		T56	1		T61	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T1	9		T3	10		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T15	6		T319	5		T320	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T215	10		T209	11		T318	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T315	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T37	5		T121	5		T168	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T48	3		T72	1		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T2	23		T57	13		T58	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	9		T173	17		T72	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	3		T85	8		T166	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T159	5		T164	2		T168	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	15		T26	5		T229	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T219	10		T213	9		T29	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T29	10		T121	5		T122	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	10		T13	1		T71	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	1		T156	13		T132	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T156	4		T159	12		T50	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T47	11		T38	4		T221	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T62	12		T32	6		T174	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	1		T60	8		T72	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T71	11		T161	2		T162	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	12		T159	10		T166	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	4		T162	8		T167	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T37	6		T220	1		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T43	1		T72	2		T164	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T2	25		T7	4		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	10		T173	18		T159	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T49	1		T61	1		T85	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T219	11		T164	3		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	16		T212	1		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T213	10		T38	10		T122	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T49	1		T211	1		T29	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	11		T13	2		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	2		T156	14		T132	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T156	5		T159	13		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	3		T47	12		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T62	13		T71	12		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T56	1		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	5		T49	1		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T61	1		T219	1		T159	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	1		T85	1		T167	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T9	13		T222	4		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T220	1		T162	9		T33	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17915	1			T3	1		T5	141		T6	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T48	5		T184	12		T305	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T134	5		T168	10		T174	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T164	9		T221	13		T233	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T54	33		T41	13		T199	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	10		T173	18		T72	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T61	13		T166	9		T26	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T164	4		T29	14		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T212	16		T31	6		T110	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T213	2		T38	16		T127	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T211	8		T29	9		T122	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	1		T38	13		T211	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T156	11		T31	10		T108	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T156	2		T211	11		T50	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T189	9		T212	17		T38	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T62	15		T71	12		T32	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	7		T60	8		T224	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	8		T61	4		T189	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T61	6		T166	4		T15	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	9		T226	10		T209	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T9	12		T186	16		T317	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T162	6		T33	3		T321	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T3	2		T31	13		T250	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T184	18		T305	14		T322	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T15	10		T319	6		T320	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T220	1		T215	11		T17	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T315	2		T227	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T316	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T37	6		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T43	1		T48	5		T72	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T2	25		T8	1		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	10		T173	18		T72	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	4		T85	9		T166	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T159	6		T164	3		T168	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T7	16		T49	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T219	11		T160	1		T213	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T29	11		T121	6		T122	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	11		T13	2		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	2		T49	1		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T156	5		T159	13		T211	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T47	12		T189	1		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T62	13		T166	1		T32	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	1		T11	3		T60	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T49	1		T61	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	13		T56	1		T61	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T1	5		T3	1		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T15	4		T320	3		T186	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T209	13		T193	7		T322	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T227	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	2		T134	5		T31	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T164	9		T221	13		T233	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T54	33		T41	13		T199	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	10		T173	18		T72	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T166	9		T214	14		T266	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T164	4		T168	11		T110	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T61	13		T212	16		T26	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T213	2		T29	14		T127	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T29	9		T122	17		T110	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	1		T38	29		T248	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T156	11		T211	8		T108	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T156	2		T211	18		T50	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T189	9		T212	17		T38	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T62	15		T32	2		T214	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	7		T60	8		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T61	4		T189	9		T71	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T9	12		T61	6		T166	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	8		T3	9		T189	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19