Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23017

1

T1

13

T2

25

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3385

1

T3

3

T7

16

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20967

1

T1

13

T3

10

T5

141

auto[1]

5435

1

T2

25

T3

3

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T320	7		T272	3		-	-
values[0]	36	1			T212	7		T248	27		T323	1
values[1]	757	1			T3	3		T13	3		T43	1
values[2]	664	1			T9	25		T85	1		T159	13
values[3]	704	1			T12	20		T61	5		T219	11
values[4]	637	1			T1	13		T11	2		T60	17
values[5]	2681	1			T2	25		T7	11		T8	1
values[6]	757	1			T7	16		T9	8		T49	1
values[7]	665	1			T7	4		T49	1		T56	1
values[8]	501	1			T3	10		T47	1		T37	6
values[9]	1110	1			T11	3		T61	7		T41	28
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	885	1			T3	3		T13	3		T43	1
values[1]	687	1			T9	25		T61	5		T219	11
values[2]	746	1			T12	20		T60	17		T36	1
values[3]	2769	1			T1	13		T2	25		T8	1
values[4]	456	1			T7	11		T11	2		T49	2
values[5]	917	1			T7	16		T9	8		T49	1
values[6]	559	1			T56	1		T189	10		T159	11
values[7]	398	1			T3	10		T7	4		T41	28
values[8]	770	1			T61	7		T161	14		T162	26
values[9]	244	1			T11	3		T166	16		T167	4
minimum	17971	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	2		T220	1		T160	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T3	3		T43	1		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	13		T61	5		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T159	1		T223	1		T134	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T72	1		T211	9		T50	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	11		T60	9		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T1	9		T2	2		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T219	1		T189	13		T156	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	1		T71	1		T167	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	1		T49	2		T61	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T9	8		T49	1		T62	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	1		T122	18		T127	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T56	1		T159	1		T72	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T189	10		T31	14		T33	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	10		T7	1		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T41	14		T37	1		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T61	7		T161	5		T162	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T161	7		T122	1		T111	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T11	2		T167	1		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T166	10		T115	1		T215	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17767	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T156	12		T173	19		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	1		T167	10		T32	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T38	11		T133	9		T122	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	12		T219	10		T164	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T159	12		T223	4		T175	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T72	1		T50	4		T121	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	9		T60	8		T47	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T1	4		T2	23		T57	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T156	4		T48	3		T170	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	10		T71	1		T167	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	1		T85	8		T164	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T62	12		T120	9		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	15		T122	16		T127	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T159	10		T72	1		T38	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T33	6		T168	1		T243	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T7	3		T71	11		T221	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T41	14		T37	5		T38	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T161	2		T162	14		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T122	1		T111	14		T266	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T11	1		T167	3		T229	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T166	6		T215	1		T305	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	2		T13	3		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T156	13		T173	17		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T272	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T320	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T212	7		T323	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T248	13		T311	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	2		T220	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T3	3		T43	1		T156	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	13		T85	1		T164	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T159	1		T223	1		T211	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T61	5		T219	1		T189	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	11		T36	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	9		T159	1		T26	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	1		T60	9		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1456	1			T2	2		T7	1		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T49	1		T61	14		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	8		T38	1		T167	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	1		T49	1		T164	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	1		T49	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T189	10		T31	14		T122	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	10		T47	1		T72	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T37	1		T238	1		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T11	2		T61	7		T71	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T41	14		T166	10		T161	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T320	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T248	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	1		T167	10		T32	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T156	13		T173	17		T38	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	12		T164	9		T166	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T159	12		T223	4		T15	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T219	10		T72	1		T213	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	9		T181	9		T175	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T1	4		T159	5		T26	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	1		T60	8		T47	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T2	23		T7	10		T57	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T85	8		T156	4		T170	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T167	3		T120	9		T51	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	15		T164	2		T127	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	3		T62	12		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T122	16		T168	1		T174	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T72	1		T176	5		T300	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T37	5		T38	4		T221	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	1		T71	11		T161	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T41	14		T166	6		T122	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	2		T220	1		T160	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	1		T43	1		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	13		T61	1		T219	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T159	13		T223	5		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T72	2		T211	1		T50	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	10		T60	9		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T1	5		T2	25		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T219	1		T189	1		T156	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	11		T71	2		T167	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	2		T49	2		T61	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T9	1		T49	1		T62	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	16		T122	17		T127	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T56	1		T159	11		T72	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T189	1		T31	1		T33	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	1		T7	4		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	15		T37	6		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T61	1		T161	3		T162	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T161	1		T122	2		T111	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	3		T167	4		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T166	7		T115	1		T215	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17899	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T156	14		T173	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	1		T212	6		T32	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T3	2		T38	13		T211	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	12		T61	4		T189	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T134	2		T31	6		T214	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T211	8		T50	6		T31	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	10		T60	8		T72	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1135	1			T1	8		T54	33		T199	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T189	12		T156	2		T212	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T167	4		T110	13		T248	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T61	13		T164	4		T212	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	7		T62	15		T51	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T122	17		T127	14		T174	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T38	16		T108	8		T304	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T189	9		T31	13		T33	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T3	9		T71	12		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T41	13		T38	4		T221	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T61	6		T161	4		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T161	6		T232	8		T248	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T253	1		T184	2		T272	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T166	9		T305	2		T320	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T227	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T156	11		T173	18		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T272	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T320	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T212	1		T323	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T248	15		T311	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	2		T220	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	1		T43	1		T156	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	13		T85	1		T164	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T159	13		T223	5		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T61	1		T219	11		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	10		T36	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T1	5		T159	6		T26	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	2		T60	9		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T2	25		T7	11		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T49	1		T61	1		T85	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	1		T38	1		T167	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	16		T49	1		T164	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	4		T49	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T189	1		T31	1		T122	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	1		T47	1		T72	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T37	6		T238	1		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T11	3		T61	1		T71	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T41	15		T166	7		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T272	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T320	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T212	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T248	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	1		T32	2		T168	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	2		T156	11		T173	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	12		T164	9		T166	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T211	11		T134	2		T15	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T61	4		T189	9		T213	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	10		T175	2		T266	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	8		T26	4		T253	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T60	8		T189	12		T72	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T54	33		T199	34		T247	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T61	13		T156	2		T212	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	7		T167	4		T51	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T164	4		T127	14		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T62	15		T38	16		T242	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T189	9		T31	13		T122	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T3	9		T108	8		T300	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T38	4		T221	13		T33	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T61	6		T71	12		T161	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T41	13		T166	9		T161	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19