Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23381

1

T1

13

T2

25

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3021

1

T3

10

T9

8

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20940

1

T3

10

T5

141

T6

18

auto[1]

5462

1

T1

13

T2

25

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	362	1			T61	14		T208	1		T226	15
values[0]	33	1			T124	1		T324	1		T256	28
values[1]	586	1			T3	10		T85	9		T159	17
values[2]	580	1			T61	7		T189	10		T220	2
values[3]	699	1			T7	4		T9	8		T49	1
values[4]	622	1			T7	16		T9	25		T12	20
values[5]	2768	1			T2	25		T8	1		T54	36
values[6]	597	1			T3	3		T7	11		T11	2
values[7]	584	1			T1	13		T13	3		T36	1
values[8]	789	1			T11	3		T49	1		T56	1
values[9]	902	1			T49	1		T61	5		T219	11
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	572	1			T85	9		T159	11		T72	27
values[1]	728	1			T7	4		T61	7		T62	28
values[2]	585	1			T9	33		T49	1		T85	1
values[3]	2735	1			T2	25		T7	16		T8	1
values[4]	607	1			T47	1		T189	10		T48	5
values[5]	640	1			T3	3		T7	11		T11	2
values[6]	570	1			T1	13		T36	1		T156	7
values[7]	697	1			T11	3		T49	1		T56	1
values[8]	991	1			T49	1		T61	19		T219	11
values[9]	196	1			T134	3		T115	1		T226	20
minimum	18081	1			T3	10		T5	141		T6	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T170	1		T121	1		T277	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T85	1		T159	1		T72	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	1		T189	10		T71	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T61	7		T62	16		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	13		T47	1		T161	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	8		T49	1		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T2	2		T7	1		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	11		T219	1		T212	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T166	11		T168	12		T53	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T47	1		T189	10		T48	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	3		T7	1		T238	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	1		T13	2		T72	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	9		T156	3		T211	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T36	1		T160	1		T161	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	2		T71	1		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	1		T56	1		T41	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T49	1		T61	19		T156	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T219	1		T37	1		T224	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T226	11		T242	8		T278	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T134	3		T115	1		T279	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17784	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T3	10		T132	1		T307	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T170	9		T121	5		T114	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T85	8		T159	10		T72	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	3		T71	11		T175	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T62	12		T159	5		T38	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T9	12		T47	11		T229	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T167	10		T29	22		T51	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T2	23		T7	15		T57	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	9		T162	8		T225	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T166	6		T168	11		T53	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T48	3		T164	2		T167	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	10		T162	14		T120	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T11	1		T13	1		T72	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	4		T156	4		T52	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T161	2		T221	6		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	1		T71	1		T223	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T41	14		T221	14		T121	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T156	13		T173	17		T166	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T219	10		T37	5		T224	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T226	9		T278	15		T204	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T279	13		T20	1		T261	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	2		T13	3		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T132	5		T249	2		T290	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T61	14		T325	12		T243	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T208	1		T226	7		T242	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T124	1		T324	1		T256	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T26	5		T33	7		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	10		T85	1		T159	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T189	10		T220	2		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T61	7		T167	1		T214	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	1		T47	1		T71	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	8		T49	1		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	1		T9	13		T60	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	11		T219	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T2	2		T8	1		T54	36
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T47	1		T189	10		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	3		T7	1		T238	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T11	1		T72	1		T164	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	9		T156	3		T134	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	2		T36	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	2		T71	1		T211	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T49	1		T56	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T49	1		T61	5		T156	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T219	1		T41	14		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T325	8		T243	17		T193	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T226	8		T209	9		T20	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T256	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T26	5		T33	6		T121	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T85	8		T159	15		T72	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T170	9		T114	5		T176	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T167	3		T174	1		T176	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	3		T47	11		T71	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T62	12		T38	9		T132	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	15		T9	12		T60	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	9		T162	8		T167	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T2	23		T57	13		T58	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T48	3		T167	3		T122	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	10		T162	14		T52	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T11	1		T72	1		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	4		T156	4		T120	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	1		T221	6		T51	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	1		T71	1		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T161	2		T221	14		T32	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T156	13		T173	17		T166	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T219	10		T41	14		T37	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T170	10		T121	6		T277	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T85	9		T159	11		T72	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	4		T189	1		T71	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T61	1		T62	13		T159	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	13		T47	12		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	1		T49	1		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T2	25		T7	16		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	10		T219	1		T212	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T166	8		T168	12		T53	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T47	1		T189	1		T48	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T7	11		T238	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	2		T13	2		T72	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	5		T156	5		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T36	1		T160	1		T161	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	3		T71	2		T223	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T49	1		T56	1		T41	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T49	1		T61	2		T156	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T219	11		T37	6		T224	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T226	10		T242	1		T278	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T134	1		T115	1		T279	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17916	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T3	1		T132	6		T307	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T232	8		T284	6		T248	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T72	14		T164	9		T213	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T189	9		T71	12		T175	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T61	6		T62	15		T38	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T9	12		T161	6		T108	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	7		T189	12		T29	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T54	33		T60	8		T199	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	10		T212	17		T162	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T166	9		T168	11		T53	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T189	9		T164	4		T167	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	2		T162	11		T275	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T13	1		T250	8		T182	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T1	8		T156	2		T211	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T161	4		T221	13		T211	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T212	6		T108	12		T234	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T41	13		T221	9		T175	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T61	17		T156	11		T173	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T224	9		T50	6		T174	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T226	10		T242	7		T278	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T134	2		T20	1		T261	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T26	4		T33	3		T326	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T3	9		T249	2		T290	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T61	1		T325	9		T243	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T208	1		T226	9		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T124	1		T324	1		T256	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T280	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T26	6		T33	10		T121	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T85	9		T159	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T189	1		T220	2		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T61	1		T167	4		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	4		T47	12		T71	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	1		T49	1		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	16		T9	13		T60	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	10		T219	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T2	25		T8	1		T54	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T47	1		T189	1		T48	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	1		T7	11		T238	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T11	2		T72	2		T164	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	5		T156	5		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	2		T36	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	3		T71	2		T211	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T49	1		T56	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T49	1		T61	1		T156	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T219	11		T41	15		T37	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T61	13		T325	11		T243	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T226	6		T242	15		T209	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T256	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T26	4		T33	3		T232	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	9		T72	14		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T189	9		T284	6		T304	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T61	6		T214	14		T232	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T71	12		T161	6		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	7		T62	15		T189	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	12		T60	8		T168	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T12	10		T162	6		T31	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T54	33		T199	34		T166	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T189	9		T212	17		T167	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	2		T162	11		T112	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T164	4		T250	8		T182	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T1	8		T156	2		T134	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T221	13		T211	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T211	7		T108	12		T234	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T161	4		T221	9		T31	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T61	4		T156	11		T173	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	13		T224	9		T50	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19