Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23055

1

T1

13

T2

25

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3347

1

T3

3

T7

16

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20980

1

T1

13

T3

10

T5

141

auto[1]

5422

1

T2

25

T3

3

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	201	1			T11	3		T166	16		T111	15
values[0]	85	1			T248	27		T323	1		T327	13
values[1]	744	1			T3	3		T13	3		T43	1
values[2]	620	1			T9	25		T61	5		T85	1
values[3]	790	1			T12	20		T60	17		T219	11
values[4]	553	1			T11	2		T219	1		T47	12
values[5]	2688	1			T1	13		T2	25		T7	11
values[6]	834	1			T7	16		T9	8		T49	1
values[7]	640	1			T7	4		T49	1		T56	1
values[8]	454	1			T3	10		T47	1		T37	6
values[9]	913	1			T61	7		T41	28		T71	24
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	688	1			T3	3		T13	3		T173	36
values[1]	674	1			T9	25		T61	5		T219	11
values[2]	791	1			T12	20		T60	17		T36	1
values[3]	2727	1			T1	13		T2	25		T8	1
values[4]	524	1			T7	11		T49	2		T61	14
values[5]	873	1			T7	16		T9	8		T49	1
values[6]	527	1			T7	4		T56	1		T189	10
values[7]	410	1			T3	10		T41	28		T47	1
values[8]	824	1			T61	7		T161	14		T162	26
values[9]	203	1			T11	3		T166	16		T167	4
minimum	18161	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	2		T220	1		T212	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T3	3		T173	19		T211	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	13		T61	5		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T159	1		T223	1		T134	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T72	1		T213	3		T50	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	11		T60	9		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T1	9		T2	2		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	1		T189	13		T156	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	1		T71	1		T167	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T49	2		T61	14		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T9	8		T49	1		T62	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	1		T31	14		T122	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T56	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T189	10		T33	7		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T3	10		T47	1		T71	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T41	14		T37	1		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T61	7		T161	5		T162	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T161	7		T111	1		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T11	2		T167	1		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T166	10		T122	1		T115	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17805	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T43	1		T156	12		T220	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	1		T38	11		T167	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T173	17		T133	9		T122	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	12		T219	10		T164	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T159	12		T223	4		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T72	1		T213	9		T50	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T12	9		T60	8		T47	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T1	4		T2	23		T57	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	1		T156	4		T170	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	10		T71	1		T167	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T85	8		T48	3		T164	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T62	12		T120	9		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	15		T122	16		T53	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	3		T159	10		T72	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T33	6		T168	1		T181	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T71	11		T221	9		T176	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T41	14		T37	5		T38	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T161	2		T162	14		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T111	14		T229	9		T266	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T11	1		T167	3		T229	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T166	6		T122	1		T215	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	2		T13	3		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T156	13		T244	9		T248	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T11	2		T214	1		T229	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T166	10		T111	1		T115	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T323	1		T328	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T248	13		T327	6		T329	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	2		T220	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	3		T43	1		T156	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	13		T61	5		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T159	1		T223	1		T211	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T219	1		T189	10		T72	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T12	11		T60	9		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T159	1		T26	5		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	1		T219	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1469	1			T1	9		T2	2		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T49	1		T61	14		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	8		T38	1		T167	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	1		T49	1		T164	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T49	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T189	10		T31	14		T122	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	10		T47	1		T72	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T37	1		T238	1		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T61	7		T71	13		T161	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T41	14		T161	7		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T11	1		T229	4		T330	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T166	6		T111	14		T243	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T328	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T248	14		T327	7		T329	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	1		T38	11		T167	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T156	13		T173	17		T133	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	12		T164	9		T166	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T159	12		T223	4		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T219	10		T72	1		T213	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	9		T60	8		T15	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T159	5		T26	5		T249	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T47	11		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T1	4		T2	23		T7	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T85	8		T156	4		T170	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T167	3		T120	9		T51	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	15		T164	2		T127	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	3		T62	12		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T122	16		T168	1		T181	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T72	1		T176	5		T300	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T37	5		T38	4		T221	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T71	11		T161	2		T162	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T41	14		T122	1		T229	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	2		T220	1		T212	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T173	18		T211	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	13		T61	1		T219	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T159	13		T223	5		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T72	2		T213	10		T50	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T12	10		T60	9		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T1	5		T2	25		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	2		T189	1		T156	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	11		T71	2		T167	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T49	2		T61	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T9	1		T49	1		T62	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	16		T31	1		T122	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	4		T56	1		T159	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T189	1		T33	10		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	1		T47	1		T71	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T41	15		T37	6		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T61	1		T161	3		T162	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T161	1		T111	15		T229	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T11	3		T167	4		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T166	7		T122	2		T115	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17956	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T43	1		T156	14		T220	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	1		T212	6		T38	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	2		T173	18		T211	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	12		T61	4		T189	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T134	2		T31	6		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T213	2		T50	6		T26	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	10		T60	8		T72	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T1	8		T54	33		T199	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T189	12		T156	2		T212	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T167	4		T110	13		T248	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T61	13		T164	4		T212	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	7		T62	15		T51	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	13		T122	17		T174	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T38	16		T304	12		T319	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T189	9		T33	3		T178	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T3	9		T71	12		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T41	13		T38	4		T221	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T61	6		T161	4		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T161	6		T232	8		T248	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T285	8		T184	2		T272	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T166	9		T258	11		T305	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T168	10		T304	10		T331	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T156	11		T244	11		T104	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T11	3		T214	1		T229	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T166	7		T111	15		T115	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T323	1		T328	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T248	15		T327	11		T329	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	2		T220	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	1		T43	1		T156	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	13		T61	1		T85	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T159	13		T223	5		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T219	11		T189	1		T72	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T12	10		T60	9		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T159	6		T26	6		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	2		T219	1		T47	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T1	5		T2	25		T7	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T49	1		T61	1		T85	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T9	1		T38	1		T167	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	16		T49	1		T164	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	4		T49	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T189	1		T31	1		T122	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	1		T47	1		T72	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T37	6		T238	1		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T61	1		T71	12		T161	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T41	15		T161	1		T122	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T234	17		T209	13		T332	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T166	9		T243	11		T305	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T248	12		T327	2		T329	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	1		T212	6		T38	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	2		T156	11		T173	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	12		T61	4		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T211	11		T134	2		T31	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T189	9		T213	2		T211	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	10		T60	8		T15	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T26	4		T253	8		T249	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T189	12		T72	14		T212	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1136	1			T1	8		T54	33		T199	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T61	13		T156	2		T212	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	7		T167	4		T51	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T164	4		T127	14		T178	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T62	15		T38	16		T265	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T189	9		T31	13		T122	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T3	9		T134	5		T108	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T38	4		T221	13		T33	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T61	6		T71	12		T161	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T41	13		T161	6		T232	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19