Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23360

1

T1

13

T2

25

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3042

1

T7

27

T11

3

T12

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20619

1

T1

13

T5

141

T6

18

auto[1]

5783

1

T2

25

T3

13

T7

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	231	1			T61	5		T221	20		T167	8
values[0]	20	1			T61	7		T85	1		T48	5
values[1]	541	1			T3	3		T9	8		T11	3
values[2]	763	1			T3	10		T71	24		T72	29
values[3]	686	1			T1	13		T12	20		T219	11
values[4]	2751	1			T2	25		T8	1		T49	1
values[5]	785	1			T85	9		T189	23		T164	19
values[6]	573	1			T11	2		T13	3		T49	1
values[7]	569	1			T7	11		T41	28		T47	1
values[8]	649	1			T9	25		T160	1		T213	12
values[9]	954	1			T7	20		T49	1		T61	14
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	547	1			T9	8		T11	3		T56	1
values[1]	715	1			T3	10		T219	11		T36	1
values[2]	639	1			T1	13		T12	20		T47	12
values[3]	2813	1			T2	25		T8	1		T49	1
values[4]	748	1			T11	2		T85	9		T189	13
values[5]	586	1			T7	11		T13	3		T49	1
values[6]	621	1			T159	24		T220	1		T164	7
values[7]	762	1			T7	16		T9	25		T189	10
values[8]	736	1			T7	4		T49	1		T61	19
values[9]	153	1			T37	6		T156	25		T212	18
minimum	18082	1			T3	3		T5	141		T6	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	8		T56	1		T48	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	2		T72	1		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	10		T219	1		T156	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T36	1		T71	13		T72	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	9		T47	1		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	11		T132	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T2	2		T8	1		T54	36
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T49	1		T60	9		T189	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	1		T85	1		T164	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T189	13		T212	17		T211	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	1		T41	14		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	1		T13	2		T62	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T159	1		T164	5		T166	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T159	1		T220	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T9	13		T189	10		T213	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	1		T160	1		T51	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	1		T49	1		T61	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T61	14		T220	1		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T53	1		T104	19		T255	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T37	1		T156	12		T212	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17823	1			T3	3		T5	141		T6	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T219	1		T258	12		T217	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T48	3		T26	5		T51	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T11	1		T72	1		T120	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T219	10		T156	4		T72	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T71	11		T72	12		T223	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	4		T47	11		T221	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	9		T132	5		T121	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T2	23		T57	13		T58	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T60	8		T71	1		T110	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	1		T85	8		T164	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T181	9		T260	6		T239	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T41	14		T224	9		T33	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	10		T13	1		T62	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T159	10		T164	2		T166	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T159	12		T167	3		T50	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	12		T213	9		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	15		T51	1		T110	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	3		T159	5		T221	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T161	2		T122	1		T168	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T255	13		T256	2		T241	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T37	5		T156	13		T296	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	2		T13	3		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T217	4		T210	12		T263	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T61	5		T221	14		T167	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T53	2		T253	8		T250	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T61	7		T85	1		T48	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T263	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	3		T9	8		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	2		T219	1		T72	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	10		T72	1		T166	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T71	13		T72	15		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	9		T219	1		T156	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	11		T36	1		T211	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T2	2		T8	1		T54	36
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	1		T60	9		T71	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T85	1		T164	10		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T189	23		T212	17		T211	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	1		T49	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	2		T62	16		T173	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T41	14		T47	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T7	1		T159	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	13		T213	3		T161	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T160	1		T167	1		T264	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T7	1		T49	1		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T7	1		T61	14		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T221	6		T167	3		T176	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T53	1		T253	7		T323	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T48	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T263	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T26	5		T222	2		T248	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T11	1		T72	1		T120	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T72	1		T166	6		T167	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T71	11		T72	12		T223	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	4		T219	10		T156	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	9		T132	5		T121	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T2	23		T57	13		T58	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T60	8		T71	1		T52	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T85	8		T164	9		T170	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T181	9		T16	1		T260	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	1		T224	9		T162	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	1		T62	12		T173	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T41	14		T159	10		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	10		T159	12		T50	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	12		T213	9		T15	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T167	3		T264	10		T209	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	3		T159	5		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	15		T37	5		T156	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	1		T56	1		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T11	3		T72	2		T120	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	1		T219	11		T156	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T36	1		T71	12		T72	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	5		T47	12		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	10		T132	6		T121	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T2	25		T8	1		T54	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T49	1		T60	9		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	2		T85	9		T164	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T189	1		T212	1		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	1		T41	15		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	11		T13	2		T62	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T159	11		T164	3		T166	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T159	13		T220	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	13		T189	1		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	16		T160	1		T51	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	4		T49	1		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T61	1		T220	1		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T53	1		T104	1		T255	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T37	6		T156	14		T212	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17952	1			T3	1		T5	141		T6	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T219	1		T258	1		T217	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	7		T26	4		T31	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T234	17		T178	9		T20	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	9		T156	2		T166	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T71	12		T72	14		T211	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	8		T221	10		T211	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	10		T230	7		T265	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T54	33		T199	34		T247	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T60	8		T189	9		T110	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T164	9		T212	6		T162	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T189	12		T212	16		T211	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T41	13		T224	9		T33	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	1		T62	15		T173	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T164	4		T166	4		T38	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T50	6		T31	13		T266	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	12		T189	9		T213	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T51	4		T110	11		T264	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T61	4		T221	13		T167	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T61	13		T161	4		T31	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T104	18		T255	15		T256	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T156	11		T212	17		T296	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T3	2		T61	6		T248	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T258	11		T245	8		T186	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T61	1		T221	7		T167	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T53	2		T253	8		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T61	1		T85	1		T48	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T263	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	1		T9	1		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T11	3		T219	1		T72	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	1		T72	2		T166	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T71	12		T72	13		T223	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	5		T219	11		T156	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	10		T36	1		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T2	25		T8	1		T54	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T49	1		T60	9		T71	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T85	9		T164	10		T170	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T189	2		T212	1		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	2		T49	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	2		T62	13		T173	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T41	15		T47	1		T159	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	11		T159	13		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	13		T213	10		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T160	1		T167	4		T264	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	4		T49	1		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T7	16		T61	1		T37	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T61	4		T221	13		T167	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T53	1		T253	7		T250	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T61	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	2		T9	7		T26	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T234	17		T258	11		T245	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	9		T166	9		T31	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T71	12		T72	14		T32	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	8		T156	2		T162	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	10		T211	11		T230	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T54	33		T199	34		T247	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T60	8		T110	13		T175	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T164	9		T38	4		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T189	21		T212	16		T211	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T212	6		T224	9		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	1		T62	15		T173	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T41	13		T164	4		T166	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T50	6		T31	13		T266	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	12		T213	2		T161	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T264	11		T209	13		T269	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T189	9		T134	2		T112	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T61	13		T156	11		T212	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19