Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23131

1

T2

25

T5

141

T6

18

auto[ADC_CTRL_FILTER_COND_OUT]

3271

1

T1

13

T3

13

T7

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20841

1

T3

3

T5

141

T6

18

auto[1]

5561

1

T1

13

T2

25

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T121	6		T215	11		T333	8
values[0]	123	1			T48	5		T215	14		T182	18
values[1]	750	1			T1	13		T61	5		T219	11
values[2]	703	1			T7	11		T9	25		T11	3
values[3]	550	1			T3	3		T71	24		T156	7
values[4]	550	1			T49	1		T47	1		T220	1
values[5]	523	1			T3	10		T49	1		T219	1
values[6]	655	1			T72	27		T166	1		T160	1
values[7]	772	1			T13	3		T37	6		T161	7
values[8]	513	1			T9	8		T61	14		T85	1
values[9]	3358	1			T2	25		T7	20		T8	1
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	925	1			T1	13		T9	25		T11	3
values[1]	748	1			T7	11		T12	20		T62	28
values[2]	643	1			T3	3		T156	7		T159	11
values[3]	424	1			T49	2		T189	10		T72	2
values[4]	591	1			T3	10		T219	1		T47	1
values[5]	687	1			T37	6		T72	27		T160	1
values[6]	2864	1			T2	25		T8	1		T13	3
values[7]	550	1			T9	8		T61	14		T43	1
values[8]	948	1			T7	16		T11	2		T49	1
values[9]	103	1			T7	4		T85	9		T71	2
minimum	17919	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T9	13		T11	2		T60	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	9		T47	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	11		T62	16		T189	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	1		T71	13		T173	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T159	1		T166	10		T211	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	3		T156	3		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T49	1		T189	10		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T49	1		T72	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T219	1		T47	1		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	10		T220	1		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T72	15		T160	1		T212	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T37	1		T212	18		T161	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1568	1			T2	2		T8	1		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T85	1		T38	14		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T61	14		T189	13		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	8		T43	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T49	1		T56	1		T61	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T7	1		T11	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T7	1		T71	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T85	1		T334	1		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17762	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T31	7		T250	1		T268	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T9	12		T11	1		T60	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	4		T47	11		T159	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	9		T62	12		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	10		T71	11		T173	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T159	10		T166	6		T26	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T156	4		T222	2		T266	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T223	4		T161	2		T229	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T72	1		T110	10		T330	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T166	4		T174	15		T176	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	6		T127	16		T176	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T72	12		T122	1		T168	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T37	5		T121	5		T168	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T2	23		T13	1		T57	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T38	11		T122	1		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T72	1		T110	14		T289	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T164	9		T224	9		T29	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T38	9		T132	3		T53	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	15		T11	1		T159	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T7	3		T71	1		T121	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T85	8		T334	9		T335	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	2		T13	3		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T268	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T215	1		T333	8		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T121	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T215	1		T182	6		T18	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T48	2		T215	1		T245	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T61	5		T219	1		T164	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	9		T47	1		T173	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	13		T11	2		T12	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	1		T159	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T159	1		T51	7		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	3		T71	13		T156	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T49	1		T47	1		T166	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T220	1		T72	1		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T219	1		T189	10		T166	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	10		T49	1		T15	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T72	15		T166	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T212	18		T211	9		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	2		T162	12		T221	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T37	1		T161	7		T38	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T61	14		T41	14		T189	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	8		T85	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1574	1			T2	2		T7	1		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	445	1			T7	1		T11	1		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T215	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T121	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T182	12		T18	1		T193	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T48	3		T215	12		T336	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T219	10		T164	2		T213	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	4		T47	11		T173	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	12		T11	1		T12	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	10		T159	5		T170	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T159	10		T51	8		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T71	11		T156	4		T222	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T166	6		T223	4		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T72	1		T230	17		T330	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T166	4		T175	1		T296	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	6		T127	16		T110	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T72	12		T122	1		T168	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T121	5		T215	1		T182	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	1		T162	14		T221	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T37	5		T38	11		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T41	14		T72	1		T167	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T32	6		T244	9		T229	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T2	23		T7	3		T57	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T7	15		T11	1		T85	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T9	13		T11	3		T60	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	5		T47	12		T159	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	10		T62	13		T189	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	11		T71	12		T173	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T159	11		T166	7		T211	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T156	5		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T49	1		T189	1		T223	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T49	1		T72	2		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T219	1		T47	1		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	1		T220	1		T15	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T72	13		T160	1		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T37	6		T212	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T2	25		T8	1		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T85	1		T38	12		T122	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T61	1		T189	1		T72	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	1		T43	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T49	1		T56	1		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T7	16		T11	2		T159	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T7	4		T71	2		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T85	9		T334	10		T335	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17883	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T31	1		T250	1		T268	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T9	12		T60	8		T61	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T1	8		T29	9		T51	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	10		T62	15		T189	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T71	12		T173	18		T162	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T166	9		T211	11		T26	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T3	2		T156	2		T232	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T189	9		T161	4		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T110	11		T214	12		T108	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T166	4		T212	6		T174	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	9		T15	4		T127	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T72	14		T212	16		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T212	17		T161	6		T211	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T13	1		T54	33		T41	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T38	13		T214	14		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T61	13		T189	12		T110	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	7		T164	9		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T61	6		T38	16		T53	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T221	9		T50	6		T31	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T337	1		T338	10		T339	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T340	17		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T341	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T31	6		T268	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T215	11		T333	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T121	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T215	1		T182	13		T18	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T48	5		T215	13		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T61	1		T219	11		T164	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	5		T47	12		T173	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	13		T11	3		T12	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	11		T159	6		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T159	11		T51	13		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	1		T71	12		T156	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	1		T47	1		T166	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T220	1		T72	2		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T219	1		T189	1		T166	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	1		T49	1		T15	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T72	13		T166	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T212	1		T211	1		T121	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	2		T162	15		T221	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T37	6		T161	1		T38	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T61	1		T41	15		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	1		T85	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T2	25		T7	4		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T7	16		T11	2		T85	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T333	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T182	5		T18	2		T193	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T245	8		T268	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T61	4		T164	4		T213	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	8		T173	18		T29	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	12		T12	10		T60	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T162	6		T134	5		T174	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T51	2		T248	12		T253	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	2		T71	12		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T166	9		T161	4		T211	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T108	8		T230	7		T242	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T189	9		T166	4		T175	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	9		T15	4		T127	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T72	14		T212	22		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T212	17		T211	8		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	1		T162	11		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T161	6		T38	13		T214	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T61	13		T41	13		T189	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	7		T32	2		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T54	33		T61	6		T199	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T164	9		T224	9		T221	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19