Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23222

1

T1

13

T2

25

T5

141

auto[ADC_CTRL_FILTER_COND_OUT]

3180

1

T3

13

T7

16

T9

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20891

1

T3

3

T5

141

T6

18

auto[1]

5511

1

T1

13

T2

25

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	203	1			T7	4		T71	2		T159	13
values[0]	71	1			T48	5		T245	9		T193	19
values[1]	767	1			T1	13		T11	3		T61	5
values[2]	723	1			T7	11		T9	25		T12	20
values[3]	614	1			T3	3		T71	24		T156	7
values[4]	508	1			T49	2		T72	2		T166	16
values[5]	457	1			T3	10		T219	1		T47	1
values[6]	690	1			T72	27		T166	1		T160	1
values[7]	797	1			T13	3		T37	6		T161	7
values[8]	490	1			T9	8		T61	14		T85	1
values[9]	3202	1			T2	25		T7	16		T8	1
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	739	1			T9	25		T11	3		T60	17
values[1]	696	1			T7	11		T12	20		T62	28
values[2]	653	1			T3	3		T156	7		T159	11
values[3]	466	1			T49	2		T189	10		T72	2
values[4]	576	1			T3	10		T219	1		T47	1
values[5]	649	1			T37	6		T72	27		T160	1
values[6]	2888	1			T2	25		T8	1		T13	3
values[7]	588	1			T9	8		T61	14		T43	1
values[8]	961	1			T7	16		T11	2		T49	1
values[9]	48	1			T7	4		T121	2		T53	1
minimum	18138	1			T1	13		T5	141		T6	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T9	13		T11	2		T60	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T173	19		T159	1		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	1		T12	11		T62	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T71	13		T170	1		T162	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T159	1		T220	1		T166	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	3		T156	3		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T49	1		T189	10		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T49	1		T72	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T219	1		T47	1		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	10		T220	1		T15	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T72	15		T160	1		T212	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T37	1		T212	18		T161	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T2	2		T8	1		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T85	1		T38	14		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T61	14		T189	13		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T9	8		T43	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T49	1		T56	1		T61	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T7	1		T11	1		T85	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T7	1		T121	1		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T280	10		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17828	1			T1	9		T5	141		T6	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T47	1		T48	2		T29	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T9	12		T11	1		T60	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T173	17		T159	5		T51	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	10		T12	9		T62	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T71	11		T170	9		T162	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T159	10		T166	6		T26	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T156	4		T266	1		T230	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T223	4		T161	2		T229	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T72	1		T110	10		T230	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T166	4		T174	15		T176	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T15	6		T127	16		T176	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T72	12		T122	1		T168	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T37	5		T121	5		T168	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T2	23		T13	1		T57	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T38	11		T122	1		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T72	1		T110	14		T260	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T164	9		T224	9		T29	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T71	1		T38	9		T132	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T7	15		T11	1		T85	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T7	3		T121	1		T337	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T280	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	4		T11	2		T13	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T47	11		T48	3		T29	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T7	1		T71	1		T121	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T159	1		T121	1		T334	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T193	10		T282	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T48	2		T245	9		T336	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T1	9		T11	2		T61	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T47	1		T173	19		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	1		T9	13		T12	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T159	1		T170	1		T162	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T159	1		T220	1		T26	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	3		T71	13		T156	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T49	1		T166	10		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T49	1		T72	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T219	1		T47	1		T189	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	10		T220	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T72	15		T166	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T212	18		T211	9		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	2		T162	12		T221	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T37	1		T161	7		T38	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T61	14		T41	14		T189	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	8		T85	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T2	2		T8	1		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T7	1		T11	1		T85	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T7	3		T71	1		T121	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T159	12		T121	5		T334	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T193	9		T282	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T48	3		T336	13		T268	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	4		T11	1		T219	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T47	11		T173	17		T29	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	10		T9	12		T12	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T159	5		T170	9		T162	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T159	10		T26	5		T51	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T71	11		T156	4		T174	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T166	6		T223	4		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T72	1		T230	17		T330	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T166	4		T175	1		T296	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	6		T127	16		T110	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T72	12		T122	1		T168	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T121	5		T168	1		T176	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	1		T162	14		T221	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T37	5		T38	11		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T41	14		T72	1		T167	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T244	9		T229	9		T300	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T2	23		T57	13		T58	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T7	15		T11	1		T85	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T9	13		T11	3		T60	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T173	18		T159	6		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	11		T12	10		T62	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T71	12		T170	10		T162	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T159	11		T220	1		T166	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	1		T156	5		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T49	1		T189	1		T223	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T49	1		T72	2		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T219	1		T47	1		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	1		T220	1		T15	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T72	13		T160	1		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T37	6		T212	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T2	25		T8	1		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T85	1		T38	12		T122	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T61	1		T189	1		T72	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	1		T43	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T49	1		T56	1		T61	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T7	16		T11	2		T85	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T7	4		T121	2		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T280	11		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17927	1			T1	5		T5	141		T6	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T47	12		T48	5		T29	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	12		T60	8		T61	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T173	18		T51	4		T234	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	10		T62	15		T189	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T71	12		T162	6		T134	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T166	9		T211	11		T26	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	2		T156	2		T232	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T189	9		T161	4		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T110	11		T214	12		T108	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T166	4		T212	6		T174	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	9		T15	4		T127	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T72	14		T212	16		T168	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T212	17		T161	6		T211	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T13	1		T54	33		T41	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T38	13		T214	14		T269	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T61	13		T189	12		T110	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	7		T164	9		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T61	6		T38	16		T175	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T221	9		T50	6		T31	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T337	1		T338	10		T339	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T280	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T1	8		T221	13		T242	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T29	9		T31	6		T283	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T7	4		T71	2		T121	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T159	13		T121	6		T334	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T193	10		T282	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T48	5		T245	1		T336	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T1	5		T11	3		T61	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T47	12		T173	18		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	11		T9	13		T12	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T159	6		T170	10		T162	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T159	11		T220	1		T26	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T71	12		T156	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	1		T166	7		T223	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T49	1		T72	2		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T219	1		T47	1		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T220	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T72	13		T166	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T212	1		T211	1		T121	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	2		T162	15		T221	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T37	6		T161	1		T38	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T61	1		T41	15		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T9	1		T85	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T2	25		T8	1		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T7	16		T11	2		T85	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T246	1		T178	9		T342	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T303	8		T343	18		T326	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T193	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T245	8		T268	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	8		T61	4		T164	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T173	18		T29	9		T31	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	12		T12	10		T60	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T162	6		T134	5		T31	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T26	4		T51	2		T248	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	2		T71	12		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T166	9		T161	4		T211	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T108	8		T230	7		T344	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T189	9		T166	4		T212	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T3	9		T15	4		T127	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T72	14		T212	16		T168	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T212	17		T211	8		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	1		T162	11		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T161	6		T38	13		T214	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T61	13		T41	13		T189	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	7		T244	11		T233	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T54	33		T61	6		T199	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T164	9		T224	9		T221	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19