Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T85	9		T238	1		T170	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	3		T12	10		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T49	1		T36	1		T164	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	2		T72	13		T164	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	1		T189	1		T156	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	1		T49	1		T41	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T189	1		T224	10		T133	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	11		T220	1		T223	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	1		T7	16		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T61	2		T71	14		T238	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T189	1		T72	2		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T173	18		T159	11		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T2	25		T8	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	5		T9	13		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T72	2		T127	17		T225	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T37	6		T159	13		T221	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T166	7		T212	1		T167	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	4		T220	1		T166	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T61	1		T85	1		T174	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T162	15		T231	3		T185	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17883	1			T5	141		T6	18		T10	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T162	6		T134	5		T174	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	10		T62	15		T156	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T164	4		T213	2		T161	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	1		T72	14		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T3	2		T189	9		T156	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	7		T41	13		T161	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T189	12		T224	9		T32	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T214	12		T242	15		T245	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	9		T51	2		T246	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T61	10		T71	12		T15	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T189	9		T31	6		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T173	18		T212	17		T211	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T54	33		T199	34		T247	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T1	8		T9	12		T60	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T127	14		T244	11		T248	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T221	13		T232	7		T249	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T166	9		T212	16		T167	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T166	4		T122	17		T168	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T61	13		T250	8		T251	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T162	11		T227	11		T252	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T61	1		T235	1		T241	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T236	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T242	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T176	15		T208	1		T237	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T85	9		T238	1		T132	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	3		T12	10		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T49	1		T36	1		T170	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	2		T72	13		T164	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	1		T189	1		T164	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	1		T41	15		T223	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T156	14		T224	10		T38	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	11		T49	1		T220	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T3	1		T7	16		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T61	2		T71	12		T173	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	2		T72	2		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T71	2		T159	11		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T56	1		T189	1		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	13		T60	9		T219	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T2	25		T8	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	5		T159	19		T132	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T85	1		T166	7		T167	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	4		T37	6		T220	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T61	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T236	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T242	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T134	5		T178	5		T253	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	10		T62	15		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T213	2		T161	6		T162	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	1		T72	14		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T3	2		T189	9		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	7		T41	13		T161	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T156	11		T224	9		T38	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	14		T214	12		T254	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	9		T189	12		T51	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T61	10		T71	12		T173	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T53	1		T214	14		T108	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T212	17		T50	6		T174	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T189	9		T212	6		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	12		T60	8		T221	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T54	33		T199	34		T247	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T1	8		T29	9		T249	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T166	9		T167	4		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T166	4		T162	11		T122	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19