Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23197

1

T2

25

T3

10

T5

141

auto[ADC_CTRL_FILTER_COND_OUT]

3205

1

T1

13

T3

3

T7

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20927

1

T3

13

T5

141

T6

18

auto[1]

5475

1

T1

13

T2

25

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	158	1			T167	8		T122	34		T174	2
values[0]	25	1			T176	15		T208	1		T237	9
values[1]	534	1			T11	3		T12	20		T219	1
values[2]	786	1			T49	1		T36	1		T72	27
values[3]	535	1			T3	3		T9	8		T13	3
values[4]	766	1			T7	11		T49	1		T156	25
values[5]	771	1			T3	10		T7	16		T61	12
values[6]	653	1			T11	2		T71	2		T159	11
values[7]	770	1			T9	25		T56	1		T60	17
values[8]	2767	1			T1	13		T2	25		T8	1
values[9]	757	1			T7	4		T61	14		T85	1
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	626	1			T11	3		T12	20		T219	1
values[1]	642	1			T13	3		T49	1		T36	1
values[2]	621	1			T3	3		T9	8		T49	1
values[3]	724	1			T7	11		T220	1		T223	5
values[4]	696	1			T3	10		T7	16		T11	2
values[5]	793	1			T189	10		T159	11		T72	2
values[6]	2875	1			T1	13		T2	25		T8	1
values[7]	541	1			T37	6		T159	13		T72	2
values[8]	631	1			T7	4		T220	1		T166	9
values[9]	153	1			T61	14		T85	1		T166	16
minimum	18100	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T170	1		T162	7		T134	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	2		T12	11		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T49	1		T36	1		T164	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	2		T72	15		T164	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T189	10		T156	12		T213	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	3		T9	8		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T220	1		T224	10		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	1		T223	1		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	10		T7	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T61	12		T43	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T189	10		T72	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T159	1		T212	18		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T2	2		T8	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	9		T9	13		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T72	1		T212	17		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T37	1		T159	1		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T167	5		T53	1		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	1		T220	1		T166	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T61	14		T85	1		T166	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T231	2		T240	1		T194	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17800	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T156	3		T221	10		T121	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T170	9		T162	8		T168	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T11	1		T12	9		T62	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T164	2		T26	5		T110	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	1		T72	12		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T156	13		T213	9		T38	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T41	14		T161	2		T29	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T224	9		T133	9		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	10		T223	4		T52	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	15		T11	1		T167	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	11		T71	12		T173	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T72	1		T120	9		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T159	10		T121	1		T174	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T2	23		T57	13		T58	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	4		T9	12		T60	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T72	1		T167	10		T127	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T37	5		T159	12		T121	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T167	3		T239	2		T226	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T7	3		T166	4		T162	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T166	6		T174	1		T201	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T231	1		T240	13		T206	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	2		T13	3		T85	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T156	4		T221	14		T121	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T167	5		T174	1		T17	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T122	18		T270	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T176	1		T208	1		T237	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T85	1		T238	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	2		T12	11		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T49	1		T36	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T72	15		T164	10		T38	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T189	10		T164	5		T213	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	3		T9	8		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T156	12		T220	1		T224	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T49	1		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	10		T7	1		T189	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T61	12		T43	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	1		T72	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T71	1		T159	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T56	1		T189	10		T212	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	13		T60	9		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T2	2		T8	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	9		T159	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T61	14		T85	1		T166	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	1		T37	1		T220	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T167	3		T174	1		T200	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T122	16		T271	2		T240	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T176	14		T237	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T85	8		T132	3		T168	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	1		T12	9		T62	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T170	9		T162	8		T26	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T72	12		T164	9		T38	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T164	2		T213	9		T230	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	1		T41	14		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T156	13		T224	9		T38	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	10		T223	4		T29	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	15		T167	3		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T47	11		T71	11		T173	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T11	1		T72	1		T120	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T71	1		T159	10		T121	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T221	9		T225	9		T243	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	12		T60	8		T219	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T2	23		T57	13		T58	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	4		T159	12		T132	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T166	6		T244	9		T239	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T7	3		T37	5		T166	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T170	10		T162	9		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	3		T12	10		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	1		T36	1		T164	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	2		T72	13		T164	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T189	1		T156	14		T213	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T9	1		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T220	1		T224	10		T133	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	11		T223	5		T52	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	1		T7	16		T11	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T61	2		T43	1		T47	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T189	1		T72	2		T120	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T159	11		T212	1		T121	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T2	25		T8	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	5		T9	13		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T72	2		T212	1		T167	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T37	6		T159	13		T121	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T167	4		T53	1		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	4		T220	1		T166	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T61	1		T85	1		T166	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T231	3		T240	14		T194	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17934	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T156	5		T221	15		T121	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T162	6		T134	5		T174	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	10		T62	15		T38	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T164	4		T161	6		T26	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T72	14		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T189	9		T156	11		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	2		T9	7		T41	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T224	9		T32	2		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T214	12		T242	15		T245	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	9		T189	12		T15	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T61	10		T71	12		T173	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T189	9		T53	1		T108	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T212	17		T112	2		T174	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T54	33		T199	34		T247	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	8		T9	12		T60	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T212	16		T127	14		T244	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T232	7		T249	2		T237	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T167	4		T250	8		T226	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T166	4		T162	11		T122	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T61	13		T166	9		T201	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T227	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T242	7		T272	11		T263	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T156	2		T221	9		T230	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T167	4		T174	2		T17	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T122	17		T270	1		T271	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T176	15		T208	1		T237	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T85	9		T238	1		T132	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	3		T12	10		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T49	1		T36	1		T170	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T72	13		T164	10		T38	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T189	1		T164	3		T213	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	1		T9	1		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T156	14		T220	1		T224	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	11		T49	1		T223	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	1		T7	16		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T61	2		T43	1		T47	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	2		T72	2		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T71	2		T159	11		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T56	1		T189	1		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	13		T60	9		T219	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T2	25		T8	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	5		T159	13		T132	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T61	1		T85	1		T166	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	4		T37	6		T220	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T167	4		T273	4		T274	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T122	17		T227	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T134	5		T253	1		T242	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	10		T62	15		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T161	6		T162	6		T26	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T72	14		T164	9		T38	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T189	9		T164	4		T213	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	2		T9	7		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T156	11		T224	9		T38	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T29	14		T214	12		T242	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	9		T189	12		T15	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T61	10		T71	12		T173	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T53	1		T108	8		T178	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T212	17		T174	10		T234	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T189	9		T212	6		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	12		T60	8		T221	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T54	33		T199	34		T247	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T1	8		T29	9		T249	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T61	13		T166	9		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T166	4		T162	11		T168	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19