Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23537

1

T1

13

T2

25

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

2865

1

T3

10

T9

8

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20959

1

T3

10

T5

141

T6

18

auto[1]

5443

1

T1

13

T2

25

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	67	1			T208	1		T193	19		T261	24
values[0]	37	1			T124	1		T275	1		T276	3
values[1]	584	1			T3	10		T159	11		T72	27
values[2]	562	1			T61	7		T85	9		T189	10
values[3]	663	1			T7	4		T9	8		T85	1
values[4]	670	1			T7	16		T9	25		T12	20
values[5]	2782	1			T2	25		T8	1		T54	36
values[6]	596	1			T3	3		T7	11		T11	2
values[7]	585	1			T1	13		T36	1		T156	7
values[8]	736	1			T11	3		T49	1		T56	1
values[9]	1240	1			T49	1		T61	19		T219	11
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	759	1			T3	10		T85	9		T159	11
values[1]	744	1			T7	4		T61	7		T85	1
values[2]	540	1			T9	33		T49	1		T43	1
values[3]	2791	1			T2	25		T7	16		T8	1
values[4]	591	1			T47	1		T189	10		T48	5
values[5]	652	1			T3	3		T7	11		T11	2
values[6]	512	1			T1	13		T36	1		T156	7
values[7]	746	1			T11	3		T49	1		T56	1
values[8]	988	1			T49	1		T61	19		T219	11
values[9]	199	1			T50	15		T134	3		T115	1
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T72	15		T170	1		T26	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	10		T85	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	1		T85	1		T189	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T61	7		T62	16		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	13		T47	1		T161	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	8		T49	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T2	2		T7	1		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	11		T219	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T189	10		T164	5		T166	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T47	1		T48	2		T211	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	3		T7	1		T162	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	1		T13	2		T72	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T1	9		T156	3		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T36	1		T160	1		T161	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	2		T56	1		T71	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T49	1		T41	14		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T49	1		T61	19		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T219	1		T224	10		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T226	18		T242	8		T278	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T50	11		T134	3		T115	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T72	12		T170	9		T26	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T85	8		T159	10		T164	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	3		T71	11		T175	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T62	12		T159	5		T38	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T9	12		T47	11		T167	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T29	12		T51	8		T174	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T2	23		T7	15		T57	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	9		T159	12		T162	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T164	2		T166	6		T38	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T48	3		T215	12		T182	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	10		T162	14		T120	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T11	1		T13	1		T72	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T1	4		T156	4		T52	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T161	2		T221	6		T32	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	1		T71	1		T223	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T41	14		T221	14		T121	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T37	5		T156	13		T173	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T219	10		T224	9		T181	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T226	17		T278	15		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T50	4		T279	13		T20	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T193	10		T280	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T208	1		T261	9		T281	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T124	1		T256	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T275	1		T276	3		T282	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T72	15		T26	5		T33	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	10		T159	1		T164	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T189	10		T220	2		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T61	7		T85	1		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	1		T85	1		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	8		T62	16		T189	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	1		T9	13		T60	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	11		T49	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1568	1			T2	2		T8	1		T54	36
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T47	1		T48	2		T238	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	3		T7	1		T164	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T11	1		T13	2		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	9		T156	3		T211	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T36	1		T160	1		T221	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	2		T56	1		T71	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T49	1		T160	1		T161	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T49	1		T61	19		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T219	1		T41	14		T224	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T193	9		T280	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T261	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T256	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T282	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T72	12		T26	5		T33	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T159	10		T164	9		T213	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T170	9		T114	5		T176	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T85	8		T159	5		T167	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	3		T47	11		T71	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T62	12		T159	12		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	15		T9	12		T60	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	9		T162	8		T127	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T2	23		T57	13		T58	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T48	3		T229	4		T215	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	10		T164	2		T162	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T11	1		T13	1		T72	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	4		T156	4		T120	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T221	6		T51	1		T111	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	1		T71	1		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T161	2		T221	14		T32	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T37	5		T156	13		T173	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T219	10		T41	14		T224	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T72	13		T170	10		T26	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	1		T85	9		T159	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	4		T85	1		T189	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T61	1		T62	13		T159	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	13		T47	12		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	1		T49	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T2	25		T7	16		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	10		T219	1		T159	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T189	1		T164	3		T166	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T47	1		T48	5		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	1		T7	11		T162	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T11	2		T13	2		T72	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	5		T156	5		T52	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T36	1		T160	1		T161	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	3		T56	1		T71	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T49	1		T41	15		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T49	1		T61	2		T37	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T219	11		T224	10		T277	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T226	19		T242	1		T278	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T50	9		T134	1		T115	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T72	14		T26	4		T33	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	9		T164	9		T213	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T189	9		T71	12		T175	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T61	6		T62	15		T38	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	12		T161	6		T29	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	7		T189	12		T29	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1147	1			T54	33		T60	8		T199	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	10		T212	17		T162	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T189	9		T164	4		T166	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T211	11		T182	8		T254	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	2		T162	11		T134	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T13	1		T250	8		T242	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T1	8		T156	2		T283	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T161	4		T221	13		T211	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T212	6		T211	7		T244	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T41	13		T221	9		T108	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T61	17		T156	11		T173	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T224	9		T174	10		T175	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T226	16		T242	7		T278	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T50	6		T134	2		T20	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T193	10		T280	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T208	1		T261	16		T281	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T124	1		T256	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T275	1		T276	1		T282	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T72	13		T26	6		T33	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	1		T159	11		T164	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T189	1		T220	2		T170	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T61	1		T85	9		T159	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	4		T85	1		T47	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T62	13		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	16		T9	13		T60	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	10		T49	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T2	25		T8	1		T54	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T47	1		T48	5		T238	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T7	11		T164	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T11	2		T13	2		T72	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	5		T156	5		T211	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T36	1		T160	1		T221	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	3		T56	1		T71	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T49	1		T160	1		T161	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T49	1		T61	2		T37	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T219	11		T41	15		T224	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T193	9		T280	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T261	8		T281	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T256	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T276	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T72	14		T26	4		T33	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	9		T164	9		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T189	9		T284	6		T264	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T61	6		T214	14		T246	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T71	12		T161	6		T29	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	7		T62	15		T189	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	12		T60	8		T168	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	10		T162	6		T31	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T54	33		T189	9		T199	34
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T212	17		T211	11		T285	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	2		T164	4		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T13	1		T250	8		T286	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	8		T156	2		T211	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T221	13		T211	8		T51	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T266	9		T248	12		T260	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T161	4		T221	9		T31	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T61	17		T156	11		T173	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T41	13		T224	9		T50	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19