Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20833

1

T1

13

T5

141

T6

18

auto[ADC_CTRL_FILTER_COND_OUT]

5569

1

T2

25

T3

13

T7

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20584

1

T3

3

T5

141

T6

18

auto[1]

5818

1

T1

13

T2

25

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T253	15		T187	20		-	-
values[0]	122	1			T238	1		T127	31		T258	3
values[1]	721	1			T13	3		T156	7		T160	1
values[2]	755	1			T9	33		T49	1		T71	24
values[3]	609	1			T37	6		T189	23		T162	15
values[4]	612	1			T49	1		T60	17		T47	13
values[5]	558	1			T7	16		T11	3		T219	11
values[6]	617	1			T7	4		T11	2		T49	1
values[7]	549	1			T56	1		T41	28		T173	36
values[8]	564	1			T12	20		T219	1		T85	1
values[9]	3380	1			T1	13		T2	25		T3	13
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	953	1			T9	25		T71	24		T156	7
values[1]	2913	1			T2	25		T8	1		T9	8
values[2]	538	1			T60	17		T37	6		T189	23
values[3]	634	1			T7	16		T49	1		T219	11
values[4]	650	1			T11	3		T61	5		T85	9
values[5]	629	1			T7	4		T11	2		T49	1
values[6]	616	1			T12	20		T56	1		T219	1
values[7]	578	1			T1	13		T7	11		T43	1
values[8]	728	1			T3	13		T61	7		T36	1
values[9]	228	1			T61	14		T62	28		T212	7
minimum	17935	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T156	3		T238	1		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	13		T71	13		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T49	1		T161	7		T211	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1614	1			T2	2		T8	1		T9	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	1		T189	23		T162	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T60	9		T166	1		T277	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T47	1		T159	1		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	1		T49	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T85	1		T212	18		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	2		T61	5		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T49	1		T189	10		T161	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	1		T11	1		T41	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T219	1		T85	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	11		T56	1		T213	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	9		T7	1		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T43	1		T72	15		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T164	5		T168	11		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	13		T61	7		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T212	7		T38	1		T50	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T61	14		T62	16		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17776	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T288	1		T227	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T156	4		T223	4		T121	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	12		T71	11		T170	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T26	5		T51	1		T111	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1034	1			T2	23		T13	1		T57	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T37	5		T162	8		T132	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T60	8		T181	14		T239	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T47	11		T159	5		T167	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	15		T219	10		T71	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T85	8		T133	9		T289	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	1		T159	12		T164	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T161	2		T167	3		T110	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	3		T11	1		T41	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T166	4		T121	5		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	9		T213	9		T132	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	4		T7	10		T72	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T72	12		T38	4		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T164	2		T168	13		T243	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T159	10		T221	6		T15	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T50	4		T168	11		T196	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T62	12		T266	7		T286	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	2		T13	3		T85	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T253	8		T187	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T238	1		T290	9		T291	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T127	15		T258	3		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T156	3		T223	1		T161	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	2		T160	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	1		T211	9		T26	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T9	21		T71	13		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T37	1		T189	23		T162	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T31	14		T277	1		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	1		T159	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T49	1		T60	9		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T167	1		T211	12		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	1		T11	2		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	1		T85	1		T189	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T11	1		T61	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T220	1		T50	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T56	1		T41	14		T173	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T219	1		T85	1		T166	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	11		T72	15		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	9		T7	1		T72	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1766	1			T2	2		T3	13		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T253	7		T187	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T290	6		T263	13		T293	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T127	16		T292	11		T294	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T156	4		T223	4		T224	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	1		T170	9		T162	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T26	5		T121	5		T122	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	12		T71	11		T72	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T37	5		T162	8		T51	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T248	7		T239	6		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T47	11		T159	5		T132	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T60	8		T71	1		T38	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T167	3		T182	12		T269	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	15		T11	1		T219	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T85	8		T161	2		T167	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	3		T11	1		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T121	5		T110	10		T174	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T41	14		T173	17		T213	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T166	10		T120	9		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	9		T72	12		T167	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	4		T7	10		T72	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1133	1			T2	23		T57	13		T58	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T156	5		T238	1		T223	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	13		T71	12		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T49	1		T161	1		T211	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1376	1			T2	25		T8	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T37	6		T189	2		T162	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T60	9		T166	1		T277	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T47	12		T159	6		T167	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	16		T49	1		T219	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T85	9		T212	1		T133	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	3		T61	1		T159	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	1		T189	1		T161	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	4		T11	2		T41	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T219	1		T85	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	10		T56	1		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	5		T7	11		T72	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T43	1		T72	13		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T164	3		T168	14		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	2		T61	1		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T212	1		T38	1		T50	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T61	1		T62	13		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17903	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T288	1		T227	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T156	2		T134	5		T122	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	12		T71	12		T212	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T161	6		T211	8		T26	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1272	1			T9	7		T13	1		T54	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T189	21		T162	6		T209	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T60	8		T104	18		T250	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T134	2		T29	9		T33	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T38	13		T221	9		T53	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T212	17		T214	14		T233	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T61	4		T164	9		T221	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T189	9		T161	4		T167	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T41	13		T156	11		T173	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T166	4		T178	12		T295	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	10		T213	2		T211	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T1	8		T166	9		T232	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T72	14		T38	4		T29	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T164	4		T168	10		T243	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	11		T61	6		T221	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T212	6		T50	6		T168	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T61	13		T62	15		T234	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T224	9		T182	8		T18	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T227	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T253	8		T187	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T238	1		T290	7		T291	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T127	17		T258	1		T292	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T156	5		T223	5		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	2		T160	1		T170	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T49	1		T211	1		T26	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	14		T71	12		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	6		T189	2		T162	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T31	1		T277	1		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T47	12		T159	6		T132	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T49	1		T60	9		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T167	4		T211	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	16		T11	3		T219	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T49	1		T85	9		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	4		T11	2		T61	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T220	1		T50	1		T121	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T56	1		T41	15		T173	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T219	1		T85	1		T166	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	10		T72	13		T167	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T1	5		T7	11		T72	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1508	1			T2	25		T3	2		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T253	7		T187	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T290	8		T263	18		T293	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T127	14		T258	2		T294	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T156	2		T161	6		T224	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	1		T162	11		T38	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T211	8		T26	4		T122	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	19		T71	12		T212	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T189	21		T162	6		T51	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T31	13		T104	18		T248	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T29	9		T33	3		T214	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T60	8		T38	13		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T211	11		T134	2		T214	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T164	9		T108	12		T248	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T189	9		T212	17		T161	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T61	4		T156	11		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T110	11		T174	10		T178	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T41	13		T173	18		T213	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T166	13		T232	7		T178	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	10		T72	14		T175	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	8		T164	4		T212	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1391	1			T3	11		T54	33		T61	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19