Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22794

1

T2

25

T3

13

T5

141

auto[ADC_CTRL_FILTER_COND_OUT]

3608

1

T1

13

T7

4

T11

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20310

1

T1

13

T3

3

T5

138

auto[1]

6092

1

T2

25

T3

10

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	738	1			T5	3		T11	1		T13	8
values[0]	20	1			T232	9		T296	10		T297	1
values[1]	541	1			T12	20		T49	1		T60	17
values[2]	2638	1			T2	25		T8	1		T54	36
values[3]	784	1			T7	11		T9	25		T11	2
values[4]	645	1			T49	2		T61	5		T85	9
values[5]	514	1			T13	3		T156	7		T159	13
values[6]	680	1			T3	3		T7	16		T9	8
values[7]	625	1			T1	13		T61	7		T85	1
values[8]	813	1			T7	4		T56	1		T62	28
values[9]	978	1			T3	10		T11	3		T43	1
minimum	17426	1			T5	138		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	463	1			T60	17		T61	14		T219	11
values[1]	2720	1			T2	25		T8	1		T9	25
values[2]	861	1			T7	11		T11	2		T49	1
values[3]	443	1			T49	1		T61	5		T85	9
values[4]	542	1			T13	3		T238	1		T223	5
values[5]	724	1			T3	3		T7	16		T9	8
values[6]	745	1			T1	13		T56	1		T61	7
values[7]	810	1			T7	4		T62	28		T43	1
values[8]	857	1			T11	3		T160	1		T161	7
values[9]	167	1			T3	10		T221	20		T167	8
minimum	18070	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T219	1		T212	17		T53	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T60	9		T61	14		T71	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T2	2		T8	1		T9	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T41	14		T189	10		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	1		T11	1		T189	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T49	1		T38	17		T211	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T85	1		T47	1		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	1		T61	5		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T223	1		T132	1		T181	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	2		T238	1		T211	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	3		T7	1		T9	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T31	14		T122	1		T298	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T56	1		T61	7		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	9		T219	1		T85	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T43	1		T220	1		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	1		T62	16		T71	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T160	1		T224	10		T38	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T11	2		T161	5		T221	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T3	10		T167	5		T112	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T221	11		T260	7		T299	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17814	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T12	11		T49	1		T164	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T219	10		T53	1		T300	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T60	8		T71	1		T122	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T2	23		T9	12		T57	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T41	14		T162	8		T29	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	10		T11	1		T159	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T38	9		T15	6		T29	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T85	8		T117	10		T175	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T47	11		T156	4		T159	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T223	4		T132	5		T181	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	1		T133	9		T120	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	15		T37	5		T170	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T122	1		T176	14		T177	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T221	6		T132	3		T127	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	4		T48	3		T72	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T72	1		T166	10		T244	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	3		T62	12		T71	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T224	9		T38	4		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T161	2		T221	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T167	3		T301	4		T302	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T221	9		T260	6		T299	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	2		T13	3		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T12	9		T164	9		T38	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	533	1			T5	3		T11	1		T13	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T221	11		T260	7		T230	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T232	9		T296	5		T297	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T219	1		T238	1		T212	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	11		T49	1		T60	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T2	2		T8	1		T54	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T189	10		T220	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	1		T9	13		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T41	14		T162	7		T38	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T85	1		T47	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T49	2		T61	5		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T223	1		T132	1		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	2		T156	3		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	3		T7	1		T9	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T219	1		T31	14		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T61	7		T36	1		T189	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	9		T85	1		T173	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T56	1		T220	1		T72	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	1		T62	16		T71	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	10		T43	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T11	2		T161	5		T221	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17299	1			T5	138		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T224	9		T167	3		T121	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T221	9		T260	6		T230	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T296	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T219	10		T53	1		T300	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	9		T60	8		T71	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T2	23		T57	13		T58	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T29	10		T237	2		T303	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	10		T9	12		T11	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T41	14		T162	8		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T85	8		T167	3		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	11		T159	5		T72	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T223	4		T132	5		T181	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	1		T156	4		T159	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	15		T37	5		T170	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T122	1		T176	14		T289	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T132	3		T51	8		T110	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	4		T173	17		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T72	1		T166	10		T221	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	3		T62	12		T71	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T38	4		T167	10		T121	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	1		T161	2		T221	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T219	11		T212	1		T53	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T60	9		T61	1		T71	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T2	25		T8	1		T9	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T41	15		T189	1		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	11		T11	2		T189	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T49	1		T38	10		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T85	9		T47	1		T117	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T49	1		T61	1		T47	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T223	5		T132	6		T181	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	2		T238	1		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	1		T7	16		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T31	1		T122	2		T298	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T56	1		T61	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	5		T219	1		T85	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T43	1		T220	1		T72	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T7	4		T62	13		T71	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T160	1		T224	10		T38	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	3		T161	3		T221	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T3	1		T167	4		T112	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T221	10		T260	8		T299	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17907	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T12	10		T49	1		T164	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T212	16		T53	1		T300	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T60	8		T61	13		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1138	1			T9	12		T54	33		T199	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T41	13		T189	9		T162	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T189	12		T164	4		T212	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T38	16		T211	8		T15	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T175	2		T304	13		T192	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T61	4		T156	2		T72	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T174	10		T242	7		T21	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T211	11		T214	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	2		T9	7		T51	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	13		T182	10		T243	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T61	6		T189	9		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	8		T212	6		T226	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T166	13		T211	7		T134	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T62	15		T71	12		T156	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T224	9		T38	4		T168	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T161	4		T221	9		T50	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T3	9		T167	4		T112	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T221	10		T260	5		T299	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T232	8		T284	6		T305	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T12	10		T164	9		T38	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	535	1			T5	3		T11	1		T13	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T221	10		T260	8		T230	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T232	1		T296	6		T297	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T219	11		T238	1		T212	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	10		T49	1		T60	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T2	25		T8	1		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T189	1		T220	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	11		T9	13		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T41	15		T162	9		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T85	9		T47	1		T167	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T49	2		T61	1		T47	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T223	5		T132	6		T181	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	2		T156	5		T159	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	1		T7	16		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T219	1		T31	1		T122	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T61	1		T36	1		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	5		T85	1		T173	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T56	1		T220	1		T72	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	4		T62	13		T71	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T3	1		T43	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T11	3		T161	3		T221	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17426	1			T5	138		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T224	9		T167	4		T108	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T221	10		T260	5		T306	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T232	8		T296	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T212	16		T53	1		T284	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	10		T60	8		T61	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1125	1			T54	33		T199	34		T247	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T189	9		T29	9		T108	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	12		T189	12		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T41	13		T162	6		T38	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T32	2		T175	2		T275	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T61	4		T72	14		T161	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T242	7		T304	13		T192	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	1		T156	2		T211	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	2		T9	7		T174	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T31	13		T182	10		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T61	6		T189	9		T51	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	8		T173	18		T212	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T166	13		T221	13		T211	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T62	15		T71	12		T156	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	9		T38	4		T168	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T161	4		T221	9		T50	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19