Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20802

1

T1

13

T5

141

T6

18

auto[ADC_CTRL_FILTER_COND_OUT]

5600

1

T2

25

T3

13

T7

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20650

1

T3

3

T5

141

T6

18

auto[1]

5752

1

T1

13

T2

25

T3

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	333	1			T61	21		T36	1		T220	1
values[0]	34	1			T238	1		T291	1		T263	32
values[1]	871	1			T9	25		T13	3		T71	24
values[2]	639	1			T9	8		T49	1		T220	1
values[3]	571	1			T37	6		T189	23		T166	1
values[4]	722	1			T49	1		T60	17		T219	11
values[5]	538	1			T7	16		T159	13		T48	5
values[6]	617	1			T11	5		T49	1		T61	5
values[7]	575	1			T7	4		T56	1		T41	28
values[8]	569	1			T7	11		T12	20		T219	1
values[9]	3053	1			T1	13		T2	25		T3	13
minimum	17880	1			T5	141		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	674	1			T9	25		T13	3		T71	24
values[1]	2878	1			T2	25		T8	1		T9	8
values[2]	541	1			T60	17		T37	6		T189	23
values[3]	657	1			T7	16		T49	1		T219	11
values[4]	630	1			T11	3		T85	9		T159	13
values[5]	620	1			T7	4		T11	2		T49	1
values[6]	610	1			T12	20		T56	1		T219	1
values[7]	593	1			T1	13		T7	11		T43	1
values[8]	757	1			T3	13		T61	7		T36	1
values[9]	193	1			T61	14		T62	28		T212	7
minimum	18249	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T238	1		T223	1		T161	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	13		T13	2		T71	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T49	1		T211	9		T26	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1592	1			T2	2		T8	1		T9	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	1		T189	23		T162	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T60	9		T166	1		T221	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T47	1		T159	1		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	1		T49	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T85	1		T211	12		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	2		T159	1		T48	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	1		T189	10		T161	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	1		T11	1		T61	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T219	1		T85	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	11		T56	1		T211	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	9		T7	1		T72	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T43	1		T72	15		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T164	5		T160	1		T168	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T3	13		T61	7		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T212	7		T38	1		T50	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T61	14		T62	16		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17903	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T170	1		T176	1		T307	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T223	4		T121	5		T122	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	12		T13	1		T71	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T26	5		T51	1		T111	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1021	1			T2	23		T57	13		T58	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	5		T162	8		T132	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T60	8		T221	14		T181	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T47	11		T159	5		T167	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	15		T219	10		T71	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T85	8		T133	9		T289	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	1		T159	12		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T161	2		T167	3		T110	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	3		T11	1		T41	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T166	4		T213	9		T121	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	9		T132	5		T215	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	4		T7	10		T72	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T72	12		T38	4		T167	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T164	2		T168	24		T243	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T159	10		T221	6		T15	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T50	4		T271	6		T196	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T62	12		T266	7		T18	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T11	2		T13	3		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T170	9		T176	14		T285	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T164	5		T38	1		T50	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T61	21		T36	1		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T238	1		T291	1		T263	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T156	3		T223	1		T161	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	13		T13	2		T71	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	1		T211	9		T26	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	8		T220	1		T72	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	1		T189	23		T162	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T166	1		T31	14		T277	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T47	1		T159	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	1		T60	9		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T167	1		T211	12		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	1		T159	1		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T49	1		T85	1		T189	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	3		T61	5		T156	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T220	1		T166	5		T213	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T56	1		T41	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	1		T219	1		T85	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	11		T72	15		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	9		T72	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1674	1			T2	2		T3	13		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17753	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T164	2		T50	4		T168	24
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T221	6		T266	7		T253	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T263	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T156	4		T223	4		T224	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	12		T13	1		T71	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T26	5		T121	5		T122	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T72	1		T264	10		T230	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T37	5		T162	8		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T181	14		T174	15		T248	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	11		T159	5		T132	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T60	8		T219	10		T71	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T167	3		T182	12		T269	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	15		T159	12		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T85	8		T161	2		T167	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	2		T156	13		T221	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T166	4		T213	9		T121	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	3		T41	14		T173	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	10		T166	6		T120	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	9		T72	12		T167	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	4		T72	1		T168	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1097	1			T2	23		T57	13		T58	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T238	1		T223	5		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	13		T13	2		T71	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T49	1		T211	1		T26	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1357	1			T2	25		T8	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T37	6		T189	2		T162	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T60	9		T166	1		T221	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T47	12		T159	6		T167	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	16		T49	1		T219	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T85	9		T211	1		T133	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	3		T159	13		T48	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T49	1		T189	1		T161	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	4		T11	2		T61	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T219	1		T85	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	10		T56	1		T211	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	5		T7	11		T72	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T43	1		T72	13		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T164	3		T160	1		T168	26
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	2		T61	1		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T212	1		T38	1		T50	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T61	1		T62	13		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18051	1			T5	141		T6	18		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T170	10		T176	15		T307	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T161	6		T134	5		T122	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	12		T13	1		T71	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T211	8		T26	4		T51	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1256	1			T9	7		T54	33		T199	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T189	21		T162	6		T209	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T60	8		T221	9		T104	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	9		T33	3		T51	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T38	13		T53	1		T230	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T211	11		T134	2		T214	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T164	9		T212	17		T108	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T189	9		T161	4		T167	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T61	4		T41	13		T156	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T166	4		T213	2		T178	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	10		T211	7		T250	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T1	8		T166	9		T232	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T72	14		T38	4		T29	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T164	4		T168	21		T243	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	11		T61	6		T221	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T212	6		T50	6		T308	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T61	13		T62	15		T266	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T156	2		T224	9		T108	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T285	8		T21	1		T309	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T164	3		T38	1		T50	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T61	2		T36	1		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T238	1		T291	1		T263	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T156	5		T223	5		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	13		T13	2		T71	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T49	1		T211	1		T26	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	1		T220	1		T72	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	6		T189	2		T162	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T166	1		T31	1		T277	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T47	12		T159	6		T132	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T49	1		T60	9		T219	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T167	4		T211	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	16		T159	13		T48	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T49	1		T85	9		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	5		T61	1		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T220	1		T166	5		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	4		T56	1		T41	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	11		T219	1		T85	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	10		T72	13		T167	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	5		T72	2		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1456	1			T2	25		T3	2		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17880	1			T5	141		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T164	4		T50	6		T168	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T61	19		T221	13		T266	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T263	18		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T156	2		T161	6		T224	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	12		T13	1		T71	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T211	8		T26	4		T122	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	7		T212	16		T31	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T189	21		T162	6		T51	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T31	13		T174	15		T104	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T29	9		T33	3		T51	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T60	8		T38	13		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T211	11		T134	2		T214	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T164	9		T108	12		T248	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T189	9		T161	4		T167	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T61	4		T156	11		T212	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T166	4		T213	2		T110	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	13		T173	18		T38	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T166	9		T232	7		T178	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	10		T72	14		T32	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T1	8		T212	6		T243	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1315	1			T3	11		T54	33		T62	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19