Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26402

1

T1

13

T2

25

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23145

1

T2

25

T3

13

T5

141

auto[ADC_CTRL_FILTER_COND_OUT]

3257

1

T1

13

T7

4

T12

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20502

1

T1

13

T3

3

T5

138

auto[1]

5900

1

T2

25

T3

10

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22657

1

T1

9

T2

2

T3

13

auto[1]

3745

1

T1

4

T2

23

T7

28

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	490	1			T3	10		T5	3		T11	1
values[0]	63	1			T238	1		T38	25		T284	7
values[1]	470	1			T12	20		T49	1		T60	17
values[2]	2711	1			T2	25		T8	1		T54	36
values[3]	750	1			T7	11		T9	25		T11	2
values[4]	609	1			T49	2		T61	5		T85	9
values[5]	624	1			T13	3		T47	1		T156	7
values[6]	598	1			T1	13		T3	3		T7	16
values[7]	564	1			T61	7		T85	1		T36	1
values[8]	858	1			T7	4		T56	1		T62	28
values[9]	1239	1			T11	3		T43	1		T156	25
minimum	17426	1			T5	138		T6	18		T10	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	633	1			T12	20		T49	1		T60	17
values[1]	2773	1			T2	25		T8	1		T9	25
values[2]	817	1			T7	11		T11	2		T49	1
values[3]	429	1			T13	3		T49	1		T61	5
values[4]	594	1			T238	1		T223	5		T211	12
values[5]	677	1			T3	3		T7	16		T9	8
values[6]	793	1			T1	13		T61	7		T219	1
values[7]	746	1			T7	4		T56	1		T43	1
values[8]	858	1			T11	3		T160	1		T161	7
values[9]	182	1			T3	10		T221	20		T167	8
minimum	17900	1			T5	141		T6	18		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

3861

1

T1

8

T3

11

T9

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	1		T219	1		T212	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	11		T60	9		T61	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T2	2		T8	1		T9	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T189	10		T220	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	1		T11	1		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T49	1		T38	17		T211	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T156	3		T159	1		T161	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	2		T49	1		T61	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T132	1		T133	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T238	1		T223	1		T211	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	3		T7	1		T9	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T31	14		T298	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T61	7		T189	10		T166	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	9		T219	1		T85	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T56	1		T43	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	1		T71	13		T156	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	2		T160	1		T161	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T38	5		T221	10		T50	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T3	10		T167	5		T168	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T221	11		T260	7		T310	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17764	1			T5	141		T6	18		T10	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T219	10		T53	1		T300	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	9		T60	8		T71	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T2	23		T9	12		T57	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T162	8		T29	10		T246	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	10		T11	1		T164	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	9		T15	6		T29	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T156	4		T159	5		T52	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	1		T85	8		T47	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T132	5		T133	9		T120	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T223	4		T52	1		T181	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	15		T37	5		T170	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T176	14		T177	14		T289	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T166	4		T132	3		T127	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	4		T62	12		T173	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T72	1		T166	6		T221	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T7	3		T71	11		T156	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	1		T161	2		T224	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	4		T221	14		T50	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T167	3		T168	11		T181	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T221	9		T260	6		T185	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	2		T13	3		T85	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	470	1			T3	10		T5	3		T11	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T260	7		T311	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T238	1		T228	7		T312	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T38	14		T284	7		T296	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	1		T219	1		T164	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	11		T60	9		T61	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T2	2		T8	1		T54	36
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T189	10		T220	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	1		T9	13		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T162	7		T38	17		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T159	1		T161	7		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T49	2		T61	5		T85	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T156	3		T132	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	2		T47	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	3		T7	1		T9	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	9		T219	1		T174	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T61	7		T132	1		T51	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T85	1		T36	1		T48	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T56	1		T189	10		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T62	16		T71	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T11	2		T43	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T156	12		T38	5		T221	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17299	1			T5	138		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T167	3		T313	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T260	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T228	6		T312	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T38	11		T296	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T219	10		T164	9		T53	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	9		T60	8		T71	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T2	23		T57	13		T58	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	6		T29	10		T168	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	10		T9	12		T11	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T162	8		T38	9		T225	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T159	5		T167	3		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T85	8		T47	11		T72	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T156	4		T132	5		T133	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	1		T159	12		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	15		T37	5		T170	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	4		T174	2		T176	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T132	3		T51	8		T314	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T48	3		T110	14		T289	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T72	1		T166	10		T221	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	3		T62	12		T71	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T11	1		T161	2		T224	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T156	13		T38	4		T221	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T13	3		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T49	1		T219	11		T212	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	10		T60	9		T61	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T2	25		T8	1		T9	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T189	1		T220	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T7	11		T11	2		T164	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T49	1		T38	10		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T156	5		T159	6		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	2		T49	1		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T132	6		T133	10		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T238	1		T223	5		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T7	16		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T31	1		T298	1		T176	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T61	1		T189	1		T166	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	5		T219	1		T85	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T56	1		T43	1		T220	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	4		T71	12		T156	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T11	3		T160	1		T161	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T38	5		T221	15		T50	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T3	1		T167	4		T168	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T221	10		T260	8		T310	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17891	1			T5	141		T6	18		T10	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T212	16		T134	2		T53	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	10		T60	8		T61	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T9	12		T54	33		T41	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T189	9		T162	6		T29	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T164	4		T212	17		T31	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T38	16		T211	8		T15	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T156	2		T161	6		T175	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	1		T61	4		T72	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T254	3		T269	7		T193	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T211	11		T214	14		T174	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	2		T9	7		T51	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T31	13		T182	10		T243	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T61	6		T189	9		T166	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	8		T62	15		T173	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T166	9		T221	13		T211	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T71	12		T156	11		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T161	4		T224	9		T175	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T38	4		T221	9		T50	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T3	9		T167	4		T168	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T221	10		T260	5		T185	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T164	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	463	1			T3	1		T5	3		T11	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T260	8		T311	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T238	1		T228	7		T312	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T38	12		T284	1		T296	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T49	1		T219	11		T164	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	10		T60	9		T61	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T2	25		T8	1		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T189	1		T220	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T7	11		T9	13		T11	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T162	9		T38	10		T225	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T159	6		T161	1		T167	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	2		T61	1		T85	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T156	5		T132	6		T133	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	2		T47	1		T159	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	1		T7	16		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	5		T219	1		T174	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T61	1		T132	4		T51	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T85	1		T36	1		T48	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T56	1		T189	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	4		T62	13		T71	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T11	3		T43	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T156	14		T38	5		T221	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17426	1			T5	138		T6	18		T10	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T3	9		T167	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T260	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T228	6		T312	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T38	13		T284	6		T296	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T164	9		T134	2		T53	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T12	10		T60	8		T61	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T54	33		T199	34		T247	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T189	9		T15	4		T29	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	12		T41	13		T189	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T162	6		T38	16		T275	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T161	6		T32	2		T174	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T61	4		T72	14		T211	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T156	2		T254	3		T304	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T211	11		T31	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T3	2		T9	7		T242	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	8		T174	10		T182	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T61	6		T51	2		T314	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T212	6		T110	13		T234	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T189	9		T166	13		T221	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T62	15		T71	12		T173	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T161	4		T224	9		T168	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T156	11		T38	4		T221	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22541

1

T1

5

T2

25

T3

2

auto[1]

auto[0]

3861

1

T1

8

T3

11

T9

19