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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.07 96.67 100.00 100.00 98.83 98.33 91.66


Total test records in report: 920
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T799 /workspace/coverage/default/4.adc_ctrl_fsm_reset.3277482972 Apr 16 02:20:56 PM PDT 24 Apr 16 02:30:21 PM PDT 24 94839442585 ps
T800 /workspace/coverage/default/22.adc_ctrl_fsm_reset.2856204587 Apr 16 02:22:50 PM PDT 24 Apr 16 02:33:43 PM PDT 24 122426582456 ps
T801 /workspace/coverage/default/47.adc_ctrl_clock_gating.2799429896 Apr 16 02:27:31 PM PDT 24 Apr 16 02:36:29 PM PDT 24 540466871477 ps
T207 /workspace/coverage/default/17.adc_ctrl_filters_both.1988394138 Apr 16 02:21:56 PM PDT 24 Apr 16 02:25:33 PM PDT 24 344399449283 ps
T802 /workspace/coverage/default/33.adc_ctrl_poweron_counter.2242897977 Apr 16 02:24:53 PM PDT 24 Apr 16 02:25:02 PM PDT 24 3583192849 ps
T68 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3847698965 Apr 16 02:18:12 PM PDT 24 Apr 16 02:18:18 PM PDT 24 4434181729 ps
T803 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2021381791 Apr 16 02:18:26 PM PDT 24 Apr 16 02:18:27 PM PDT 24 460144192 ps
T136 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1680398196 Apr 16 02:17:10 PM PDT 24 Apr 16 02:17:13 PM PDT 24 1028044363 ps
T804 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1019552671 Apr 16 02:17:14 PM PDT 24 Apr 16 02:17:16 PM PDT 24 348533796 ps
T76 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.160154289 Apr 16 02:17:48 PM PDT 24 Apr 16 02:17:50 PM PDT 24 486855247 ps
T805 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3828024478 Apr 16 02:17:58 PM PDT 24 Apr 16 02:18:00 PM PDT 24 283949813 ps
T806 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.173109368 Apr 16 02:18:02 PM PDT 24 Apr 16 02:18:03 PM PDT 24 429051793 ps
T807 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1407974123 Apr 16 02:18:27 PM PDT 24 Apr 16 02:18:28 PM PDT 24 467988999 ps
T808 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.812798849 Apr 16 02:17:57 PM PDT 24 Apr 16 02:17:59 PM PDT 24 334112654 ps
T73 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.394899947 Apr 16 02:18:07 PM PDT 24 Apr 16 02:18:15 PM PDT 24 8731634253 ps
T74 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1341237584 Apr 16 02:17:23 PM PDT 24 Apr 16 02:17:32 PM PDT 24 4114425095 ps
T81 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.295914907 Apr 16 02:17:59 PM PDT 24 Apr 16 02:18:02 PM PDT 24 411558459 ps
T809 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3511919528 Apr 16 02:17:35 PM PDT 24 Apr 16 02:17:36 PM PDT 24 318726174 ps
T137 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3553700118 Apr 16 02:17:32 PM PDT 24 Apr 16 02:17:37 PM PDT 24 1149402922 ps
T138 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3298892701 Apr 16 02:18:18 PM PDT 24 Apr 16 02:18:20 PM PDT 24 324975227 ps
T82 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3941186267 Apr 16 02:17:47 PM PDT 24 Apr 16 02:17:49 PM PDT 24 534787080 ps
T109 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1484843095 Apr 16 02:18:16 PM PDT 24 Apr 16 02:18:18 PM PDT 24 579837151 ps
T69 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2715021121 Apr 16 02:18:20 PM PDT 24 Apr 16 02:18:32 PM PDT 24 5014512879 ps
T139 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4099407560 Apr 16 02:17:11 PM PDT 24 Apr 16 02:17:13 PM PDT 24 503566431 ps
T70 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.629934246 Apr 16 02:17:28 PM PDT 24 Apr 16 02:17:34 PM PDT 24 2161985093 ps
T150 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.306097706 Apr 16 02:18:02 PM PDT 24 Apr 16 02:18:05 PM PDT 24 2429923714 ps
T810 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.70258301 Apr 16 02:18:25 PM PDT 24 Apr 16 02:18:27 PM PDT 24 292547238 ps
T75 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.205630092 Apr 16 02:17:48 PM PDT 24 Apr 16 02:17:55 PM PDT 24 4180956615 ps
T811 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3652042647 Apr 16 02:18:24 PM PDT 24 Apr 16 02:18:26 PM PDT 24 331836722 ps
T151 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1763665608 Apr 16 02:17:57 PM PDT 24 Apr 16 02:18:02 PM PDT 24 4774749940 ps
T812 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2467741756 Apr 16 02:17:48 PM PDT 24 Apr 16 02:17:50 PM PDT 24 502379678 ps
T140 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2782647583 Apr 16 02:17:29 PM PDT 24 Apr 16 02:17:34 PM PDT 24 932316196 ps
T152 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.858940738 Apr 16 02:18:16 PM PDT 24 Apr 16 02:18:23 PM PDT 24 4905306258 ps
T153 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.823990023 Apr 16 02:17:52 PM PDT 24 Apr 16 02:17:58 PM PDT 24 4926438783 ps
T77 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.467709883 Apr 16 02:18:20 PM PDT 24 Apr 16 02:18:41 PM PDT 24 7825740306 ps
T87 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3985210233 Apr 16 02:17:43 PM PDT 24 Apr 16 02:18:05 PM PDT 24 8426466798 ps
T813 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3730226113 Apr 16 02:18:23 PM PDT 24 Apr 16 02:18:26 PM PDT 24 521806947 ps
T814 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2648921829 Apr 16 02:18:30 PM PDT 24 Apr 16 02:18:32 PM PDT 24 425095314 ps
T815 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3549098252 Apr 16 02:18:22 PM PDT 24 Apr 16 02:18:24 PM PDT 24 512688223 ps
T94 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.176021705 Apr 16 02:18:12 PM PDT 24 Apr 16 02:18:14 PM PDT 24 647209414 ps
T88 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1566496409 Apr 16 02:17:44 PM PDT 24 Apr 16 02:17:47 PM PDT 24 415093389 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.944478044 Apr 16 02:17:39 PM PDT 24 Apr 16 02:17:40 PM PDT 24 458207131 ps
T93 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1881248680 Apr 16 02:17:32 PM PDT 24 Apr 16 02:17:46 PM PDT 24 4450686177 ps
T89 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3268280250 Apr 16 02:17:56 PM PDT 24 Apr 16 02:18:03 PM PDT 24 4216394128 ps
T816 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1881784581 Apr 16 02:18:22 PM PDT 24 Apr 16 02:18:25 PM PDT 24 411063436 ps
T92 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1938680621 Apr 16 02:18:17 PM PDT 24 Apr 16 02:18:24 PM PDT 24 7961574540 ps
T817 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2198552127 Apr 16 02:17:48 PM PDT 24 Apr 16 02:17:50 PM PDT 24 446655858 ps
T154 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.737217443 Apr 16 02:18:01 PM PDT 24 Apr 16 02:18:03 PM PDT 24 440570572 ps
T818 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.683430988 Apr 16 02:18:30 PM PDT 24 Apr 16 02:18:32 PM PDT 24 457584132 ps
T819 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.787659674 Apr 16 02:18:32 PM PDT 24 Apr 16 02:18:35 PM PDT 24 507461781 ps
T83 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3005062918 Apr 16 02:17:54 PM PDT 24 Apr 16 02:17:57 PM PDT 24 393648438 ps
T820 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.749020729 Apr 16 02:17:32 PM PDT 24 Apr 16 02:17:34 PM PDT 24 422224268 ps
T141 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2519446332 Apr 16 02:17:47 PM PDT 24 Apr 16 02:17:49 PM PDT 24 368465594 ps
T155 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.522007804 Apr 16 02:17:39 PM PDT 24 Apr 16 02:17:48 PM PDT 24 2387510017 ps
T821 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.750612107 Apr 16 02:18:11 PM PDT 24 Apr 16 02:18:13 PM PDT 24 480840045 ps
T822 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3269013948 Apr 16 02:17:10 PM PDT 24 Apr 16 02:17:21 PM PDT 24 3967272090 ps
T345 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1742620589 Apr 16 02:17:34 PM PDT 24 Apr 16 02:17:40 PM PDT 24 8974524176 ps
T823 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2090242151 Apr 16 02:18:21 PM PDT 24 Apr 16 02:18:23 PM PDT 24 460924588 ps
T84 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2809815616 Apr 16 02:17:21 PM PDT 24 Apr 16 02:17:24 PM PDT 24 553787965 ps
T824 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.665420602 Apr 16 02:18:26 PM PDT 24 Apr 16 02:18:28 PM PDT 24 523136610 ps
T825 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1696804851 Apr 16 02:18:31 PM PDT 24 Apr 16 02:18:33 PM PDT 24 325509123 ps
T826 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4277433146 Apr 16 02:18:02 PM PDT 24 Apr 16 02:18:04 PM PDT 24 302544976 ps
T827 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.866995600 Apr 16 02:17:19 PM PDT 24 Apr 16 02:17:22 PM PDT 24 553765400 ps
T142 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1400689191 Apr 16 02:17:45 PM PDT 24 Apr 16 02:17:47 PM PDT 24 494726457 ps
T143 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2142504711 Apr 16 02:17:10 PM PDT 24 Apr 16 02:17:14 PM PDT 24 1146293365 ps
T90 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.221161684 Apr 16 02:18:11 PM PDT 24 Apr 16 02:18:15 PM PDT 24 458960958 ps
T144 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1178856477 Apr 16 02:18:14 PM PDT 24 Apr 16 02:18:16 PM PDT 24 409860996 ps
T145 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.193578021 Apr 16 02:17:33 PM PDT 24 Apr 16 02:17:35 PM PDT 24 1187760477 ps
T146 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3528249566 Apr 16 02:17:29 PM PDT 24 Apr 16 02:17:50 PM PDT 24 22565560224 ps
T828 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3855075294 Apr 16 02:18:21 PM PDT 24 Apr 16 02:18:25 PM PDT 24 4454512054 ps
T829 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2840114326 Apr 16 02:17:56 PM PDT 24 Apr 16 02:17:57 PM PDT 24 569142411 ps
T830 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4270029469 Apr 16 02:17:47 PM PDT 24 Apr 16 02:17:50 PM PDT 24 2378652316 ps
T831 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3064858147 Apr 16 02:18:21 PM PDT 24 Apr 16 02:18:24 PM PDT 24 452318214 ps
T91 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1124133814 Apr 16 02:18:17 PM PDT 24 Apr 16 02:18:19 PM PDT 24 407159884 ps
T832 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1092481135 Apr 16 02:17:58 PM PDT 24 Apr 16 02:18:00 PM PDT 24 398142452 ps
T147 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1916456223 Apr 16 02:17:10 PM PDT 24 Apr 16 02:19:02 PM PDT 24 51562580913 ps
T833 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3735162209 Apr 16 02:18:12 PM PDT 24 Apr 16 02:18:14 PM PDT 24 446826763 ps
T834 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.265660006 Apr 16 02:18:27 PM PDT 24 Apr 16 02:18:28 PM PDT 24 416059932 ps
T148 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2974582524 Apr 16 02:18:06 PM PDT 24 Apr 16 02:18:08 PM PDT 24 572869633 ps
T835 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4190482599 Apr 16 02:17:48 PM PDT 24 Apr 16 02:17:50 PM PDT 24 489928494 ps
T836 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4164905465 Apr 16 02:17:59 PM PDT 24 Apr 16 02:18:04 PM PDT 24 2861773051 ps
T837 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3447334067 Apr 16 02:17:44 PM PDT 24 Apr 16 02:17:51 PM PDT 24 4570426526 ps
T838 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1410239844 Apr 16 02:17:42 PM PDT 24 Apr 16 02:17:45 PM PDT 24 613729233 ps
T839 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1467371722 Apr 16 02:17:16 PM PDT 24 Apr 16 02:17:18 PM PDT 24 353731836 ps
T840 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.44712094 Apr 16 02:17:28 PM PDT 24 Apr 16 02:17:30 PM PDT 24 447928746 ps
T841 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1165781773 Apr 16 02:18:13 PM PDT 24 Apr 16 02:18:19 PM PDT 24 8109769712 ps
T842 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1178054020 Apr 16 02:18:27 PM PDT 24 Apr 16 02:18:28 PM PDT 24 427202353 ps
T843 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2848419010 Apr 16 02:17:23 PM PDT 24 Apr 16 02:17:25 PM PDT 24 909281267 ps
T844 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2329451669 Apr 16 02:17:38 PM PDT 24 Apr 16 02:17:43 PM PDT 24 1203147991 ps
T845 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1609601768 Apr 16 02:18:21 PM PDT 24 Apr 16 02:18:23 PM PDT 24 544738929 ps
T846 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2130561303 Apr 16 02:17:51 PM PDT 24 Apr 16 02:17:52 PM PDT 24 423896048 ps
T847 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2476011342 Apr 16 02:17:59 PM PDT 24 Apr 16 02:18:01 PM PDT 24 665098249 ps
T848 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1319654635 Apr 16 02:18:20 PM PDT 24 Apr 16 02:18:21 PM PDT 24 340499014 ps
T149 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4277653588 Apr 16 02:17:19 PM PDT 24 Apr 16 02:17:22 PM PDT 24 1266638091 ps
T849 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3651928930 Apr 16 02:18:09 PM PDT 24 Apr 16 02:18:11 PM PDT 24 470738366 ps
T850 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.843442705 Apr 16 02:18:12 PM PDT 24 Apr 16 02:18:19 PM PDT 24 4794196392 ps
T851 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1159790325 Apr 16 02:17:34 PM PDT 24 Apr 16 02:17:36 PM PDT 24 329517785 ps
T852 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2843130875 Apr 16 02:18:18 PM PDT 24 Apr 16 02:18:20 PM PDT 24 399086316 ps
T853 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.83279449 Apr 16 02:18:22 PM PDT 24 Apr 16 02:18:25 PM PDT 24 322497120 ps
T854 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2762695863 Apr 16 02:18:21 PM PDT 24 Apr 16 02:18:23 PM PDT 24 325819504 ps
T855 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3453424594 Apr 16 02:17:33 PM PDT 24 Apr 16 02:17:35 PM PDT 24 740409671 ps
T856 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3874102668 Apr 16 02:18:06 PM PDT 24 Apr 16 02:18:10 PM PDT 24 454063804 ps
T857 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.681232013 Apr 16 02:17:35 PM PDT 24 Apr 16 02:17:37 PM PDT 24 622046281 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3627402082 Apr 16 02:17:36 PM PDT 24 Apr 16 02:17:39 PM PDT 24 2386729893 ps
T859 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1589909353 Apr 16 02:18:08 PM PDT 24 Apr 16 02:18:10 PM PDT 24 443312124 ps
T347 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2281583074 Apr 16 02:18:00 PM PDT 24 Apr 16 02:18:07 PM PDT 24 4123244204 ps
T346 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3763752514 Apr 16 02:17:59 PM PDT 24 Apr 16 02:18:20 PM PDT 24 8090730375 ps
T860 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.292207882 Apr 16 02:18:06 PM PDT 24 Apr 16 02:18:10 PM PDT 24 5201242275 ps
T861 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1242025816 Apr 16 02:18:24 PM PDT 24 Apr 16 02:18:26 PM PDT 24 404929292 ps
T862 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4132345270 Apr 16 02:17:49 PM PDT 24 Apr 16 02:18:04 PM PDT 24 4359424454 ps
T863 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2700156763 Apr 16 02:17:32 PM PDT 24 Apr 16 02:18:41 PM PDT 24 52996331004 ps
T864 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2420004634 Apr 16 02:17:59 PM PDT 24 Apr 16 02:18:02 PM PDT 24 4409835081 ps
T865 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2446149521 Apr 16 02:17:19 PM PDT 24 Apr 16 02:17:24 PM PDT 24 2582761300 ps
T866 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3587051788 Apr 16 02:17:39 PM PDT 24 Apr 16 02:18:16 PM PDT 24 53104706183 ps
T867 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1007771955 Apr 16 02:18:27 PM PDT 24 Apr 16 02:18:29 PM PDT 24 458951103 ps
T868 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2579531196 Apr 16 02:18:22 PM PDT 24 Apr 16 02:18:25 PM PDT 24 338981549 ps
T869 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4276960498 Apr 16 02:17:57 PM PDT 24 Apr 16 02:17:59 PM PDT 24 566618009 ps
T870 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.321183579 Apr 16 02:17:13 PM PDT 24 Apr 16 02:17:18 PM PDT 24 4659870974 ps
T871 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.475008677 Apr 16 02:17:53 PM PDT 24 Apr 16 02:17:54 PM PDT 24 488608381 ps
T872 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.519196871 Apr 16 02:17:57 PM PDT 24 Apr 16 02:18:10 PM PDT 24 8141373900 ps
T873 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.34319164 Apr 16 02:18:06 PM PDT 24 Apr 16 02:18:09 PM PDT 24 490154095 ps
T874 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.562579901 Apr 16 02:17:20 PM PDT 24 Apr 16 02:17:22 PM PDT 24 370393183 ps
T875 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1271291872 Apr 16 02:18:21 PM PDT 24 Apr 16 02:18:24 PM PDT 24 542570487 ps
T876 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3122740840 Apr 16 02:17:47 PM PDT 24 Apr 16 02:17:48 PM PDT 24 314952180 ps
T877 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1201489431 Apr 16 02:18:27 PM PDT 24 Apr 16 02:18:29 PM PDT 24 446599397 ps
T878 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1950050417 Apr 16 02:17:19 PM PDT 24 Apr 16 02:18:29 PM PDT 24 53275618936 ps
T879 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.21821755 Apr 16 02:18:15 PM PDT 24 Apr 16 02:18:16 PM PDT 24 512334530 ps
T880 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4052930008 Apr 16 02:17:51 PM PDT 24 Apr 16 02:18:14 PM PDT 24 8330562936 ps
T881 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2975842007 Apr 16 02:17:43 PM PDT 24 Apr 16 02:17:45 PM PDT 24 495253816 ps
T882 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3078836721 Apr 16 02:18:24 PM PDT 24 Apr 16 02:18:26 PM PDT 24 458625475 ps
T883 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4040685089 Apr 16 02:17:21 PM PDT 24 Apr 16 02:17:25 PM PDT 24 1273001110 ps
T884 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.707770840 Apr 16 02:18:13 PM PDT 24 Apr 16 02:18:15 PM PDT 24 436931965 ps
T885 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2905450489 Apr 16 02:18:22 PM PDT 24 Apr 16 02:18:24 PM PDT 24 336923619 ps
T886 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3610233427 Apr 16 02:17:41 PM PDT 24 Apr 16 02:17:44 PM PDT 24 497703547 ps
T887 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3348305347 Apr 16 02:17:54 PM PDT 24 Apr 16 02:17:57 PM PDT 24 638840206 ps
T888 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.545122246 Apr 16 02:18:28 PM PDT 24 Apr 16 02:18:30 PM PDT 24 531069476 ps
T95 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.876093438 Apr 16 02:17:07 PM PDT 24 Apr 16 02:17:14 PM PDT 24 7947062752 ps
T889 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.423320385 Apr 16 02:17:34 PM PDT 24 Apr 16 02:17:37 PM PDT 24 473957230 ps
T890 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4068984742 Apr 16 02:17:57 PM PDT 24 Apr 16 02:17:59 PM PDT 24 666010615 ps
T891 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.826634340 Apr 16 02:17:43 PM PDT 24 Apr 16 02:17:46 PM PDT 24 2071648394 ps
T892 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.822393943 Apr 16 02:18:29 PM PDT 24 Apr 16 02:18:31 PM PDT 24 402919145 ps
T96 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3186431662 Apr 16 02:18:06 PM PDT 24 Apr 16 02:18:15 PM PDT 24 8649621711 ps
T893 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.245244726 Apr 16 02:17:33 PM PDT 24 Apr 16 02:17:36 PM PDT 24 502978516 ps
T894 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3333799180 Apr 16 02:18:11 PM PDT 24 Apr 16 02:18:12 PM PDT 24 519188402 ps
T895 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3083537465 Apr 16 02:18:01 PM PDT 24 Apr 16 02:18:04 PM PDT 24 1270500150 ps
T896 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3446709511 Apr 16 02:18:14 PM PDT 24 Apr 16 02:18:17 PM PDT 24 769338806 ps
T897 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2442071283 Apr 16 02:17:53 PM PDT 24 Apr 16 02:18:06 PM PDT 24 4387440757 ps
T898 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1665772517 Apr 16 02:18:29 PM PDT 24 Apr 16 02:18:31 PM PDT 24 500818050 ps
T899 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3765923759 Apr 16 02:18:06 PM PDT 24 Apr 16 02:18:08 PM PDT 24 617924500 ps
T900 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.715185478 Apr 16 02:18:03 PM PDT 24 Apr 16 02:18:06 PM PDT 24 480779948 ps
T901 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.615561687 Apr 16 02:17:22 PM PDT 24 Apr 16 02:17:24 PM PDT 24 413439111 ps
T902 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1141115750 Apr 16 02:18:11 PM PDT 24 Apr 16 02:18:19 PM PDT 24 8271074309 ps
T903 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3237598193 Apr 16 02:17:52 PM PDT 24 Apr 16 02:17:53 PM PDT 24 352661746 ps
T904 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1824240859 Apr 16 02:18:21 PM PDT 24 Apr 16 02:18:24 PM PDT 24 549685642 ps
T905 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1288893308 Apr 16 02:18:00 PM PDT 24 Apr 16 02:18:03 PM PDT 24 714927988 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1020039203 Apr 16 02:17:08 PM PDT 24 Apr 16 02:17:12 PM PDT 24 460011087 ps
T907 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1655048513 Apr 16 02:17:07 PM PDT 24 Apr 16 02:17:08 PM PDT 24 302663150 ps
T908 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.627582080 Apr 16 02:17:14 PM PDT 24 Apr 16 02:17:15 PM PDT 24 658341350 ps
T909 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.301728108 Apr 16 02:17:57 PM PDT 24 Apr 16 02:17:59 PM PDT 24 529976050 ps
T910 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2318557762 Apr 16 02:18:15 PM PDT 24 Apr 16 02:18:17 PM PDT 24 324726998 ps
T911 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.541588254 Apr 16 02:18:06 PM PDT 24 Apr 16 02:18:18 PM PDT 24 2712091935 ps
T912 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2674975785 Apr 16 02:18:27 PM PDT 24 Apr 16 02:18:29 PM PDT 24 403382332 ps
T913 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2412070606 Apr 16 02:17:53 PM PDT 24 Apr 16 02:17:55 PM PDT 24 538872841 ps
T914 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4247954430 Apr 16 02:18:21 PM PDT 24 Apr 16 02:18:23 PM PDT 24 403045207 ps
T915 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.306576333 Apr 16 02:17:36 PM PDT 24 Apr 16 02:17:38 PM PDT 24 1209889808 ps
T916 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1008536066 Apr 16 02:18:06 PM PDT 24 Apr 16 02:18:07 PM PDT 24 457803427 ps
T917 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1618229839 Apr 16 02:18:11 PM PDT 24 Apr 16 02:18:14 PM PDT 24 531745749 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2244888440 Apr 16 02:17:48 PM PDT 24 Apr 16 02:17:52 PM PDT 24 449181632 ps
T919 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1564441356 Apr 16 02:17:40 PM PDT 24 Apr 16 02:17:42 PM PDT 24 443560612 ps
T920 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3309872027 Apr 16 02:18:27 PM PDT 24 Apr 16 02:18:30 PM PDT 24 493795420 ps

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3804704097
Short name T7
Test name
Test status
Simulation time 489913556692 ps
CPU time 477.91 seconds
Started Apr 16 02:27:25 PM PDT 24
Finished Apr 16 02:35:24 PM PDT 24
Peak memory 202344 kb
Host smart-17956c42-0bb6-40a0-a4d4-7c86a1ece9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804704097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3804704097
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.20782583
Short name T13
Test name
Test status
Simulation time 51758736132 ps
CPU time 139.62 seconds
Started Apr 16 02:27:48 PM PDT 24
Finished Apr 16 02:30:08 PM PDT 24
Peak memory 219092 kb
Host smart-ff239a0f-b8c6-4127-9d94-35a21c97bca8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20782583 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.20782583
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3851238752
Short name T61
Test name
Test status
Simulation time 566013333405 ps
CPU time 1166.55 seconds
Started Apr 16 02:24:29 PM PDT 24
Finished Apr 16 02:43:56 PM PDT 24
Peak memory 202268 kb
Host smart-0c14532f-b512-44db-a6d0-2fe7cd63cbe7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851238752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3851238752
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1463524923
Short name T37
Test name
Test status
Simulation time 353052328859 ps
CPU time 989.64 seconds
Started Apr 16 02:21:10 PM PDT 24
Finished Apr 16 02:37:41 PM PDT 24
Peak memory 210828 kb
Host smart-e68b3fd6-d18d-4829-894f-22e2537e960e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463524923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1463524923
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1932877480
Short name T50
Test name
Test status
Simulation time 560415442209 ps
CPU time 618.47 seconds
Started Apr 16 02:27:39 PM PDT 24
Finished Apr 16 02:37:59 PM PDT 24
Peak memory 211944 kb
Host smart-be77fbf2-ac25-4f34-94a2-75178dda881f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932877480 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1932877480
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.919897875
Short name T18
Test name
Test status
Simulation time 685461591273 ps
CPU time 190.59 seconds
Started Apr 16 02:23:07 PM PDT 24
Finished Apr 16 02:26:19 PM PDT 24
Peak memory 218572 kb
Host smart-45b2eb63-c57c-4af0-8803-1e21ac320cd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919897875 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.919897875
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2448298127
Short name T38
Test name
Test status
Simulation time 678075042712 ps
CPU time 747.96 seconds
Started Apr 16 02:22:36 PM PDT 24
Finished Apr 16 02:35:05 PM PDT 24
Peak memory 202216 kb
Host smart-58fc2938-58c0-47ea-9713-9e524278a9b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448298127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2448298127
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1272588021
Short name T72
Test name
Test status
Simulation time 514311340907 ps
CPU time 144.12 seconds
Started Apr 16 02:23:58 PM PDT 24
Finished Apr 16 02:26:23 PM PDT 24
Peak memory 202240 kb
Host smart-51af0f9d-e782-4121-bf63-6d3e2babbe41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272588021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1272588021
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.503456156
Short name T189
Test name
Test status
Simulation time 555716267886 ps
CPU time 332.46 seconds
Started Apr 16 02:23:58 PM PDT 24
Finished Apr 16 02:29:31 PM PDT 24
Peak memory 202324 kb
Host smart-89be4b1a-eeaa-4ef7-94e7-80778c8faab5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503456156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.503456156
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1844644521
Short name T248
Test name
Test status
Simulation time 547868319811 ps
CPU time 1189.04 seconds
Started Apr 16 02:27:41 PM PDT 24
Finished Apr 16 02:47:31 PM PDT 24
Peak memory 202264 kb
Host smart-2766bef9-d987-4ced-8c71-23c8bf68d909
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844644521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1844644521
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.17124568
Short name T156
Test name
Test status
Simulation time 396134818818 ps
CPU time 239.09 seconds
Started Apr 16 02:21:19 PM PDT 24
Finished Apr 16 02:25:19 PM PDT 24
Peak memory 202232 kb
Host smart-459c9d43-25cc-4857-aaf1-34529e697c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17124568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.17124568
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2881162970
Short name T54
Test name
Test status
Simulation time 608293134432 ps
CPU time 718.03 seconds
Started Apr 16 02:20:45 PM PDT 24
Finished Apr 16 02:32:44 PM PDT 24
Peak memory 202224 kb
Host smart-63fdb555-a25b-450e-a951-5ad704f1efeb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881162970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2881162970
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2312096004
Short name T174
Test name
Test status
Simulation time 520184746284 ps
CPU time 138 seconds
Started Apr 16 02:21:09 PM PDT 24
Finished Apr 16 02:23:28 PM PDT 24
Peak memory 202272 kb
Host smart-a1a69887-5710-4346-b82e-7e80c74bc99e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312096004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2312096004
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1703740776
Short name T29
Test name
Test status
Simulation time 389197022971 ps
CPU time 806.35 seconds
Started Apr 16 02:21:12 PM PDT 24
Finished Apr 16 02:34:39 PM PDT 24
Peak memory 202352 kb
Host smart-fcad0462-c7d5-4a24-a596-50d224d3c090
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703740776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1703740776
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3941186267
Short name T82
Test name
Test status
Simulation time 534787080 ps
CPU time 1.65 seconds
Started Apr 16 02:17:47 PM PDT 24
Finished Apr 16 02:17:49 PM PDT 24
Peak memory 201472 kb
Host smart-6af5a90d-8340-4eb0-9047-00950ccf13ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941186267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3941186267
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3231557667
Short name T253
Test name
Test status
Simulation time 526705103099 ps
CPU time 661.09 seconds
Started Apr 16 02:25:20 PM PDT 24
Finished Apr 16 02:36:22 PM PDT 24
Peak memory 202264 kb
Host smart-7b6618a5-e44b-4f60-81e2-050885e0b00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231557667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3231557667
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1792222826
Short name T169
Test name
Test status
Simulation time 472413990 ps
CPU time 1.12 seconds
Started Apr 16 02:21:33 PM PDT 24
Finished Apr 16 02:21:35 PM PDT 24
Peak memory 201956 kb
Host smart-1ba009c8-9b95-4698-b35c-165613eb1cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792222826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1792222826
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1792103780
Short name T166
Test name
Test status
Simulation time 558432527552 ps
CPU time 276.55 seconds
Started Apr 16 02:21:27 PM PDT 24
Finished Apr 16 02:26:04 PM PDT 24
Peak memory 202296 kb
Host smart-50f1d96b-6142-4d40-98f2-7b4063b0ff30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792103780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1792103780
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1265653607
Short name T221
Test name
Test status
Simulation time 528591396654 ps
CPU time 101.73 seconds
Started Apr 16 02:27:22 PM PDT 24
Finished Apr 16 02:29:05 PM PDT 24
Peak memory 202216 kb
Host smart-e4125477-03e9-4e50-aeba-f77954860b84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265653607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1265653607
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1400689191
Short name T142
Test name
Test status
Simulation time 494726457 ps
CPU time 2 seconds
Started Apr 16 02:17:45 PM PDT 24
Finished Apr 16 02:17:47 PM PDT 24
Peak memory 201236 kb
Host smart-2d885e63-a32d-4edb-9c71-365511824440
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400689191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1400689191
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.608078495
Short name T98
Test name
Test status
Simulation time 7876165563 ps
CPU time 6.85 seconds
Started Apr 16 02:20:41 PM PDT 24
Finished Apr 16 02:20:49 PM PDT 24
Peak memory 217820 kb
Host smart-1ce74f1f-28e6-4b99-b601-6b25cb379530
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608078495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.608078495
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2485439584
Short name T182
Test name
Test status
Simulation time 518416809206 ps
CPU time 340.89 seconds
Started Apr 16 02:20:40 PM PDT 24
Finished Apr 16 02:26:22 PM PDT 24
Peak memory 202312 kb
Host smart-bb116fe1-748c-4ed6-b6c2-3c064781940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485439584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2485439584
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2072379575
Short name T167
Test name
Test status
Simulation time 528533128238 ps
CPU time 328.65 seconds
Started Apr 16 02:23:38 PM PDT 24
Finished Apr 16 02:29:07 PM PDT 24
Peak memory 202276 kb
Host smart-0751044b-b35d-40b3-9b1b-c1849c2e048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072379575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2072379575
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3041597244
Short name T12
Test name
Test status
Simulation time 164945466957 ps
CPU time 30.85 seconds
Started Apr 16 02:27:01 PM PDT 24
Finished Apr 16 02:27:33 PM PDT 24
Peak memory 202220 kb
Host smart-4e1b8666-71fb-4780-b759-e08a1fa0ff34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041597244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3041597244
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.567839759
Short name T290
Test name
Test status
Simulation time 507376888897 ps
CPU time 300.86 seconds
Started Apr 16 02:24:16 PM PDT 24
Finished Apr 16 02:29:18 PM PDT 24
Peak memory 202344 kb
Host smart-ba476799-e941-42cf-88c1-4d75307cb30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567839759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.567839759
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.287033775
Short name T9
Test name
Test status
Simulation time 336069270084 ps
CPU time 440.21 seconds
Started Apr 16 02:26:31 PM PDT 24
Finished Apr 16 02:33:51 PM PDT 24
Peak memory 202316 kb
Host smart-fcccfe47-6f52-4764-914c-a49fcb401afa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287033775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.287033775
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2801001551
Short name T227
Test name
Test status
Simulation time 411206831549 ps
CPU time 949.64 seconds
Started Apr 16 02:22:06 PM PDT 24
Finished Apr 16 02:37:56 PM PDT 24
Peak memory 202468 kb
Host smart-2ed3bdb0-477b-4bf9-a2aa-831f56f34cf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801001551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2801001551
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2436378184
Short name T159
Test name
Test status
Simulation time 496747005066 ps
CPU time 585.69 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:30:57 PM PDT 24
Peak memory 202244 kb
Host smart-5718da1a-e695-4329-885d-66c1bdf93c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436378184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2436378184
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3697611957
Short name T193
Test name
Test status
Simulation time 333209553298 ps
CPU time 79.01 seconds
Started Apr 16 02:23:23 PM PDT 24
Finished Apr 16 02:24:43 PM PDT 24
Peak memory 202344 kb
Host smart-a93f1429-e0ee-44f4-aaa4-a1aba65de944
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697611957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3697611957
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1455720998
Short name T256
Test name
Test status
Simulation time 535042216874 ps
CPU time 315.55 seconds
Started Apr 16 02:20:46 PM PDT 24
Finished Apr 16 02:26:02 PM PDT 24
Peak memory 202248 kb
Host smart-0b76bc2f-03f5-4ecf-80dc-a81d84d3d2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455720998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1455720998
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2410757074
Short name T212
Test name
Test status
Simulation time 565651353287 ps
CPU time 588.8 seconds
Started Apr 16 02:21:26 PM PDT 24
Finished Apr 16 02:31:16 PM PDT 24
Peak memory 202284 kb
Host smart-4f9cb00f-21af-4f85-9998-e0688161b2e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410757074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2410757074
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3719290730
Short name T245
Test name
Test status
Simulation time 359320306337 ps
CPU time 144.29 seconds
Started Apr 16 02:25:37 PM PDT 24
Finished Apr 16 02:28:02 PM PDT 24
Peak memory 202204 kb
Host smart-14eff89d-5aa5-4d2c-a2e2-5ee335c930ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719290730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3719290730
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1152876078
Short name T176
Test name
Test status
Simulation time 491098200287 ps
CPU time 283.01 seconds
Started Apr 16 02:22:16 PM PDT 24
Finished Apr 16 02:27:00 PM PDT 24
Peak memory 202208 kb
Host smart-b8c083f7-7644-4d9d-bb5f-f40d8fa7dae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152876078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1152876078
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1332651611
Short name T33
Test name
Test status
Simulation time 121209511956 ps
CPU time 144.07 seconds
Started Apr 16 02:25:40 PM PDT 24
Finished Apr 16 02:28:05 PM PDT 24
Peak memory 202448 kb
Host smart-120c9cbb-92a9-4e1e-bb0c-7fd8ae068fc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332651611 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1332651611
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3268280250
Short name T89
Test name
Test status
Simulation time 4216394128 ps
CPU time 6.14 seconds
Started Apr 16 02:17:56 PM PDT 24
Finished Apr 16 02:18:03 PM PDT 24
Peak memory 201484 kb
Host smart-b4562a09-41ea-4135-97c2-9d80fe19103d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268280250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3268280250
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1061085756
Short name T263
Test name
Test status
Simulation time 509445042320 ps
CPU time 602.24 seconds
Started Apr 16 02:21:03 PM PDT 24
Finished Apr 16 02:31:06 PM PDT 24
Peak memory 202216 kb
Host smart-93c0273d-5b61-4fa4-88c4-247b94ca9148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061085756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1061085756
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4099407560
Short name T139
Test name
Test status
Simulation time 503566431 ps
CPU time 1.08 seconds
Started Apr 16 02:17:11 PM PDT 24
Finished Apr 16 02:17:13 PM PDT 24
Peak memory 201244 kb
Host smart-f10e1639-ca1f-447b-b9b9-e0edab0da372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099407560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4099407560
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2944186307
Short name T261
Test name
Test status
Simulation time 343935029130 ps
CPU time 421.84 seconds
Started Apr 16 02:25:42 PM PDT 24
Finished Apr 16 02:32:45 PM PDT 24
Peak memory 202256 kb
Host smart-2b760610-63f8-4b17-825a-d33b357c32f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944186307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2944186307
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.988382452
Short name T232
Test name
Test status
Simulation time 366487164138 ps
CPU time 373.11 seconds
Started Apr 16 02:23:11 PM PDT 24
Finished Apr 16 02:29:25 PM PDT 24
Peak memory 202268 kb
Host smart-d28363bf-eeb3-415a-a377-795dba7590a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988382452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.988382452
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3528423191
Short name T215
Test name
Test status
Simulation time 665239688353 ps
CPU time 173.72 seconds
Started Apr 16 02:24:52 PM PDT 24
Finished Apr 16 02:27:46 PM PDT 24
Peak memory 202216 kb
Host smart-3f344a94-3e63-4be6-a2b9-31b3746f4231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528423191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3528423191
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.225611920
Short name T21
Test name
Test status
Simulation time 337474622922 ps
CPU time 682.67 seconds
Started Apr 16 02:24:41 PM PDT 24
Finished Apr 16 02:36:04 PM PDT 24
Peak memory 218964 kb
Host smart-4aab4a4b-96ac-41d0-88b7-99fce61db7c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225611920 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.225611920
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2051671793
Short name T228
Test name
Test status
Simulation time 169070989627 ps
CPU time 381.69 seconds
Started Apr 16 02:27:11 PM PDT 24
Finished Apr 16 02:33:34 PM PDT 24
Peak memory 202312 kb
Host smart-83cbed52-5883-4731-810b-3f937b615ec3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051671793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2051671793
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3928091778
Short name T320
Test name
Test status
Simulation time 178271666934 ps
CPU time 118.57 seconds
Started Apr 16 02:27:24 PM PDT 24
Finished Apr 16 02:29:23 PM PDT 24
Peak memory 202228 kb
Host smart-b56a1f27-8830-4b45-ad18-a3a8919b2e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928091778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3928091778
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2837883084
Short name T280
Test name
Test status
Simulation time 516281530136 ps
CPU time 410.42 seconds
Started Apr 16 02:24:27 PM PDT 24
Finished Apr 16 02:31:18 PM PDT 24
Peak memory 202268 kb
Host smart-f9fbcf84-9d95-4c7a-a723-747087a730c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837883084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2837883084
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2415982454
Short name T268
Test name
Test status
Simulation time 495566363028 ps
CPU time 320.01 seconds
Started Apr 16 02:21:50 PM PDT 24
Finished Apr 16 02:27:11 PM PDT 24
Peak memory 202252 kb
Host smart-4b36f955-4d03-4049-b6f5-45610eb3c265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415982454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2415982454
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3190520050
Short name T121
Test name
Test status
Simulation time 496196480992 ps
CPU time 1141.87 seconds
Started Apr 16 02:21:47 PM PDT 24
Finished Apr 16 02:40:50 PM PDT 24
Peak memory 202180 kb
Host smart-7b02eb6e-4d2c-40dd-8915-0a3aed3f6768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190520050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3190520050
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2291540975
Short name T132
Test name
Test status
Simulation time 324430486243 ps
CPU time 690.92 seconds
Started Apr 16 02:22:56 PM PDT 24
Finished Apr 16 02:34:28 PM PDT 24
Peak memory 202180 kb
Host smart-590d7fc3-d8c9-4d33-a0ee-e54443bbefb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291540975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2291540975
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.979212755
Short name T258
Test name
Test status
Simulation time 377440331692 ps
CPU time 827.09 seconds
Started Apr 16 02:21:04 PM PDT 24
Finished Apr 16 02:34:53 PM PDT 24
Peak memory 202244 kb
Host smart-d985bb05-2f4c-462e-bdae-da5880d3c4d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979212755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.979212755
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2735033262
Short name T275
Test name
Test status
Simulation time 481604327998 ps
CPU time 317.46 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:26:30 PM PDT 24
Peak memory 202280 kb
Host smart-590254b3-9aed-475d-b15b-4e1a1e590057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735033262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2735033262
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3186431662
Short name T96
Test name
Test status
Simulation time 8649621711 ps
CPU time 8.01 seconds
Started Apr 16 02:18:06 PM PDT 24
Finished Apr 16 02:18:15 PM PDT 24
Peak memory 201544 kb
Host smart-2335df29-cc48-4056-9383-727b8b79dec4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186431662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3186431662
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.4051525878
Short name T385
Test name
Test status
Simulation time 330028679932 ps
CPU time 189.62 seconds
Started Apr 16 02:21:29 PM PDT 24
Finished Apr 16 02:24:39 PM PDT 24
Peak memory 202216 kb
Host smart-34150e94-3ffa-4192-8246-fb8cfcaba663
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051525878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.4051525878
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1828045454
Short name T272
Test name
Test status
Simulation time 365296413595 ps
CPU time 922.98 seconds
Started Apr 16 02:22:16 PM PDT 24
Finished Apr 16 02:37:40 PM PDT 24
Peak memory 202248 kb
Host smart-56b267ae-b15e-4c04-8d4b-89bf5a88b5a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828045454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1828045454
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.652270869
Short name T278
Test name
Test status
Simulation time 539528353823 ps
CPU time 1347.67 seconds
Started Apr 16 02:21:17 PM PDT 24
Finished Apr 16 02:43:46 PM PDT 24
Peak memory 202232 kb
Host smart-27cfa805-4b9f-4c1a-8ebc-eb0d18f6ab52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652270869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.652270869
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3063352731
Short name T373
Test name
Test status
Simulation time 124297682471 ps
CPU time 408.58 seconds
Started Apr 16 02:21:37 PM PDT 24
Finished Apr 16 02:28:27 PM PDT 24
Peak memory 202552 kb
Host smart-e5216d20-1c6c-41c9-8a22-dfbdf52c5bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063352731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3063352731
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.204182797
Short name T260
Test name
Test status
Simulation time 139238258201 ps
CPU time 77.85 seconds
Started Apr 16 02:20:49 PM PDT 24
Finished Apr 16 02:22:08 PM PDT 24
Peak memory 210872 kb
Host smart-29c8f030-60b2-4480-b186-95b8ad4d396e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204182797 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.204182797
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.625276860
Short name T265
Test name
Test status
Simulation time 27341419540 ps
CPU time 78.53 seconds
Started Apr 16 02:24:32 PM PDT 24
Finished Apr 16 02:25:52 PM PDT 24
Peak memory 210968 kb
Host smart-fed05bef-8c9e-4c70-bcb7-b6d0263e078e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625276860 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.625276860
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.908196274
Short name T340
Test name
Test status
Simulation time 162164432426 ps
CPU time 352.02 seconds
Started Apr 16 02:20:54 PM PDT 24
Finished Apr 16 02:26:46 PM PDT 24
Peak memory 202276 kb
Host smart-f48fcec0-7631-431d-9edf-e67d4a749653
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908196274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.908196274
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2799840249
Short name T236
Test name
Test status
Simulation time 126847474175 ps
CPU time 165.31 seconds
Started Apr 16 02:26:36 PM PDT 24
Finished Apr 16 02:29:22 PM PDT 24
Peak memory 218848 kb
Host smart-c66760f9-e505-4a75-a870-861f952a4b02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799840249 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2799840249
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.295914907
Short name T81
Test name
Test status
Simulation time 411558459 ps
CPU time 2.21 seconds
Started Apr 16 02:17:59 PM PDT 24
Finished Apr 16 02:18:02 PM PDT 24
Peak memory 201520 kb
Host smart-3db556ee-1c0c-44ff-bedb-d3ca5d073ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295914907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.295914907
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1406713945
Short name T352
Test name
Test status
Simulation time 143096084765 ps
CPU time 705.92 seconds
Started Apr 16 02:21:44 PM PDT 24
Finished Apr 16 02:33:32 PM PDT 24
Peak memory 202632 kb
Host smart-aa4320d7-03b3-43aa-9b33-94c76e86eb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406713945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1406713945
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3204929721
Short name T328
Test name
Test status
Simulation time 335862568741 ps
CPU time 186.51 seconds
Started Apr 16 02:20:45 PM PDT 24
Finished Apr 16 02:23:52 PM PDT 24
Peak memory 202228 kb
Host smart-4222e543-0ad3-4017-b555-d1160bcc7ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204929721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3204929721
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4141148497
Short name T206
Test name
Test status
Simulation time 489721027234 ps
CPU time 303.59 seconds
Started Apr 16 02:23:42 PM PDT 24
Finished Apr 16 02:28:46 PM PDT 24
Peak memory 202224 kb
Host smart-dcda2813-2c9f-48d2-ab2b-d3e74a3e801a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141148497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4141148497
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.107070607
Short name T357
Test name
Test status
Simulation time 134718508847 ps
CPU time 693.76 seconds
Started Apr 16 02:25:34 PM PDT 24
Finished Apr 16 02:37:09 PM PDT 24
Peak memory 202648 kb
Host smart-2c16dbbf-3218-4d13-a48b-7599c1851b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107070607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.107070607
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3085619195
Short name T32
Test name
Test status
Simulation time 304529624804 ps
CPU time 422.31 seconds
Started Apr 16 02:26:08 PM PDT 24
Finished Apr 16 02:33:11 PM PDT 24
Peak memory 210880 kb
Host smart-eb729328-2448-4684-8322-0a217c75c984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085619195 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3085619195
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3186514709
Short name T242
Test name
Test status
Simulation time 653949313215 ps
CPU time 1577.16 seconds
Started Apr 16 02:26:53 PM PDT 24
Finished Apr 16 02:53:12 PM PDT 24
Peak memory 202260 kb
Host smart-1e807020-de1d-4d4c-8936-2329aabb602a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186514709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3186514709
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.4004432446
Short name T257
Test name
Test status
Simulation time 329627862665 ps
CPU time 385.88 seconds
Started Apr 16 02:20:39 PM PDT 24
Finished Apr 16 02:27:06 PM PDT 24
Peak memory 202308 kb
Host smart-4c81d7fc-7f2a-49d1-b4e3-685f6fd5e946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004432446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.4004432446
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2464360417
Short name T164
Test name
Test status
Simulation time 353361254242 ps
CPU time 848.53 seconds
Started Apr 16 02:21:23 PM PDT 24
Finished Apr 16 02:35:32 PM PDT 24
Peak memory 202216 kb
Host smart-3bae5427-bbd2-4e85-9b50-ff142ad3c511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464360417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2464360417
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.605939965
Short name T337
Test name
Test status
Simulation time 127211939092 ps
CPU time 50.87 seconds
Started Apr 16 02:21:23 PM PDT 24
Finished Apr 16 02:22:14 PM PDT 24
Peak memory 211564 kb
Host smart-645b4e11-0704-4193-8ecf-65a7655a9f53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605939965 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.605939965
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2686945006
Short name T331
Test name
Test status
Simulation time 517456238767 ps
CPU time 1228.92 seconds
Started Apr 16 02:21:41 PM PDT 24
Finished Apr 16 02:42:12 PM PDT 24
Peak memory 202208 kb
Host smart-eba16a9a-7bfa-4fbe-af9f-1ebd7466ea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686945006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2686945006
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3119255500
Short name T316
Test name
Test status
Simulation time 165566486976 ps
CPU time 101.07 seconds
Started Apr 16 02:26:59 PM PDT 24
Finished Apr 16 02:28:41 PM PDT 24
Peak memory 202296 kb
Host smart-6ba041cb-e72e-4824-9733-01144e16496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119255500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3119255500
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2097584474
Short name T48
Test name
Test status
Simulation time 43724072799 ps
CPU time 92.83 seconds
Started Apr 16 02:27:23 PM PDT 24
Finished Apr 16 02:28:56 PM PDT 24
Peak memory 202368 kb
Host smart-3f26b86b-d573-4f7d-ae81-e34a818b7a94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097584474 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2097584474
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2032336997
Short name T341
Test name
Test status
Simulation time 427394789816 ps
CPU time 238.9 seconds
Started Apr 16 02:20:41 PM PDT 24
Finished Apr 16 02:24:40 PM PDT 24
Peak memory 202260 kb
Host smart-98cfe723-32b9-4cf4-8255-9879533b13b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032336997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2032336997
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1660601087
Short name T45
Test name
Test status
Simulation time 115842805984 ps
CPU time 519.18 seconds
Started Apr 16 02:21:16 PM PDT 24
Finished Apr 16 02:29:56 PM PDT 24
Peak memory 202560 kb
Host smart-745a9abd-e7f0-4c61-b828-ccb8fdcacb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660601087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1660601087
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.846694706
Short name T161
Test name
Test status
Simulation time 356406954942 ps
CPU time 114.73 seconds
Started Apr 16 02:21:15 PM PDT 24
Finished Apr 16 02:23:10 PM PDT 24
Peak memory 202316 kb
Host smart-d96ed7c4-f0b7-4eed-ac25-4024662dd3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846694706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
846694706
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1753978925
Short name T283
Test name
Test status
Simulation time 45886180672 ps
CPU time 168.51 seconds
Started Apr 16 02:21:15 PM PDT 24
Finished Apr 16 02:24:05 PM PDT 24
Peak memory 211000 kb
Host smart-f18d2400-7a1c-4dab-bfc9-6d111e1088c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753978925 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1753978925
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2538544383
Short name T292
Test name
Test status
Simulation time 166286318695 ps
CPU time 82.87 seconds
Started Apr 16 02:21:12 PM PDT 24
Finished Apr 16 02:22:36 PM PDT 24
Peak memory 202264 kb
Host smart-b6728cd5-eb45-4291-ba9c-d6a347983b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538544383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2538544383
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3112597118
Short name T209
Test name
Test status
Simulation time 336405127663 ps
CPU time 194.08 seconds
Started Apr 16 02:21:41 PM PDT 24
Finished Apr 16 02:24:57 PM PDT 24
Peak memory 202300 kb
Host smart-3354d31a-1cf9-4a13-abce-a11044158957
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112597118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3112597118
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.618382057
Short name T363
Test name
Test status
Simulation time 539065975492 ps
CPU time 536.71 seconds
Started Apr 16 02:21:45 PM PDT 24
Finished Apr 16 02:30:43 PM PDT 24
Peak memory 202612 kb
Host smart-8e2854e9-b93d-4231-930f-7d8caa119974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618382057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
618382057
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2568508522
Short name T276
Test name
Test status
Simulation time 575312284702 ps
CPU time 681.59 seconds
Started Apr 16 02:21:44 PM PDT 24
Finished Apr 16 02:33:07 PM PDT 24
Peak memory 202284 kb
Host smart-ba521145-a4a3-4bc6-8b4e-bb9814f6fb9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568508522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2568508522
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.134266710
Short name T249
Test name
Test status
Simulation time 442225760494 ps
CPU time 1257.19 seconds
Started Apr 16 02:21:49 PM PDT 24
Finished Apr 16 02:42:47 PM PDT 24
Peak memory 210756 kb
Host smart-daeb9cc2-9c77-461d-86a3-3bb5da48eb13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134266710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
134266710
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2669976772
Short name T315
Test name
Test status
Simulation time 490391468142 ps
CPU time 292.8 seconds
Started Apr 16 02:22:24 PM PDT 24
Finished Apr 16 02:27:17 PM PDT 24
Peak memory 202220 kb
Host smart-3350bfa2-ebd5-4aa2-8e0d-932554d5fda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669976772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2669976772
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.526057024
Short name T296
Test name
Test status
Simulation time 433766575804 ps
CPU time 269.02 seconds
Started Apr 16 02:22:41 PM PDT 24
Finished Apr 16 02:27:11 PM PDT 24
Peak memory 202352 kb
Host smart-bd9aa9bf-6296-47ae-96f8-e6d3a773bf83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526057024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.526057024
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3236183317
Short name T348
Test name
Test status
Simulation time 126646298004 ps
CPU time 431.68 seconds
Started Apr 16 02:24:42 PM PDT 24
Finished Apr 16 02:31:54 PM PDT 24
Peak memory 202600 kb
Host smart-a0e3c081-f6fd-4084-ab01-7ee1f8e32fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236183317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3236183317
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.932331250
Short name T241
Test name
Test status
Simulation time 330275372653 ps
CPU time 207.5 seconds
Started Apr 16 02:24:57 PM PDT 24
Finished Apr 16 02:28:25 PM PDT 24
Peak memory 202296 kb
Host smart-0ce3eeb3-74c7-4f5d-b094-8ff35ec6da39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932331250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.932331250
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.865848814
Short name T31
Test name
Test status
Simulation time 596555690559 ps
CPU time 1398.23 seconds
Started Apr 16 02:25:13 PM PDT 24
Finished Apr 16 02:48:32 PM PDT 24
Peak memory 202328 kb
Host smart-fbd639c3-42fb-48c5-9e87-54ec9324d8d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865848814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.865848814
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3439386539
Short name T362
Test name
Test status
Simulation time 94244061576 ps
CPU time 303.45 seconds
Started Apr 16 02:25:50 PM PDT 24
Finished Apr 16 02:30:54 PM PDT 24
Peak memory 202576 kb
Host smart-73651def-4cb2-4308-ac56-1058976223f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439386539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3439386539
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2261392178
Short name T282
Test name
Test status
Simulation time 159675826005 ps
CPU time 64.06 seconds
Started Apr 16 02:26:58 PM PDT 24
Finished Apr 16 02:28:03 PM PDT 24
Peak memory 202256 kb
Host smart-4e7022d8-5791-408b-8ff1-88c21517eb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261392178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2261392178
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2681098872
Short name T333
Test name
Test status
Simulation time 518456074955 ps
CPU time 203.76 seconds
Started Apr 16 02:27:12 PM PDT 24
Finished Apr 16 02:30:36 PM PDT 24
Peak memory 202284 kb
Host smart-404741a5-de1c-4e39-bc13-618a5946e509
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681098872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2681098872
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1349564319
Short name T210
Test name
Test status
Simulation time 547397134145 ps
CPU time 331.55 seconds
Started Apr 16 02:27:47 PM PDT 24
Finished Apr 16 02:33:20 PM PDT 24
Peak memory 202204 kb
Host smart-18de35d1-ec58-43d9-b8a3-b550415009f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349564319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1349564319
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3311995855
Short name T217
Test name
Test status
Simulation time 491714639805 ps
CPU time 1241.68 seconds
Started Apr 16 02:27:41 PM PDT 24
Finished Apr 16 02:48:24 PM PDT 24
Peak memory 202212 kb
Host smart-279eb230-9292-409c-b2d1-5acc9770f8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311995855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3311995855
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1025670786
Short name T216
Test name
Test status
Simulation time 288615582364 ps
CPU time 325.75 seconds
Started Apr 16 02:27:44 PM PDT 24
Finished Apr 16 02:33:11 PM PDT 24
Peak memory 210864 kb
Host smart-2730efcd-82aa-45f4-bfc8-3d944c2ab1e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025670786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1025670786
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2142504711
Short name T143
Test name
Test status
Simulation time 1146293365 ps
CPU time 2.88 seconds
Started Apr 16 02:17:10 PM PDT 24
Finished Apr 16 02:17:14 PM PDT 24
Peak memory 201376 kb
Host smart-b630d5a9-1443-41be-ac27-490d0f6c6250
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142504711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2142504711
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1916456223
Short name T147
Test name
Test status
Simulation time 51562580913 ps
CPU time 111.02 seconds
Started Apr 16 02:17:10 PM PDT 24
Finished Apr 16 02:19:02 PM PDT 24
Peak memory 201476 kb
Host smart-05cf3c36-cddf-4562-809b-90c7dac285c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916456223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1916456223
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1680398196
Short name T136
Test name
Test status
Simulation time 1028044363 ps
CPU time 2.05 seconds
Started Apr 16 02:17:10 PM PDT 24
Finished Apr 16 02:17:13 PM PDT 24
Peak memory 201216 kb
Host smart-57b52150-1dbf-428b-986a-4117c82298a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680398196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1680398196
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1467371722
Short name T839
Test name
Test status
Simulation time 353731836 ps
CPU time 1.63 seconds
Started Apr 16 02:17:16 PM PDT 24
Finished Apr 16 02:17:18 PM PDT 24
Peak memory 201216 kb
Host smart-18411e01-7ac7-46e2-ae97-d493e7e2a45e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467371722 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1467371722
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1655048513
Short name T907
Test name
Test status
Simulation time 302663150 ps
CPU time 0.98 seconds
Started Apr 16 02:17:07 PM PDT 24
Finished Apr 16 02:17:08 PM PDT 24
Peak memory 201224 kb
Host smart-e0e000a2-047b-4025-bf45-37c9ac4df2df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655048513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1655048513
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3269013948
Short name T822
Test name
Test status
Simulation time 3967272090 ps
CPU time 10.27 seconds
Started Apr 16 02:17:10 PM PDT 24
Finished Apr 16 02:17:21 PM PDT 24
Peak memory 201492 kb
Host smart-6a34777a-2df3-4599-9796-bc17bede3f00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269013948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3269013948
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1020039203
Short name T906
Test name
Test status
Simulation time 460011087 ps
CPU time 3.67 seconds
Started Apr 16 02:17:08 PM PDT 24
Finished Apr 16 02:17:12 PM PDT 24
Peak memory 201460 kb
Host smart-5d5ae810-44d2-4334-aa90-164043810dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020039203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1020039203
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.876093438
Short name T95
Test name
Test status
Simulation time 7947062752 ps
CPU time 7 seconds
Started Apr 16 02:17:07 PM PDT 24
Finished Apr 16 02:17:14 PM PDT 24
Peak memory 201456 kb
Host smart-c77974df-9078-4a1f-82b2-f07dc56bb773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876093438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.876093438
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4040685089
Short name T883
Test name
Test status
Simulation time 1273001110 ps
CPU time 3.14 seconds
Started Apr 16 02:17:21 PM PDT 24
Finished Apr 16 02:17:25 PM PDT 24
Peak memory 201628 kb
Host smart-6a5f1bde-b7dc-464a-8ecd-d7e880498fb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040685089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4040685089
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1950050417
Short name T878
Test name
Test status
Simulation time 53275618936 ps
CPU time 69.74 seconds
Started Apr 16 02:17:19 PM PDT 24
Finished Apr 16 02:18:29 PM PDT 24
Peak memory 201528 kb
Host smart-6c3620e1-f781-45e1-b9c7-b4220460e384
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950050417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1950050417
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4277653588
Short name T149
Test name
Test status
Simulation time 1266638091 ps
CPU time 2.33 seconds
Started Apr 16 02:17:19 PM PDT 24
Finished Apr 16 02:17:22 PM PDT 24
Peak memory 201236 kb
Host smart-8f5f8178-5c7c-4a70-86be-af2bce834530
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277653588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.4277653588
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.866995600
Short name T827
Test name
Test status
Simulation time 553765400 ps
CPU time 2.04 seconds
Started Apr 16 02:17:19 PM PDT 24
Finished Apr 16 02:17:22 PM PDT 24
Peak memory 201332 kb
Host smart-bd86b207-a203-45ef-aca0-143a303edd70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866995600 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.866995600
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.562579901
Short name T874
Test name
Test status
Simulation time 370393183 ps
CPU time 1.03 seconds
Started Apr 16 02:17:20 PM PDT 24
Finished Apr 16 02:17:22 PM PDT 24
Peak memory 201208 kb
Host smart-375add19-4c5e-4208-be48-65443a6efe70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562579901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.562579901
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1019552671
Short name T804
Test name
Test status
Simulation time 348533796 ps
CPU time 0.87 seconds
Started Apr 16 02:17:14 PM PDT 24
Finished Apr 16 02:17:16 PM PDT 24
Peak memory 201252 kb
Host smart-7ccce9f3-af01-4683-aef6-7aa62452b386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019552671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1019552671
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2446149521
Short name T865
Test name
Test status
Simulation time 2582761300 ps
CPU time 3.83 seconds
Started Apr 16 02:17:19 PM PDT 24
Finished Apr 16 02:17:24 PM PDT 24
Peak memory 201284 kb
Host smart-7c6466f0-caf4-42ec-b7a1-f09e290c0415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446149521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2446149521
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.627582080
Short name T908
Test name
Test status
Simulation time 658341350 ps
CPU time 1.5 seconds
Started Apr 16 02:17:14 PM PDT 24
Finished Apr 16 02:17:15 PM PDT 24
Peak memory 201532 kb
Host smart-6f74cb4c-8434-4df6-ae73-889672857f74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627582080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.627582080
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.321183579
Short name T870
Test name
Test status
Simulation time 4659870974 ps
CPU time 4.52 seconds
Started Apr 16 02:17:13 PM PDT 24
Finished Apr 16 02:17:18 PM PDT 24
Peak memory 201512 kb
Host smart-afa44181-8a59-4b54-9082-c9a744fb03a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321183579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.321183579
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.301728108
Short name T909
Test name
Test status
Simulation time 529976050 ps
CPU time 0.98 seconds
Started Apr 16 02:17:57 PM PDT 24
Finished Apr 16 02:17:59 PM PDT 24
Peak memory 201300 kb
Host smart-ce92c3ef-f618-4778-bca9-37d40e9e7ff0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301728108 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.301728108
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1092481135
Short name T832
Test name
Test status
Simulation time 398142452 ps
CPU time 1.68 seconds
Started Apr 16 02:17:58 PM PDT 24
Finished Apr 16 02:18:00 PM PDT 24
Peak memory 201204 kb
Host smart-65e33e91-c4e8-4a08-aca3-0945319751fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092481135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1092481135
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.812798849
Short name T808
Test name
Test status
Simulation time 334112654 ps
CPU time 1.39 seconds
Started Apr 16 02:17:57 PM PDT 24
Finished Apr 16 02:17:59 PM PDT 24
Peak memory 201256 kb
Host smart-d2db0fac-30d3-4880-9568-4376f058fcf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812798849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.812798849
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4164905465
Short name T836
Test name
Test status
Simulation time 2861773051 ps
CPU time 4.5 seconds
Started Apr 16 02:17:59 PM PDT 24
Finished Apr 16 02:18:04 PM PDT 24
Peak memory 201204 kb
Host smart-ac319962-d2ef-4d4d-a488-85c3e5ce6c1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164905465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.4164905465
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2476011342
Short name T847
Test name
Test status
Simulation time 665098249 ps
CPU time 1.42 seconds
Started Apr 16 02:17:59 PM PDT 24
Finished Apr 16 02:18:01 PM PDT 24
Peak memory 201556 kb
Host smart-177fdbaa-5dfa-4941-a5ed-19d011e56ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476011342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2476011342
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.519196871
Short name T872
Test name
Test status
Simulation time 8141373900 ps
CPU time 12.6 seconds
Started Apr 16 02:17:57 PM PDT 24
Finished Apr 16 02:18:10 PM PDT 24
Peak memory 201456 kb
Host smart-27449dd8-7b83-4309-b6f2-e62fc11782fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519196871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.519196871
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4068984742
Short name T890
Test name
Test status
Simulation time 666010615 ps
CPU time 1.28 seconds
Started Apr 16 02:17:57 PM PDT 24
Finished Apr 16 02:17:59 PM PDT 24
Peak memory 209728 kb
Host smart-d8086eff-0e28-4354-96df-0e8951fa9281
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068984742 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.4068984742
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4276960498
Short name T869
Test name
Test status
Simulation time 566618009 ps
CPU time 1.15 seconds
Started Apr 16 02:17:57 PM PDT 24
Finished Apr 16 02:17:59 PM PDT 24
Peak memory 201208 kb
Host smart-251f7528-7dfc-40fb-9995-541f377130a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276960498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.4276960498
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3828024478
Short name T805
Test name
Test status
Simulation time 283949813 ps
CPU time 1.27 seconds
Started Apr 16 02:17:58 PM PDT 24
Finished Apr 16 02:18:00 PM PDT 24
Peak memory 201236 kb
Host smart-c42cd429-5c7a-43c2-84b7-8c711c5f1822
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828024478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3828024478
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2420004634
Short name T864
Test name
Test status
Simulation time 4409835081 ps
CPU time 2.19 seconds
Started Apr 16 02:17:59 PM PDT 24
Finished Apr 16 02:18:02 PM PDT 24
Peak memory 201516 kb
Host smart-f2fba2d2-f735-4895-ad06-419860ca003b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420004634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2420004634
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1288893308
Short name T905
Test name
Test status
Simulation time 714927988 ps
CPU time 2.37 seconds
Started Apr 16 02:18:00 PM PDT 24
Finished Apr 16 02:18:03 PM PDT 24
Peak memory 201472 kb
Host smart-9348260e-f512-47f9-a1aa-9a6cbc1b32ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288893308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1288893308
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.715185478
Short name T900
Test name
Test status
Simulation time 480779948 ps
CPU time 2.09 seconds
Started Apr 16 02:18:03 PM PDT 24
Finished Apr 16 02:18:06 PM PDT 24
Peak memory 201268 kb
Host smart-a8d02653-3ce4-4e64-abca-7d5a619ac830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715185478 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.715185478
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.737217443
Short name T154
Test name
Test status
Simulation time 440570572 ps
CPU time 0.97 seconds
Started Apr 16 02:18:01 PM PDT 24
Finished Apr 16 02:18:03 PM PDT 24
Peak memory 201240 kb
Host smart-d572e0df-0d48-4d93-ae5b-9e2287d8ae06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737217443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.737217443
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.4277433146
Short name T826
Test name
Test status
Simulation time 302544976 ps
CPU time 0.81 seconds
Started Apr 16 02:18:02 PM PDT 24
Finished Apr 16 02:18:04 PM PDT 24
Peak memory 201252 kb
Host smart-4641d4b3-fb82-4d04-be61-bdd111070c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277433146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.4277433146
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.306097706
Short name T150
Test name
Test status
Simulation time 2429923714 ps
CPU time 2.29 seconds
Started Apr 16 02:18:02 PM PDT 24
Finished Apr 16 02:18:05 PM PDT 24
Peak memory 201284 kb
Host smart-2a1de14f-80cf-4915-99da-5e3883719538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306097706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.306097706
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3763752514
Short name T346
Test name
Test status
Simulation time 8090730375 ps
CPU time 20.39 seconds
Started Apr 16 02:17:59 PM PDT 24
Finished Apr 16 02:18:20 PM PDT 24
Peak memory 201476 kb
Host smart-f6993696-d9c1-4587-a238-620febe202a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763752514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3763752514
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3735162209
Short name T833
Test name
Test status
Simulation time 446826763 ps
CPU time 1.88 seconds
Started Apr 16 02:18:12 PM PDT 24
Finished Apr 16 02:18:14 PM PDT 24
Peak memory 201288 kb
Host smart-410fc3b8-dc8a-45e7-b4e6-8ccc98186a8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735162209 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3735162209
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2974582524
Short name T148
Test name
Test status
Simulation time 572869633 ps
CPU time 1.56 seconds
Started Apr 16 02:18:06 PM PDT 24
Finished Apr 16 02:18:08 PM PDT 24
Peak memory 201268 kb
Host smart-5abe54c8-75e5-4907-8eb7-6cce6cec22fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974582524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2974582524
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.173109368
Short name T806
Test name
Test status
Simulation time 429051793 ps
CPU time 1.11 seconds
Started Apr 16 02:18:02 PM PDT 24
Finished Apr 16 02:18:03 PM PDT 24
Peak memory 201240 kb
Host smart-211f5217-1f8f-4288-b9be-8d8e22d63b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173109368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.173109368
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.541588254
Short name T911
Test name
Test status
Simulation time 2712091935 ps
CPU time 11.27 seconds
Started Apr 16 02:18:06 PM PDT 24
Finished Apr 16 02:18:18 PM PDT 24
Peak memory 201316 kb
Host smart-e9c6dc83-4695-4370-956b-e09e90e3ab3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541588254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.541588254
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3083537465
Short name T895
Test name
Test status
Simulation time 1270500150 ps
CPU time 2.89 seconds
Started Apr 16 02:18:01 PM PDT 24
Finished Apr 16 02:18:04 PM PDT 24
Peak memory 210744 kb
Host smart-594876fb-49f8-4b52-9dff-4f83cfe3e015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083537465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3083537465
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2281583074
Short name T347
Test name
Test status
Simulation time 4123244204 ps
CPU time 6.84 seconds
Started Apr 16 02:18:00 PM PDT 24
Finished Apr 16 02:18:07 PM PDT 24
Peak memory 201512 kb
Host smart-22605542-6e28-48df-99e1-974da1395846
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281583074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2281583074
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3765923759
Short name T899
Test name
Test status
Simulation time 617924500 ps
CPU time 1.28 seconds
Started Apr 16 02:18:06 PM PDT 24
Finished Apr 16 02:18:08 PM PDT 24
Peak memory 201300 kb
Host smart-d1194d47-268f-4b13-bd0f-6bd319dd0b34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765923759 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3765923759
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1589909353
Short name T859
Test name
Test status
Simulation time 443312124 ps
CPU time 1.34 seconds
Started Apr 16 02:18:08 PM PDT 24
Finished Apr 16 02:18:10 PM PDT 24
Peak memory 201264 kb
Host smart-3ab2c3ff-b1f1-449b-8744-99ad81ba2961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589909353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1589909353
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3333799180
Short name T894
Test name
Test status
Simulation time 519188402 ps
CPU time 0.92 seconds
Started Apr 16 02:18:11 PM PDT 24
Finished Apr 16 02:18:12 PM PDT 24
Peak memory 201228 kb
Host smart-46b301f0-04ce-4880-964a-c3be06220bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333799180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3333799180
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.292207882
Short name T860
Test name
Test status
Simulation time 5201242275 ps
CPU time 3.69 seconds
Started Apr 16 02:18:06 PM PDT 24
Finished Apr 16 02:18:10 PM PDT 24
Peak memory 201448 kb
Host smart-f9885369-6c97-4173-ab97-2c4a22c6f1e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292207882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.292207882
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3874102668
Short name T856
Test name
Test status
Simulation time 454063804 ps
CPU time 3.15 seconds
Started Apr 16 02:18:06 PM PDT 24
Finished Apr 16 02:18:10 PM PDT 24
Peak memory 210752 kb
Host smart-91b173f2-68f6-4407-8f86-b6d5bc4d8086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874102668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3874102668
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.176021705
Short name T94
Test name
Test status
Simulation time 647209414 ps
CPU time 1.39 seconds
Started Apr 16 02:18:12 PM PDT 24
Finished Apr 16 02:18:14 PM PDT 24
Peak memory 201300 kb
Host smart-89fffa1a-9797-4547-a117-31a4c42be598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176021705 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.176021705
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3298892701
Short name T138
Test name
Test status
Simulation time 324975227 ps
CPU time 0.87 seconds
Started Apr 16 02:18:18 PM PDT 24
Finished Apr 16 02:18:20 PM PDT 24
Peak memory 201168 kb
Host smart-984c600e-a0d5-4a31-af91-12a35197a8ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298892701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3298892701
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1008536066
Short name T916
Test name
Test status
Simulation time 457803427 ps
CPU time 0.88 seconds
Started Apr 16 02:18:06 PM PDT 24
Finished Apr 16 02:18:07 PM PDT 24
Peak memory 201208 kb
Host smart-cd758103-7167-43ff-8ec7-9c59ae6c176f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008536066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1008536066
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.843442705
Short name T850
Test name
Test status
Simulation time 4794196392 ps
CPU time 6.25 seconds
Started Apr 16 02:18:12 PM PDT 24
Finished Apr 16 02:18:19 PM PDT 24
Peak memory 201464 kb
Host smart-5596f855-ecf0-46a2-a6a4-ebadd4f31e5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843442705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.843442705
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.34319164
Short name T873
Test name
Test status
Simulation time 490154095 ps
CPU time 2.64 seconds
Started Apr 16 02:18:06 PM PDT 24
Finished Apr 16 02:18:09 PM PDT 24
Peak memory 201560 kb
Host smart-50adaf62-064f-4fdb-b7d3-90e14fdcd481
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34319164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.34319164
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.394899947
Short name T73
Test name
Test status
Simulation time 8731634253 ps
CPU time 7.98 seconds
Started Apr 16 02:18:07 PM PDT 24
Finished Apr 16 02:18:15 PM PDT 24
Peak memory 201520 kb
Host smart-f8574498-6f59-4bff-8b40-97f3a10f02e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394899947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.394899947
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.750612107
Short name T821
Test name
Test status
Simulation time 480840045 ps
CPU time 1.64 seconds
Started Apr 16 02:18:11 PM PDT 24
Finished Apr 16 02:18:13 PM PDT 24
Peak memory 201304 kb
Host smart-4a3ae1ed-b5be-467b-a6ef-3ccbc2127b04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750612107 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.750612107
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.707770840
Short name T884
Test name
Test status
Simulation time 436931965 ps
CPU time 1.91 seconds
Started Apr 16 02:18:13 PM PDT 24
Finished Apr 16 02:18:15 PM PDT 24
Peak memory 201228 kb
Host smart-3b18cfb8-cab9-4025-852f-7d1ec20e597f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707770840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.707770840
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3651928930
Short name T849
Test name
Test status
Simulation time 470738366 ps
CPU time 1.73 seconds
Started Apr 16 02:18:09 PM PDT 24
Finished Apr 16 02:18:11 PM PDT 24
Peak memory 201252 kb
Host smart-9ea995ac-7985-4c50-ac98-c8313b9c6324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651928930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3651928930
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3847698965
Short name T68
Test name
Test status
Simulation time 4434181729 ps
CPU time 5.45 seconds
Started Apr 16 02:18:12 PM PDT 24
Finished Apr 16 02:18:18 PM PDT 24
Peak memory 201492 kb
Host smart-01924d97-4858-4061-ae49-0b76880f5b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847698965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3847698965
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1618229839
Short name T917
Test name
Test status
Simulation time 531745749 ps
CPU time 2.72 seconds
Started Apr 16 02:18:11 PM PDT 24
Finished Apr 16 02:18:14 PM PDT 24
Peak memory 201428 kb
Host smart-ab3f437a-2b9f-4023-b33e-08867f29d89b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618229839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1618229839
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1141115750
Short name T902
Test name
Test status
Simulation time 8271074309 ps
CPU time 7.99 seconds
Started Apr 16 02:18:11 PM PDT 24
Finished Apr 16 02:18:19 PM PDT 24
Peak memory 201488 kb
Host smart-38d8725c-ce0e-41ba-997f-04f651faa5ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141115750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1141115750
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2318557762
Short name T910
Test name
Test status
Simulation time 324726998 ps
CPU time 1.49 seconds
Started Apr 16 02:18:15 PM PDT 24
Finished Apr 16 02:18:17 PM PDT 24
Peak memory 201304 kb
Host smart-10dbcc06-5cef-4431-81b6-aab1c952ffd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318557762 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2318557762
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1178856477
Short name T144
Test name
Test status
Simulation time 409860996 ps
CPU time 1.66 seconds
Started Apr 16 02:18:14 PM PDT 24
Finished Apr 16 02:18:16 PM PDT 24
Peak memory 201224 kb
Host smart-98abbfd1-aab6-4de6-ba08-0c3e94f18129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178856477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1178856477
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2843130875
Short name T852
Test name
Test status
Simulation time 399086316 ps
CPU time 1.18 seconds
Started Apr 16 02:18:18 PM PDT 24
Finished Apr 16 02:18:20 PM PDT 24
Peak memory 201180 kb
Host smart-857fa6d4-5de9-4111-a37f-afb41d234acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843130875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2843130875
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.858940738
Short name T152
Test name
Test status
Simulation time 4905306258 ps
CPU time 6.21 seconds
Started Apr 16 02:18:16 PM PDT 24
Finished Apr 16 02:18:23 PM PDT 24
Peak memory 201456 kb
Host smart-66bccd08-6ee8-40bc-81e6-7a7b9e7816b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858940738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.858940738
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.221161684
Short name T90
Test name
Test status
Simulation time 458960958 ps
CPU time 3.76 seconds
Started Apr 16 02:18:11 PM PDT 24
Finished Apr 16 02:18:15 PM PDT 24
Peak memory 201508 kb
Host smart-98dede3b-0d38-4a92-890f-a7ee0e12f742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221161684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.221161684
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1165781773
Short name T841
Test name
Test status
Simulation time 8109769712 ps
CPU time 6.44 seconds
Started Apr 16 02:18:13 PM PDT 24
Finished Apr 16 02:18:19 PM PDT 24
Peak memory 201512 kb
Host smart-9787a99f-7b82-4bdd-9cbe-84bc976c2530
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165781773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1165781773
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1484843095
Short name T109
Test name
Test status
Simulation time 579837151 ps
CPU time 1.59 seconds
Started Apr 16 02:18:16 PM PDT 24
Finished Apr 16 02:18:18 PM PDT 24
Peak memory 201324 kb
Host smart-9d6979fe-f2de-4319-8a65-273b5e69784d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484843095 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1484843095
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1271291872
Short name T875
Test name
Test status
Simulation time 542570487 ps
CPU time 1.92 seconds
Started Apr 16 02:18:21 PM PDT 24
Finished Apr 16 02:18:24 PM PDT 24
Peak memory 201236 kb
Host smart-d8bd51e4-8ca6-4332-8abb-5cb6a7468998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271291872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1271291872
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.21821755
Short name T879
Test name
Test status
Simulation time 512334530 ps
CPU time 0.91 seconds
Started Apr 16 02:18:15 PM PDT 24
Finished Apr 16 02:18:16 PM PDT 24
Peak memory 201224 kb
Host smart-8e97f01c-24df-49f0-a6d7-8b5cd12e2214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21821755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.21821755
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2715021121
Short name T69
Test name
Test status
Simulation time 5014512879 ps
CPU time 11.25 seconds
Started Apr 16 02:18:20 PM PDT 24
Finished Apr 16 02:18:32 PM PDT 24
Peak memory 201476 kb
Host smart-4a00764f-771b-4b7d-a30a-caabb8c0fea3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715021121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2715021121
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1124133814
Short name T91
Test name
Test status
Simulation time 407159884 ps
CPU time 1.38 seconds
Started Apr 16 02:18:17 PM PDT 24
Finished Apr 16 02:18:19 PM PDT 24
Peak memory 201436 kb
Host smart-cfa5593f-8086-466a-99f5-ed9dcacc1017
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124133814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1124133814
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1938680621
Short name T92
Test name
Test status
Simulation time 7961574540 ps
CPU time 6.76 seconds
Started Apr 16 02:18:17 PM PDT 24
Finished Apr 16 02:18:24 PM PDT 24
Peak memory 201500 kb
Host smart-c816da2b-a463-4b32-a3e1-7351233ec7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938680621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1938680621
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1824240859
Short name T904
Test name
Test status
Simulation time 549685642 ps
CPU time 2.24 seconds
Started Apr 16 02:18:21 PM PDT 24
Finished Apr 16 02:18:24 PM PDT 24
Peak memory 201284 kb
Host smart-bd5f2851-a727-49a9-bbc2-4975ee05369b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824240859 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1824240859
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3078836721
Short name T882
Test name
Test status
Simulation time 458625475 ps
CPU time 1 seconds
Started Apr 16 02:18:24 PM PDT 24
Finished Apr 16 02:18:26 PM PDT 24
Peak memory 201244 kb
Host smart-c8780ed1-d902-4dae-a69c-08f7570c8bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078836721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3078836721
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1609601768
Short name T845
Test name
Test status
Simulation time 544738929 ps
CPU time 0.98 seconds
Started Apr 16 02:18:21 PM PDT 24
Finished Apr 16 02:18:23 PM PDT 24
Peak memory 201404 kb
Host smart-e178fabf-9a2f-400a-810a-7768972bb3b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609601768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1609601768
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3855075294
Short name T828
Test name
Test status
Simulation time 4454512054 ps
CPU time 4.03 seconds
Started Apr 16 02:18:21 PM PDT 24
Finished Apr 16 02:18:25 PM PDT 24
Peak memory 201420 kb
Host smart-dcc8f278-bfa9-49d4-b699-609e5cf015c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855075294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3855075294
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3446709511
Short name T896
Test name
Test status
Simulation time 769338806 ps
CPU time 2.12 seconds
Started Apr 16 02:18:14 PM PDT 24
Finished Apr 16 02:18:17 PM PDT 24
Peak memory 201488 kb
Host smart-e22f4f3b-43b3-4d7b-ad53-b8b94dcef653
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446709511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3446709511
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.467709883
Short name T77
Test name
Test status
Simulation time 7825740306 ps
CPU time 19.91 seconds
Started Apr 16 02:18:20 PM PDT 24
Finished Apr 16 02:18:41 PM PDT 24
Peak memory 201540 kb
Host smart-271501b8-20d9-4e60-b4de-d4cbea38c96a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467709883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.467709883
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2782647583
Short name T140
Test name
Test status
Simulation time 932316196 ps
CPU time 4.33 seconds
Started Apr 16 02:17:29 PM PDT 24
Finished Apr 16 02:17:34 PM PDT 24
Peak memory 201420 kb
Host smart-d663b6fb-bfff-4a06-a3be-98a9e083c7b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782647583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2782647583
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3528249566
Short name T146
Test name
Test status
Simulation time 22565560224 ps
CPU time 20.48 seconds
Started Apr 16 02:17:29 PM PDT 24
Finished Apr 16 02:17:50 PM PDT 24
Peak memory 201440 kb
Host smart-2ac42cd1-4fb6-44c1-9642-13afaa58f283
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528249566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3528249566
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2848419010
Short name T843
Test name
Test status
Simulation time 909281267 ps
CPU time 1.82 seconds
Started Apr 16 02:17:23 PM PDT 24
Finished Apr 16 02:17:25 PM PDT 24
Peak memory 201256 kb
Host smart-730f6923-4585-47da-8990-072c0d8755e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848419010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2848419010
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3453424594
Short name T855
Test name
Test status
Simulation time 740409671 ps
CPU time 1.29 seconds
Started Apr 16 02:17:33 PM PDT 24
Finished Apr 16 02:17:35 PM PDT 24
Peak memory 201300 kb
Host smart-dc78cd1f-21f5-4916-afbe-4345a48fa61d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453424594 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3453424594
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.44712094
Short name T840
Test name
Test status
Simulation time 447928746 ps
CPU time 1.19 seconds
Started Apr 16 02:17:28 PM PDT 24
Finished Apr 16 02:17:30 PM PDT 24
Peak memory 201212 kb
Host smart-a0246f7a-52ba-4457-a54c-77ba81667bd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44712094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.44712094
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.615561687
Short name T901
Test name
Test status
Simulation time 413439111 ps
CPU time 1.11 seconds
Started Apr 16 02:17:22 PM PDT 24
Finished Apr 16 02:17:24 PM PDT 24
Peak memory 201216 kb
Host smart-e479eed7-529e-4107-935c-73e40517c572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615561687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.615561687
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.629934246
Short name T70
Test name
Test status
Simulation time 2161985093 ps
CPU time 5.84 seconds
Started Apr 16 02:17:28 PM PDT 24
Finished Apr 16 02:17:34 PM PDT 24
Peak memory 201280 kb
Host smart-02176033-72cc-4968-a2f9-af26598470dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629934246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.629934246
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2809815616
Short name T84
Test name
Test status
Simulation time 553787965 ps
CPU time 2.62 seconds
Started Apr 16 02:17:21 PM PDT 24
Finished Apr 16 02:17:24 PM PDT 24
Peak memory 201716 kb
Host smart-7b0f4193-1c3d-48b4-ba5a-123c4f10b464
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809815616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2809815616
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1341237584
Short name T74
Test name
Test status
Simulation time 4114425095 ps
CPU time 9.35 seconds
Started Apr 16 02:17:23 PM PDT 24
Finished Apr 16 02:17:32 PM PDT 24
Peak memory 201548 kb
Host smart-a1257097-628b-46bc-9738-543c7f2067c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341237584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1341237584
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2090242151
Short name T823
Test name
Test status
Simulation time 460924588 ps
CPU time 0.93 seconds
Started Apr 16 02:18:21 PM PDT 24
Finished Apr 16 02:18:23 PM PDT 24
Peak memory 201240 kb
Host smart-999a6e52-07f2-416c-b1de-87f1ce37ed39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090242151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2090242151
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1319654635
Short name T848
Test name
Test status
Simulation time 340499014 ps
CPU time 0.78 seconds
Started Apr 16 02:18:20 PM PDT 24
Finished Apr 16 02:18:21 PM PDT 24
Peak memory 201260 kb
Host smart-7fc2be72-d29b-4537-b535-fdd3edbd8738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319654635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1319654635
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2762695863
Short name T854
Test name
Test status
Simulation time 325819504 ps
CPU time 0.8 seconds
Started Apr 16 02:18:21 PM PDT 24
Finished Apr 16 02:18:23 PM PDT 24
Peak memory 201208 kb
Host smart-66a48d2d-3bd5-4a1c-ab26-7ff105758732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762695863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2762695863
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3652042647
Short name T811
Test name
Test status
Simulation time 331836722 ps
CPU time 1.41 seconds
Started Apr 16 02:18:24 PM PDT 24
Finished Apr 16 02:18:26 PM PDT 24
Peak memory 201252 kb
Host smart-7b6ff53e-9175-40c4-9d16-c1dcede01630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652042647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3652042647
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2579531196
Short name T868
Test name
Test status
Simulation time 338981549 ps
CPU time 1.39 seconds
Started Apr 16 02:18:22 PM PDT 24
Finished Apr 16 02:18:25 PM PDT 24
Peak memory 201244 kb
Host smart-d1690ef0-3d41-46e1-b619-614b1a8a2113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579531196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2579531196
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1881784581
Short name T816
Test name
Test status
Simulation time 411063436 ps
CPU time 1.1 seconds
Started Apr 16 02:18:22 PM PDT 24
Finished Apr 16 02:18:25 PM PDT 24
Peak memory 201232 kb
Host smart-875694f7-ba90-4a48-9360-9834df241492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881784581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1881784581
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3730226113
Short name T813
Test name
Test status
Simulation time 521806947 ps
CPU time 1.85 seconds
Started Apr 16 02:18:23 PM PDT 24
Finished Apr 16 02:18:26 PM PDT 24
Peak memory 201248 kb
Host smart-0fdec681-c4e8-42ed-8af8-2fdd65b040ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730226113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3730226113
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3064858147
Short name T831
Test name
Test status
Simulation time 452318214 ps
CPU time 0.71 seconds
Started Apr 16 02:18:21 PM PDT 24
Finished Apr 16 02:18:24 PM PDT 24
Peak memory 201184 kb
Host smart-4fb43291-1d70-4ed2-8738-daec3de49259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064858147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3064858147
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4247954430
Short name T914
Test name
Test status
Simulation time 403045207 ps
CPU time 0.74 seconds
Started Apr 16 02:18:21 PM PDT 24
Finished Apr 16 02:18:23 PM PDT 24
Peak memory 201240 kb
Host smart-30cd5316-9c5c-4827-bc91-55f45dd20702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247954430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.4247954430
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3549098252
Short name T815
Test name
Test status
Simulation time 512688223 ps
CPU time 0.98 seconds
Started Apr 16 02:18:22 PM PDT 24
Finished Apr 16 02:18:24 PM PDT 24
Peak memory 201232 kb
Host smart-96125dbd-8fa4-43b1-9639-efb404e7ec64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549098252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3549098252
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3553700118
Short name T137
Test name
Test status
Simulation time 1149402922 ps
CPU time 4 seconds
Started Apr 16 02:17:32 PM PDT 24
Finished Apr 16 02:17:37 PM PDT 24
Peak memory 201456 kb
Host smart-a75cf6a4-27e5-404a-82dc-d3db0ac11c6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553700118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3553700118
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2700156763
Short name T863
Test name
Test status
Simulation time 52996331004 ps
CPU time 68.86 seconds
Started Apr 16 02:17:32 PM PDT 24
Finished Apr 16 02:18:41 PM PDT 24
Peak memory 201480 kb
Host smart-4c868098-3256-48d7-8d5c-5c02beee9ad9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700156763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2700156763
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.193578021
Short name T145
Test name
Test status
Simulation time 1187760477 ps
CPU time 1.51 seconds
Started Apr 16 02:17:33 PM PDT 24
Finished Apr 16 02:17:35 PM PDT 24
Peak memory 201240 kb
Host smart-40148c39-7dd6-43dd-8529-3ba569eccce0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193578021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.193578021
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.681232013
Short name T857
Test name
Test status
Simulation time 622046281 ps
CPU time 1.29 seconds
Started Apr 16 02:17:35 PM PDT 24
Finished Apr 16 02:17:37 PM PDT 24
Peak memory 201488 kb
Host smart-a247601d-1210-410d-ab9d-bd29e917f3a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681232013 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.681232013
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1159790325
Short name T851
Test name
Test status
Simulation time 329517785 ps
CPU time 1.62 seconds
Started Apr 16 02:17:34 PM PDT 24
Finished Apr 16 02:17:36 PM PDT 24
Peak memory 201172 kb
Host smart-b3ab3d04-80c7-43cc-90de-23e420755acc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159790325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1159790325
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.749020729
Short name T820
Test name
Test status
Simulation time 422224268 ps
CPU time 0.89 seconds
Started Apr 16 02:17:32 PM PDT 24
Finished Apr 16 02:17:34 PM PDT 24
Peak memory 201232 kb
Host smart-50351012-e122-4ec4-b3dd-a21af27dbede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749020729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.749020729
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3627402082
Short name T858
Test name
Test status
Simulation time 2386729893 ps
CPU time 1.89 seconds
Started Apr 16 02:17:36 PM PDT 24
Finished Apr 16 02:17:39 PM PDT 24
Peak memory 201304 kb
Host smart-77688581-c056-4fc3-b3a0-1141b8752f82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627402082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3627402082
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.423320385
Short name T889
Test name
Test status
Simulation time 473957230 ps
CPU time 2.59 seconds
Started Apr 16 02:17:34 PM PDT 24
Finished Apr 16 02:17:37 PM PDT 24
Peak memory 201488 kb
Host smart-d82af12b-d9b1-4198-85ae-c06a07f36b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423320385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.423320385
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1742620589
Short name T345
Test name
Test status
Simulation time 8974524176 ps
CPU time 5.18 seconds
Started Apr 16 02:17:34 PM PDT 24
Finished Apr 16 02:17:40 PM PDT 24
Peak memory 201516 kb
Host smart-ca44c31b-a8df-4402-add9-c65c3aa1725f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742620589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1742620589
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2905450489
Short name T885
Test name
Test status
Simulation time 336923619 ps
CPU time 0.89 seconds
Started Apr 16 02:18:22 PM PDT 24
Finished Apr 16 02:18:24 PM PDT 24
Peak memory 201204 kb
Host smart-254d6650-5aa2-45ee-931b-8447321c678c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905450489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2905450489
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.83279449
Short name T853
Test name
Test status
Simulation time 322497120 ps
CPU time 1 seconds
Started Apr 16 02:18:22 PM PDT 24
Finished Apr 16 02:18:25 PM PDT 24
Peak memory 201228 kb
Host smart-74ff17dd-858d-4b54-bb77-d3bf9407ecac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83279449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.83279449
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1696804851
Short name T825
Test name
Test status
Simulation time 325509123 ps
CPU time 1.37 seconds
Started Apr 16 02:18:31 PM PDT 24
Finished Apr 16 02:18:33 PM PDT 24
Peak memory 201168 kb
Host smart-60d25551-da19-45fb-ac7f-90393e7ab1a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696804851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1696804851
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1178054020
Short name T842
Test name
Test status
Simulation time 427202353 ps
CPU time 0.7 seconds
Started Apr 16 02:18:27 PM PDT 24
Finished Apr 16 02:18:28 PM PDT 24
Peak memory 201244 kb
Host smart-0fe9b0b2-7968-4279-acf5-eb358bd34aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178054020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1178054020
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.683430988
Short name T818
Test name
Test status
Simulation time 457584132 ps
CPU time 1.35 seconds
Started Apr 16 02:18:30 PM PDT 24
Finished Apr 16 02:18:32 PM PDT 24
Peak memory 201260 kb
Host smart-6f0ba420-56ef-4085-b49c-341c340c1559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683430988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.683430988
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.545122246
Short name T888
Test name
Test status
Simulation time 531069476 ps
CPU time 1.76 seconds
Started Apr 16 02:18:28 PM PDT 24
Finished Apr 16 02:18:30 PM PDT 24
Peak memory 201216 kb
Host smart-8f9d1539-523f-45e3-825d-e1bbd7a99212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545122246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.545122246
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1201489431
Short name T877
Test name
Test status
Simulation time 446599397 ps
CPU time 1.72 seconds
Started Apr 16 02:18:27 PM PDT 24
Finished Apr 16 02:18:29 PM PDT 24
Peak memory 201212 kb
Host smart-92de47dd-d719-449f-861d-d034ab0f61c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201489431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1201489431
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1242025816
Short name T861
Test name
Test status
Simulation time 404929292 ps
CPU time 0.85 seconds
Started Apr 16 02:18:24 PM PDT 24
Finished Apr 16 02:18:26 PM PDT 24
Peak memory 201232 kb
Host smart-feba8aaa-b176-4433-ac1c-3f8c2d8d5353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242025816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1242025816
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.265660006
Short name T834
Test name
Test status
Simulation time 416059932 ps
CPU time 0.72 seconds
Started Apr 16 02:18:27 PM PDT 24
Finished Apr 16 02:18:28 PM PDT 24
Peak memory 201208 kb
Host smart-f7712654-2dda-404c-846f-2c0167eeb3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265660006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.265660006
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2021381791
Short name T803
Test name
Test status
Simulation time 460144192 ps
CPU time 0.91 seconds
Started Apr 16 02:18:26 PM PDT 24
Finished Apr 16 02:18:27 PM PDT 24
Peak memory 201164 kb
Host smart-a0cd7688-d057-465d-b9dd-9a373da8fce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021381791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2021381791
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2329451669
Short name T844
Test name
Test status
Simulation time 1203147991 ps
CPU time 5.1 seconds
Started Apr 16 02:17:38 PM PDT 24
Finished Apr 16 02:17:43 PM PDT 24
Peak memory 201432 kb
Host smart-0bfa4f3c-177d-443a-837c-e922aaf2c717
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329451669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2329451669
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3587051788
Short name T866
Test name
Test status
Simulation time 53104706183 ps
CPU time 36.64 seconds
Started Apr 16 02:17:39 PM PDT 24
Finished Apr 16 02:18:16 PM PDT 24
Peak memory 201488 kb
Host smart-5da1a5d9-3da8-4d21-bbed-f559cff90782
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587051788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3587051788
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.306576333
Short name T915
Test name
Test status
Simulation time 1209889808 ps
CPU time 1.15 seconds
Started Apr 16 02:17:36 PM PDT 24
Finished Apr 16 02:17:38 PM PDT 24
Peak memory 201240 kb
Host smart-6d4b7c47-a7fa-4294-96b4-d49bc3c44932
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306576333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.306576333
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.944478044
Short name T119
Test name
Test status
Simulation time 458207131 ps
CPU time 1.19 seconds
Started Apr 16 02:17:39 PM PDT 24
Finished Apr 16 02:17:40 PM PDT 24
Peak memory 201312 kb
Host smart-a1fe2509-3773-46df-8c2b-ad8a15b66d72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944478044 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.944478044
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1564441356
Short name T919
Test name
Test status
Simulation time 443560612 ps
CPU time 0.99 seconds
Started Apr 16 02:17:40 PM PDT 24
Finished Apr 16 02:17:42 PM PDT 24
Peak memory 201252 kb
Host smart-8211ddbb-3c81-4551-b2e1-901076fec109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564441356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1564441356
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3511919528
Short name T809
Test name
Test status
Simulation time 318726174 ps
CPU time 1.08 seconds
Started Apr 16 02:17:35 PM PDT 24
Finished Apr 16 02:17:36 PM PDT 24
Peak memory 201432 kb
Host smart-9da0b6b9-e2a0-46f0-ac0d-c09d621d9fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511919528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3511919528
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.522007804
Short name T155
Test name
Test status
Simulation time 2387510017 ps
CPU time 9.4 seconds
Started Apr 16 02:17:39 PM PDT 24
Finished Apr 16 02:17:48 PM PDT 24
Peak memory 201300 kb
Host smart-862a9d6b-e3b6-47a0-b930-8971175b4b26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522007804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.522007804
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.245244726
Short name T893
Test name
Test status
Simulation time 502978516 ps
CPU time 2.4 seconds
Started Apr 16 02:17:33 PM PDT 24
Finished Apr 16 02:17:36 PM PDT 24
Peak memory 201496 kb
Host smart-bc0375ce-7d5c-4b73-ab56-ae5a96a2426c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245244726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.245244726
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1881248680
Short name T93
Test name
Test status
Simulation time 4450686177 ps
CPU time 12.8 seconds
Started Apr 16 02:17:32 PM PDT 24
Finished Apr 16 02:17:46 PM PDT 24
Peak memory 201440 kb
Host smart-6de12f8e-0d07-414c-a820-dd0b73cb6346
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881248680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1881248680
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1665772517
Short name T898
Test name
Test status
Simulation time 500818050 ps
CPU time 1.77 seconds
Started Apr 16 02:18:29 PM PDT 24
Finished Apr 16 02:18:31 PM PDT 24
Peak memory 201096 kb
Host smart-46f96ba5-6f3e-478f-9694-895b1f67dcf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665772517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1665772517
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3309872027
Short name T920
Test name
Test status
Simulation time 493795420 ps
CPU time 1.77 seconds
Started Apr 16 02:18:27 PM PDT 24
Finished Apr 16 02:18:30 PM PDT 24
Peak memory 201240 kb
Host smart-e4578506-a3af-4bf2-a035-b69533c6f9a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309872027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3309872027
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.822393943
Short name T892
Test name
Test status
Simulation time 402919145 ps
CPU time 1.47 seconds
Started Apr 16 02:18:29 PM PDT 24
Finished Apr 16 02:18:31 PM PDT 24
Peak memory 201128 kb
Host smart-fcaf233e-5b70-4c71-b95a-f5dcc7b88ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822393943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.822393943
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.665420602
Short name T824
Test name
Test status
Simulation time 523136610 ps
CPU time 0.92 seconds
Started Apr 16 02:18:26 PM PDT 24
Finished Apr 16 02:18:28 PM PDT 24
Peak memory 201220 kb
Host smart-794ac5bc-6741-4213-bb48-8411d876acbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665420602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.665420602
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2648921829
Short name T814
Test name
Test status
Simulation time 425095314 ps
CPU time 1.65 seconds
Started Apr 16 02:18:30 PM PDT 24
Finished Apr 16 02:18:32 PM PDT 24
Peak memory 201256 kb
Host smart-10337eaf-d440-4498-afe2-abd9ef30ed3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648921829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2648921829
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2674975785
Short name T912
Test name
Test status
Simulation time 403382332 ps
CPU time 0.86 seconds
Started Apr 16 02:18:27 PM PDT 24
Finished Apr 16 02:18:29 PM PDT 24
Peak memory 201240 kb
Host smart-deba6303-0ffd-4af6-b5f4-1a5e7536d012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674975785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2674975785
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1407974123
Short name T807
Test name
Test status
Simulation time 467988999 ps
CPU time 0.89 seconds
Started Apr 16 02:18:27 PM PDT 24
Finished Apr 16 02:18:28 PM PDT 24
Peak memory 201188 kb
Host smart-e8768b6a-8c66-4ba2-a5dd-74f5a02b3c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407974123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1407974123
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1007771955
Short name T867
Test name
Test status
Simulation time 458951103 ps
CPU time 1.72 seconds
Started Apr 16 02:18:27 PM PDT 24
Finished Apr 16 02:18:29 PM PDT 24
Peak memory 201216 kb
Host smart-9ae039f0-5bd7-4b55-b71f-b9c743d60ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007771955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1007771955
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.70258301
Short name T810
Test name
Test status
Simulation time 292547238 ps
CPU time 1.25 seconds
Started Apr 16 02:18:25 PM PDT 24
Finished Apr 16 02:18:27 PM PDT 24
Peak memory 201240 kb
Host smart-058d94ab-907a-45d4-99e4-85ce2a12a04c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70258301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.70258301
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.787659674
Short name T819
Test name
Test status
Simulation time 507461781 ps
CPU time 1.85 seconds
Started Apr 16 02:18:32 PM PDT 24
Finished Apr 16 02:18:35 PM PDT 24
Peak memory 201236 kb
Host smart-5c37fab8-a47e-4922-b118-2865da4f0f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787659674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.787659674
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1410239844
Short name T838
Test name
Test status
Simulation time 613729233 ps
CPU time 1.6 seconds
Started Apr 16 02:17:42 PM PDT 24
Finished Apr 16 02:17:45 PM PDT 24
Peak memory 201256 kb
Host smart-efb6d49d-c91a-4c34-a5f9-4a9b50ca2f8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410239844 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1410239844
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2975842007
Short name T881
Test name
Test status
Simulation time 495253816 ps
CPU time 0.89 seconds
Started Apr 16 02:17:43 PM PDT 24
Finished Apr 16 02:17:45 PM PDT 24
Peak memory 201252 kb
Host smart-66e4088a-9702-458a-ae3d-a31e8b6b6bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975842007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2975842007
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.826634340
Short name T891
Test name
Test status
Simulation time 2071648394 ps
CPU time 2.45 seconds
Started Apr 16 02:17:43 PM PDT 24
Finished Apr 16 02:17:46 PM PDT 24
Peak memory 201252 kb
Host smart-7e70cac5-1427-4bac-9d50-a69f7ef77c63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826634340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.826634340
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3610233427
Short name T886
Test name
Test status
Simulation time 497703547 ps
CPU time 2.39 seconds
Started Apr 16 02:17:41 PM PDT 24
Finished Apr 16 02:17:44 PM PDT 24
Peak memory 201472 kb
Host smart-df69a1a1-0768-4c30-af55-a8e60ce5122f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610233427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3610233427
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3447334067
Short name T837
Test name
Test status
Simulation time 4570426526 ps
CPU time 6.65 seconds
Started Apr 16 02:17:44 PM PDT 24
Finished Apr 16 02:17:51 PM PDT 24
Peak memory 201448 kb
Host smart-a4727864-aab5-4614-9e45-0d047e6e860f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447334067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3447334067
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.160154289
Short name T76
Test name
Test status
Simulation time 486855247 ps
CPU time 1.26 seconds
Started Apr 16 02:17:48 PM PDT 24
Finished Apr 16 02:17:50 PM PDT 24
Peak memory 201260 kb
Host smart-93bba142-cc62-4d60-9763-a4d8d7f2b5b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160154289 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.160154289
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3122740840
Short name T876
Test name
Test status
Simulation time 314952180 ps
CPU time 1.11 seconds
Started Apr 16 02:17:47 PM PDT 24
Finished Apr 16 02:17:48 PM PDT 24
Peak memory 201212 kb
Host smart-48dff0f2-9a6a-4ac4-b900-02173a64c9ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122740840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3122740840
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2198552127
Short name T817
Test name
Test status
Simulation time 446655858 ps
CPU time 0.98 seconds
Started Apr 16 02:17:48 PM PDT 24
Finished Apr 16 02:17:50 PM PDT 24
Peak memory 201184 kb
Host smart-0abdcff7-9795-4dc8-aaa3-ea554b893a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198552127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2198552127
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4270029469
Short name T830
Test name
Test status
Simulation time 2378652316 ps
CPU time 2.04 seconds
Started Apr 16 02:17:47 PM PDT 24
Finished Apr 16 02:17:50 PM PDT 24
Peak memory 201276 kb
Host smart-d00ed8a5-59d8-43e9-afad-3cc443f69bcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270029469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.4270029469
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1566496409
Short name T88
Test name
Test status
Simulation time 415093389 ps
CPU time 2.51 seconds
Started Apr 16 02:17:44 PM PDT 24
Finished Apr 16 02:17:47 PM PDT 24
Peak memory 201516 kb
Host smart-efe48f92-c819-456c-92ef-a17092503a77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566496409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1566496409
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3985210233
Short name T87
Test name
Test status
Simulation time 8426466798 ps
CPU time 21.63 seconds
Started Apr 16 02:17:43 PM PDT 24
Finished Apr 16 02:18:05 PM PDT 24
Peak memory 201524 kb
Host smart-f215ea1a-ad14-44ee-b118-8b7809ec44d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985210233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3985210233
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4190482599
Short name T835
Test name
Test status
Simulation time 489928494 ps
CPU time 1.34 seconds
Started Apr 16 02:17:48 PM PDT 24
Finished Apr 16 02:17:50 PM PDT 24
Peak memory 201212 kb
Host smart-34450c14-59eb-4f72-8553-0cc141e77477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190482599 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4190482599
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2519446332
Short name T141
Test name
Test status
Simulation time 368465594 ps
CPU time 1.64 seconds
Started Apr 16 02:17:47 PM PDT 24
Finished Apr 16 02:17:49 PM PDT 24
Peak memory 201176 kb
Host smart-9b917942-b50e-49da-b3e9-7999cb5971a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519446332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2519446332
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2467741756
Short name T812
Test name
Test status
Simulation time 502379678 ps
CPU time 1.82 seconds
Started Apr 16 02:17:48 PM PDT 24
Finished Apr 16 02:17:50 PM PDT 24
Peak memory 201252 kb
Host smart-5968d402-5d68-443e-9a6e-8a3e9c75d42a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467741756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2467741756
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4132345270
Short name T862
Test name
Test status
Simulation time 4359424454 ps
CPU time 15.24 seconds
Started Apr 16 02:17:49 PM PDT 24
Finished Apr 16 02:18:04 PM PDT 24
Peak memory 201536 kb
Host smart-bc159c16-fde1-4408-a8de-3a0d770990de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132345270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4132345270
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2244888440
Short name T918
Test name
Test status
Simulation time 449181632 ps
CPU time 3.18 seconds
Started Apr 16 02:17:48 PM PDT 24
Finished Apr 16 02:17:52 PM PDT 24
Peak memory 201520 kb
Host smart-121af48c-ef7f-48af-a193-f801de11f511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244888440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2244888440
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4052930008
Short name T880
Test name
Test status
Simulation time 8330562936 ps
CPU time 22.84 seconds
Started Apr 16 02:17:51 PM PDT 24
Finished Apr 16 02:18:14 PM PDT 24
Peak memory 201460 kb
Host smart-32bbbe56-aea1-43e3-8cc2-6349ae2dd36a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052930008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.4052930008
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2840114326
Short name T829
Test name
Test status
Simulation time 569142411 ps
CPU time 1.25 seconds
Started Apr 16 02:17:56 PM PDT 24
Finished Apr 16 02:17:57 PM PDT 24
Peak memory 201288 kb
Host smart-ef089815-32dd-4f30-9e40-36919db7abc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840114326 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2840114326
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3237598193
Short name T903
Test name
Test status
Simulation time 352661746 ps
CPU time 0.97 seconds
Started Apr 16 02:17:52 PM PDT 24
Finished Apr 16 02:17:53 PM PDT 24
Peak memory 201244 kb
Host smart-7b326b03-d76d-4962-8ba4-ec48ad1e47a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237598193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3237598193
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2130561303
Short name T846
Test name
Test status
Simulation time 423896048 ps
CPU time 0.75 seconds
Started Apr 16 02:17:51 PM PDT 24
Finished Apr 16 02:17:52 PM PDT 24
Peak memory 201212 kb
Host smart-075292c1-9d87-4209-bb9e-d2340f6d893b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130561303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2130561303
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1763665608
Short name T151
Test name
Test status
Simulation time 4774749940 ps
CPU time 4.11 seconds
Started Apr 16 02:17:57 PM PDT 24
Finished Apr 16 02:18:02 PM PDT 24
Peak memory 201456 kb
Host smart-b86292d8-e619-4449-9a44-19b0dc923b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763665608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1763665608
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.205630092
Short name T75
Test name
Test status
Simulation time 4180956615 ps
CPU time 6.55 seconds
Started Apr 16 02:17:48 PM PDT 24
Finished Apr 16 02:17:55 PM PDT 24
Peak memory 201452 kb
Host smart-8204f1ca-e88f-4ddc-b01d-43135e8ebad2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205630092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.205630092
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3348305347
Short name T887
Test name
Test status
Simulation time 638840206 ps
CPU time 2.41 seconds
Started Apr 16 02:17:54 PM PDT 24
Finished Apr 16 02:17:57 PM PDT 24
Peak memory 201288 kb
Host smart-6f8884bd-cc43-4d87-9bc5-e46ac1223f8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348305347 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3348305347
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2412070606
Short name T913
Test name
Test status
Simulation time 538872841 ps
CPU time 0.99 seconds
Started Apr 16 02:17:53 PM PDT 24
Finished Apr 16 02:17:55 PM PDT 24
Peak memory 201260 kb
Host smart-5a485801-bf24-4b98-a01c-c195a5dd343d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412070606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2412070606
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.475008677
Short name T871
Test name
Test status
Simulation time 488608381 ps
CPU time 0.85 seconds
Started Apr 16 02:17:53 PM PDT 24
Finished Apr 16 02:17:54 PM PDT 24
Peak memory 201184 kb
Host smart-23da4ad3-f526-4614-a618-2e4a59ffe833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475008677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.475008677
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.823990023
Short name T153
Test name
Test status
Simulation time 4926438783 ps
CPU time 5.55 seconds
Started Apr 16 02:17:52 PM PDT 24
Finished Apr 16 02:17:58 PM PDT 24
Peak memory 201484 kb
Host smart-ed60d96c-ea5a-4696-a154-c6dad8d64ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823990023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.823990023
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3005062918
Short name T83
Test name
Test status
Simulation time 393648438 ps
CPU time 1.98 seconds
Started Apr 16 02:17:54 PM PDT 24
Finished Apr 16 02:17:57 PM PDT 24
Peak memory 201492 kb
Host smart-3ec3b083-a3de-4607-9873-1ebab3344d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005062918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3005062918
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2442071283
Short name T897
Test name
Test status
Simulation time 4387440757 ps
CPU time 12.62 seconds
Started Apr 16 02:17:53 PM PDT 24
Finished Apr 16 02:18:06 PM PDT 24
Peak memory 201460 kb
Host smart-1f7e4ed3-a803-481c-873f-4b40201ecf33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442071283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2442071283
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.4277418932
Short name T596
Test name
Test status
Simulation time 520087539 ps
CPU time 0.95 seconds
Started Apr 16 02:20:40 PM PDT 24
Finished Apr 16 02:20:42 PM PDT 24
Peak memory 201968 kb
Host smart-6c7be6e0-ccbc-4cfe-ac43-67d149471e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277418932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.4277418932
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3335592325
Short name T229
Test name
Test status
Simulation time 323778964751 ps
CPU time 187.93 seconds
Started Apr 16 02:20:43 PM PDT 24
Finished Apr 16 02:23:51 PM PDT 24
Peak memory 202200 kb
Host smart-351cfd68-157f-4327-9210-02d2f210163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335592325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3335592325
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1834944135
Short name T579
Test name
Test status
Simulation time 160753301218 ps
CPU time 348.74 seconds
Started Apr 16 02:20:40 PM PDT 24
Finished Apr 16 02:26:29 PM PDT 24
Peak memory 202280 kb
Host smart-796f5a73-0f59-4025-b1f3-a96ed6e92296
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834944135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1834944135
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.4266460622
Short name T324
Test name
Test status
Simulation time 328906510923 ps
CPU time 353.16 seconds
Started Apr 16 02:20:44 PM PDT 24
Finished Apr 16 02:26:38 PM PDT 24
Peak memory 202344 kb
Host smart-9a629c6c-845f-443a-9ee6-6865c704bc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266460622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.4266460622
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.472275445
Short name T25
Test name
Test status
Simulation time 335823190875 ps
CPU time 216.92 seconds
Started Apr 16 02:20:38 PM PDT 24
Finished Apr 16 02:24:16 PM PDT 24
Peak memory 202140 kb
Host smart-79d75012-c1c7-42c5-bf8a-1c47b42726d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=472275445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.472275445
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1290941777
Short name T322
Test name
Test status
Simulation time 563457064723 ps
CPU time 568.42 seconds
Started Apr 16 02:20:44 PM PDT 24
Finished Apr 16 02:30:13 PM PDT 24
Peak memory 202280 kb
Host smart-6325b86b-d876-4b38-9304-08bfb73e83dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290941777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1290941777
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3996874620
Short name T378
Test name
Test status
Simulation time 390235798995 ps
CPU time 432.73 seconds
Started Apr 16 02:20:40 PM PDT 24
Finished Apr 16 02:27:53 PM PDT 24
Peak memory 202188 kb
Host smart-b5592ae3-584c-4eb6-b9cc-2096efd884b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996874620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3996874620
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1780208803
Short name T5
Test name
Test status
Simulation time 106333978400 ps
CPU time 351.04 seconds
Started Apr 16 02:20:41 PM PDT 24
Finished Apr 16 02:26:33 PM PDT 24
Peak memory 202576 kb
Host smart-b1324007-e3a0-4b7a-9b7d-a6db671339dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780208803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1780208803
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.248294333
Short name T713
Test name
Test status
Simulation time 29881249812 ps
CPU time 37.07 seconds
Started Apr 16 02:20:39 PM PDT 24
Finished Apr 16 02:21:17 PM PDT 24
Peak memory 202032 kb
Host smart-b82d5801-eba7-4771-8b18-65d390520a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248294333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.248294333
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2821878859
Short name T30
Test name
Test status
Simulation time 4160620139 ps
CPU time 1.16 seconds
Started Apr 16 02:20:44 PM PDT 24
Finished Apr 16 02:20:46 PM PDT 24
Peak memory 201980 kb
Host smart-31c15053-a1e8-453d-8488-72e217d1b85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821878859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2821878859
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.652858724
Short name T412
Test name
Test status
Simulation time 5675884508 ps
CPU time 15.04 seconds
Started Apr 16 02:20:41 PM PDT 24
Finished Apr 16 02:20:57 PM PDT 24
Peak memory 202072 kb
Host smart-a858dacb-fa43-4a31-9493-d24580e49905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652858724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.652858724
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3650482852
Short name T235
Test name
Test status
Simulation time 170365961369 ps
CPU time 403.62 seconds
Started Apr 16 02:20:41 PM PDT 24
Finished Apr 16 02:27:25 PM PDT 24
Peak memory 202260 kb
Host smart-be0c8481-5178-4ead-a961-4221ba6f8aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650482852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3650482852
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4080561530
Short name T755
Test name
Test status
Simulation time 88299389175 ps
CPU time 341.71 seconds
Started Apr 16 02:20:42 PM PDT 24
Finished Apr 16 02:26:25 PM PDT 24
Peak memory 202740 kb
Host smart-ffba73b8-a367-402b-9681-6b00f66353d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080561530 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4080561530
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1494230888
Short name T469
Test name
Test status
Simulation time 323387808 ps
CPU time 0.98 seconds
Started Apr 16 02:20:44 PM PDT 24
Finished Apr 16 02:20:46 PM PDT 24
Peak memory 201884 kb
Host smart-5df1e2f3-1db7-4735-b610-5092500ba8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494230888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1494230888
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1188905292
Short name T269
Test name
Test status
Simulation time 176632163185 ps
CPU time 89.7 seconds
Started Apr 16 02:20:45 PM PDT 24
Finished Apr 16 02:22:16 PM PDT 24
Peak memory 202344 kb
Host smart-614cd178-56f9-4585-84b3-5cf27d737eda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188905292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1188905292
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.408275724
Short name T111
Test name
Test status
Simulation time 164610925491 ps
CPU time 387.51 seconds
Started Apr 16 02:20:40 PM PDT 24
Finished Apr 16 02:27:08 PM PDT 24
Peak memory 202328 kb
Host smart-d4a0324b-757e-45e7-998b-8acd4e2e5fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408275724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.408275724
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3337158554
Short name T443
Test name
Test status
Simulation time 159747183505 ps
CPU time 391.8 seconds
Started Apr 16 02:20:40 PM PDT 24
Finished Apr 16 02:27:13 PM PDT 24
Peak memory 202212 kb
Host smart-0e58c90b-49c1-4797-8175-35021a611652
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337158554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3337158554
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2594537791
Short name T498
Test name
Test status
Simulation time 493918352784 ps
CPU time 1033.42 seconds
Started Apr 16 02:20:46 PM PDT 24
Finished Apr 16 02:38:00 PM PDT 24
Peak memory 202248 kb
Host smart-732d81d7-3e2a-447f-9e5a-efca1b901be1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594537791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2594537791
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2568000305
Short name T662
Test name
Test status
Simulation time 175826279447 ps
CPU time 213.6 seconds
Started Apr 16 02:20:47 PM PDT 24
Finished Apr 16 02:24:21 PM PDT 24
Peak memory 202380 kb
Host smart-d77ec603-ad8d-4240-bda0-0dfaeb26007e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568000305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2568000305
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3485841366
Short name T703
Test name
Test status
Simulation time 609062799772 ps
CPU time 710.6 seconds
Started Apr 16 02:20:45 PM PDT 24
Finished Apr 16 02:32:36 PM PDT 24
Peak memory 202188 kb
Host smart-ed9b7c6e-fad1-413c-846b-478e30606ebd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485841366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3485841366
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2524975994
Short name T59
Test name
Test status
Simulation time 78585791330 ps
CPU time 327.8 seconds
Started Apr 16 02:20:45 PM PDT 24
Finished Apr 16 02:26:14 PM PDT 24
Peak memory 202636 kb
Host smart-f74c3f3d-616b-4c0e-a0bf-c1e82a4425f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524975994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2524975994
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2506182436
Short name T563
Test name
Test status
Simulation time 36004970861 ps
CPU time 19.36 seconds
Started Apr 16 02:20:46 PM PDT 24
Finished Apr 16 02:21:06 PM PDT 24
Peak memory 202004 kb
Host smart-3eb3c73f-de50-49b3-ac2b-ec4d167fda18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506182436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2506182436
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2714284120
Short name T411
Test name
Test status
Simulation time 4240093120 ps
CPU time 2.82 seconds
Started Apr 16 02:20:48 PM PDT 24
Finished Apr 16 02:20:51 PM PDT 24
Peak memory 202032 kb
Host smart-c7f98a9d-fe68-47de-9584-b745f3fff042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714284120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2714284120
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.313688401
Short name T79
Test name
Test status
Simulation time 4596863819 ps
CPU time 3.61 seconds
Started Apr 16 02:20:46 PM PDT 24
Finished Apr 16 02:20:50 PM PDT 24
Peak memory 217740 kb
Host smart-fab57cd1-b73b-4a7f-bc16-3afea34e2419
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313688401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.313688401
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3434757874
Short name T767
Test name
Test status
Simulation time 5786783948 ps
CPU time 5.02 seconds
Started Apr 16 02:20:46 PM PDT 24
Finished Apr 16 02:20:52 PM PDT 24
Peak memory 202108 kb
Host smart-8c3a0033-91f5-4034-b2db-1276a7a76e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434757874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3434757874
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3573355503
Short name T638
Test name
Test status
Simulation time 299746587388 ps
CPU time 1081.57 seconds
Started Apr 16 02:20:48 PM PDT 24
Finished Apr 16 02:38:50 PM PDT 24
Peak memory 213232 kb
Host smart-47254abe-861e-422f-8472-caa6cfe533f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573355503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3573355503
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.875444532
Short name T254
Test name
Test status
Simulation time 59387611336 ps
CPU time 93.76 seconds
Started Apr 16 02:20:46 PM PDT 24
Finished Apr 16 02:22:21 PM PDT 24
Peak memory 210956 kb
Host smart-ad1ea3de-f408-4211-8e0f-f1fa0c8ea376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875444532 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.875444532
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1848608810
Short name T682
Test name
Test status
Simulation time 334589924 ps
CPU time 1.38 seconds
Started Apr 16 02:21:16 PM PDT 24
Finished Apr 16 02:21:18 PM PDT 24
Peak memory 201892 kb
Host smart-331e1393-2da3-4fa5-aa1b-9491f864274f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848608810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1848608810
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4117999786
Short name T560
Test name
Test status
Simulation time 326095765112 ps
CPU time 780.63 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:34:13 PM PDT 24
Peak memory 202328 kb
Host smart-954eedf8-f7a7-4f05-8950-8116fcae3ada
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117999786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4117999786
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.985134503
Short name T173
Test name
Test status
Simulation time 189761049108 ps
CPU time 347.59 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:27:00 PM PDT 24
Peak memory 202240 kb
Host smart-8787fa4d-996c-4039-af7c-be1a9cde80bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985134503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.985134503
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1584836279
Short name T200
Test name
Test status
Simulation time 495166890443 ps
CPU time 151.8 seconds
Started Apr 16 02:21:12 PM PDT 24
Finished Apr 16 02:23:45 PM PDT 24
Peak memory 202248 kb
Host smart-0641d50c-9896-41f8-86ff-f354bd57ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584836279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1584836279
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.168222687
Short name T439
Test name
Test status
Simulation time 486892180525 ps
CPU time 589.24 seconds
Started Apr 16 02:21:14 PM PDT 24
Finished Apr 16 02:31:04 PM PDT 24
Peak memory 202220 kb
Host smart-39c6b835-d22b-42a5-aeaf-1caf52ff6111
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=168222687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.168222687
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.736969790
Short name T784
Test name
Test status
Simulation time 485577867894 ps
CPU time 1113.21 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:39:45 PM PDT 24
Peak memory 202192 kb
Host smart-8e023056-a887-4f56-9b9f-259ca7c467a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736969790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.736969790
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.781310743
Short name T8
Test name
Test status
Simulation time 165058118039 ps
CPU time 58.72 seconds
Started Apr 16 02:21:13 PM PDT 24
Finished Apr 16 02:22:12 PM PDT 24
Peak memory 202188 kb
Host smart-9e803107-d6f6-44a8-8494-58a7a3b71073
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=781310743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.781310743
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.866564458
Short name T281
Test name
Test status
Simulation time 341702697360 ps
CPU time 382.57 seconds
Started Apr 16 02:21:12 PM PDT 24
Finished Apr 16 02:27:36 PM PDT 24
Peak memory 202296 kb
Host smart-5a9220c8-4171-43fd-b06c-9cf26e2e29fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866564458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.866564458
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2443234263
Short name T511
Test name
Test status
Simulation time 601227157433 ps
CPU time 354.14 seconds
Started Apr 16 02:21:15 PM PDT 24
Finished Apr 16 02:27:10 PM PDT 24
Peak memory 202188 kb
Host smart-86ea3efa-9fa1-4a6c-8320-4496fe26f9e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443234263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2443234263
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1618129770
Short name T28
Test name
Test status
Simulation time 38954196154 ps
CPU time 83.78 seconds
Started Apr 16 02:21:12 PM PDT 24
Finished Apr 16 02:22:37 PM PDT 24
Peak memory 202080 kb
Host smart-373d28d6-9fb9-4748-849f-befd2fd45991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618129770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1618129770
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3594245993
Short name T736
Test name
Test status
Simulation time 4149061128 ps
CPU time 9.68 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:21:22 PM PDT 24
Peak memory 202008 kb
Host smart-480f5712-d059-4850-b25d-258942864803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594245993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3594245993
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.923588887
Short name T27
Test name
Test status
Simulation time 5827266813 ps
CPU time 2.5 seconds
Started Apr 16 02:21:14 PM PDT 24
Finished Apr 16 02:21:17 PM PDT 24
Peak memory 202084 kb
Host smart-d5044064-3c30-4360-8206-8db91a163522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923588887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.923588887
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3668386993
Short name T470
Test name
Test status
Simulation time 395206695 ps
CPU time 1.48 seconds
Started Apr 16 02:21:17 PM PDT 24
Finished Apr 16 02:21:19 PM PDT 24
Peak memory 201976 kb
Host smart-11e0d11d-e261-4c43-ac3b-124adc33a349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668386993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3668386993
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.4269477793
Short name T187
Test name
Test status
Simulation time 355034409143 ps
CPU time 211.21 seconds
Started Apr 16 02:21:20 PM PDT 24
Finished Apr 16 02:24:52 PM PDT 24
Peak memory 202188 kb
Host smart-22af7b76-262e-4dfe-82bc-251f054062ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269477793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.4269477793
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.27151897
Short name T516
Test name
Test status
Simulation time 324342356541 ps
CPU time 762.67 seconds
Started Apr 16 02:21:14 PM PDT 24
Finished Apr 16 02:33:58 PM PDT 24
Peak memory 202276 kb
Host smart-0211ecc4-aa90-46db-a7f3-8afdda54487c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=27151897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt
_fixed.27151897
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3958378165
Short name T56
Test name
Test status
Simulation time 155104860195 ps
CPU time 334.82 seconds
Started Apr 16 02:21:14 PM PDT 24
Finished Apr 16 02:26:50 PM PDT 24
Peak memory 202276 kb
Host smart-4a02990c-f934-44f9-adea-fe3d8ac59afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958378165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3958378165
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2214228723
Short name T521
Test name
Test status
Simulation time 331257295921 ps
CPU time 117.15 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:23:10 PM PDT 24
Peak memory 202268 kb
Host smart-8bb78d7a-10ce-4a55-9afd-6a524e4f721a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214228723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2214228723
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1675427464
Short name T214
Test name
Test status
Simulation time 567058507870 ps
CPU time 625.12 seconds
Started Apr 16 02:21:12 PM PDT 24
Finished Apr 16 02:31:38 PM PDT 24
Peak memory 202288 kb
Host smart-12f9446d-41c1-47a3-aff2-7e0131e6a912
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675427464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1675427464
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1986881111
Short name T125
Test name
Test status
Simulation time 412747658761 ps
CPU time 190.11 seconds
Started Apr 16 02:21:21 PM PDT 24
Finished Apr 16 02:24:31 PM PDT 24
Peak memory 202528 kb
Host smart-1be110bb-0812-4dc9-8693-b9c66658a551
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986881111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1986881111
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3836466691
Short name T353
Test name
Test status
Simulation time 135660173822 ps
CPU time 496.62 seconds
Started Apr 16 02:21:19 PM PDT 24
Finished Apr 16 02:29:37 PM PDT 24
Peak memory 202580 kb
Host smart-095ac939-5302-446c-993e-59a5b8d01d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836466691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3836466691
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2796229982
Short name T517
Test name
Test status
Simulation time 35822915976 ps
CPU time 87.22 seconds
Started Apr 16 02:21:18 PM PDT 24
Finished Apr 16 02:22:47 PM PDT 24
Peak memory 202044 kb
Host smart-9544a4bb-34f6-4077-b78b-b09777f21d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796229982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2796229982
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1986991522
Short name T426
Test name
Test status
Simulation time 4890180023 ps
CPU time 11.27 seconds
Started Apr 16 02:21:18 PM PDT 24
Finished Apr 16 02:21:31 PM PDT 24
Peak memory 202052 kb
Host smart-5ec660f3-84da-4b54-8e5e-63759717f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986991522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1986991522
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.429659703
Short name T446
Test name
Test status
Simulation time 6057905257 ps
CPU time 4.61 seconds
Started Apr 16 02:21:15 PM PDT 24
Finished Apr 16 02:21:20 PM PDT 24
Peak memory 201992 kb
Host smart-65c99b09-a53e-45c8-982e-bf3fb0d7ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429659703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.429659703
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3806054034
Short name T218
Test name
Test status
Simulation time 459464865308 ps
CPU time 1118.02 seconds
Started Apr 16 02:21:17 PM PDT 24
Finished Apr 16 02:39:56 PM PDT 24
Peak memory 202328 kb
Host smart-b090cc96-57eb-45f7-8654-b594e710bd4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806054034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3806054034
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3166167484
Short name T19
Test name
Test status
Simulation time 119316590720 ps
CPU time 268.91 seconds
Started Apr 16 02:21:19 PM PDT 24
Finished Apr 16 02:25:49 PM PDT 24
Peak memory 210928 kb
Host smart-bef008d0-3b56-47ed-be39-ff6540cb1624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166167484 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3166167484
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2881357571
Short name T791
Test name
Test status
Simulation time 432635271 ps
CPU time 0.85 seconds
Started Apr 16 02:21:36 PM PDT 24
Finished Apr 16 02:21:38 PM PDT 24
Peak memory 201952 kb
Host smart-61cff5cc-59c7-4a5c-b633-3c9eb2fee0b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881357571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2881357571
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.152520953
Short name T224
Test name
Test status
Simulation time 195728421215 ps
CPU time 120.91 seconds
Started Apr 16 02:21:26 PM PDT 24
Finished Apr 16 02:23:28 PM PDT 24
Peak memory 202272 kb
Host smart-1f548d31-ff16-4fdb-bedd-6ca779365015
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152520953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.152520953
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.4227763749
Short name T620
Test name
Test status
Simulation time 484958805657 ps
CPU time 143.29 seconds
Started Apr 16 02:21:21 PM PDT 24
Finished Apr 16 02:23:45 PM PDT 24
Peak memory 202488 kb
Host smart-c2270c20-d0b4-4801-b9cc-c67198efab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227763749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.4227763749
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.758964174
Short name T562
Test name
Test status
Simulation time 325090155053 ps
CPU time 755.72 seconds
Started Apr 16 02:21:19 PM PDT 24
Finished Apr 16 02:33:56 PM PDT 24
Peak memory 202196 kb
Host smart-bf02fd79-8993-40e2-83e5-81b481a66d48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=758964174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.758964174
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2541210425
Short name T625
Test name
Test status
Simulation time 168917009993 ps
CPU time 105.78 seconds
Started Apr 16 02:21:19 PM PDT 24
Finished Apr 16 02:23:06 PM PDT 24
Peak memory 202220 kb
Host smart-5e6d9ed0-6856-4a15-a99e-d1b6c2dacf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541210425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2541210425
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.4034450117
Short name T495
Test name
Test status
Simulation time 326641274223 ps
CPU time 826.65 seconds
Started Apr 16 02:21:19 PM PDT 24
Finished Apr 16 02:35:07 PM PDT 24
Peak memory 202328 kb
Host smart-0a315b8d-fb6c-483d-acc9-6dc882e45964
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034450117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.4034450117
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1478835843
Short name T309
Test name
Test status
Simulation time 458097520855 ps
CPU time 277.78 seconds
Started Apr 16 02:21:17 PM PDT 24
Finished Apr 16 02:25:56 PM PDT 24
Peak memory 202168 kb
Host smart-4c387fc8-4f88-4012-ad40-5fe1a6681e54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478835843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1478835843
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3988804946
Short name T199
Test name
Test status
Simulation time 594633968917 ps
CPU time 1413.84 seconds
Started Apr 16 02:21:18 PM PDT 24
Finished Apr 16 02:44:53 PM PDT 24
Peak memory 202320 kb
Host smart-b1c3e896-978a-492b-9d5b-93b2cee0774c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988804946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3988804946
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.71591008
Short name T349
Test name
Test status
Simulation time 109827456480 ps
CPU time 375.51 seconds
Started Apr 16 02:21:26 PM PDT 24
Finished Apr 16 02:27:43 PM PDT 24
Peak memory 202560 kb
Host smart-e2df7e18-70ef-4144-9674-6c657da488db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71591008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.71591008
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.63160728
Short name T445
Test name
Test status
Simulation time 41804589662 ps
CPU time 89.4 seconds
Started Apr 16 02:21:22 PM PDT 24
Finished Apr 16 02:22:51 PM PDT 24
Peak memory 202068 kb
Host smart-b4a0cf2b-6616-4943-97ce-141fb0dfddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63160728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.63160728
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2237322674
Short name T653
Test name
Test status
Simulation time 5260466610 ps
CPU time 2.25 seconds
Started Apr 16 02:21:22 PM PDT 24
Finished Apr 16 02:21:25 PM PDT 24
Peak memory 201972 kb
Host smart-697641fd-93b4-47dd-980d-15f57bf57f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237322674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2237322674
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.348786246
Short name T524
Test name
Test status
Simulation time 6055239637 ps
CPU time 14.62 seconds
Started Apr 16 02:21:17 PM PDT 24
Finished Apr 16 02:21:33 PM PDT 24
Peak memory 202080 kb
Host smart-b5a4e801-3de0-4064-82db-8297872ec680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348786246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.348786246
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2847594399
Short name T314
Test name
Test status
Simulation time 327561015847 ps
CPU time 408.67 seconds
Started Apr 16 02:21:31 PM PDT 24
Finished Apr 16 02:28:21 PM PDT 24
Peak memory 202308 kb
Host smart-cb6bd928-d3d9-4ffa-b0f7-70d7c326dc6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847594399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2847594399
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.305688428
Short name T675
Test name
Test status
Simulation time 323469540035 ps
CPU time 766.15 seconds
Started Apr 16 02:21:31 PM PDT 24
Finished Apr 16 02:34:18 PM PDT 24
Peak memory 202340 kb
Host smart-0d6c29ab-d117-4005-a7dd-b2fd6e1229ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305688428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.305688428
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3946982536
Short name T181
Test name
Test status
Simulation time 327629602889 ps
CPU time 70.45 seconds
Started Apr 16 02:21:29 PM PDT 24
Finished Apr 16 02:22:40 PM PDT 24
Peak memory 202184 kb
Host smart-a9fca0c4-3f95-4821-b124-337a5af32c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946982536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3946982536
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3492445989
Short name T432
Test name
Test status
Simulation time 329874986063 ps
CPU time 761.28 seconds
Started Apr 16 02:21:28 PM PDT 24
Finished Apr 16 02:34:10 PM PDT 24
Peak memory 202252 kb
Host smart-51a4c861-d6c8-439c-ab4e-65afac202969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492445989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3492445989
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3265980055
Short name T451
Test name
Test status
Simulation time 166347290553 ps
CPU time 214.72 seconds
Started Apr 16 02:21:27 PM PDT 24
Finished Apr 16 02:25:02 PM PDT 24
Peak memory 202256 kb
Host smart-1ee30786-4454-4606-9b82-729ecfd2cfdb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265980055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3265980055
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3511110564
Short name T428
Test name
Test status
Simulation time 206341640898 ps
CPU time 99.92 seconds
Started Apr 16 02:21:37 PM PDT 24
Finished Apr 16 02:23:18 PM PDT 24
Peak memory 202304 kb
Host smart-a5bd9f21-fea3-445f-8875-f8d36f61652c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511110564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3511110564
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1705978140
Short name T454
Test name
Test status
Simulation time 126634488192 ps
CPU time 456.56 seconds
Started Apr 16 02:21:36 PM PDT 24
Finished Apr 16 02:29:14 PM PDT 24
Peak memory 202556 kb
Host smart-25c69445-f714-428e-9f46-e4c42a17da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705978140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1705978140
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.104588550
Short name T467
Test name
Test status
Simulation time 33887901765 ps
CPU time 22.67 seconds
Started Apr 16 02:21:37 PM PDT 24
Finished Apr 16 02:22:00 PM PDT 24
Peak memory 202044 kb
Host smart-0b2f8bb8-fe6b-4bb2-80d6-6d618174cd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104588550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.104588550
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1218110927
Short name T46
Test name
Test status
Simulation time 3917214177 ps
CPU time 3.05 seconds
Started Apr 16 02:21:33 PM PDT 24
Finished Apr 16 02:21:37 PM PDT 24
Peak memory 202048 kb
Host smart-9f254e51-a76f-44c0-b594-5e4c6149b30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218110927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1218110927
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3934650279
Short name T44
Test name
Test status
Simulation time 5942554285 ps
CPU time 7.14 seconds
Started Apr 16 02:21:26 PM PDT 24
Finished Apr 16 02:21:34 PM PDT 24
Peak memory 202064 kb
Host smart-e201f211-320f-449c-9ce3-35da2f316b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934650279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3934650279
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2678203940
Short name T576
Test name
Test status
Simulation time 340736324531 ps
CPU time 790.76 seconds
Started Apr 16 02:21:30 PM PDT 24
Finished Apr 16 02:34:42 PM PDT 24
Peak memory 202336 kb
Host smart-971e95ae-511f-4a87-974c-88e9a83058d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678203940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2678203940
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.494185124
Short name T719
Test name
Test status
Simulation time 198678931030 ps
CPU time 41.65 seconds
Started Apr 16 02:21:32 PM PDT 24
Finished Apr 16 02:22:14 PM PDT 24
Peak memory 210484 kb
Host smart-a22d9b98-19c6-49ef-a563-da022c3e68cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494185124 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.494185124
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4265676063
Short name T392
Test name
Test status
Simulation time 548188290 ps
CPU time 0.97 seconds
Started Apr 16 02:21:42 PM PDT 24
Finished Apr 16 02:21:45 PM PDT 24
Peak memory 201912 kb
Host smart-c15b1c17-8d75-4966-a98e-60951e888687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265676063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4265676063
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1293110387
Short name T202
Test name
Test status
Simulation time 164863132950 ps
CPU time 408.13 seconds
Started Apr 16 02:21:36 PM PDT 24
Finished Apr 16 02:28:25 PM PDT 24
Peak memory 202256 kb
Host smart-0c66079c-84c0-4f02-b1dd-97186dd1c4d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293110387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1293110387
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2800455281
Short name T305
Test name
Test status
Simulation time 504722781031 ps
CPU time 1053.48 seconds
Started Apr 16 02:21:37 PM PDT 24
Finished Apr 16 02:39:12 PM PDT 24
Peak memory 202332 kb
Host smart-165cad41-7027-4f64-bd14-93bd3cc2d8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800455281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2800455281
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.749836964
Short name T635
Test name
Test status
Simulation time 161312649950 ps
CPU time 95.13 seconds
Started Apr 16 02:21:37 PM PDT 24
Finished Apr 16 02:23:13 PM PDT 24
Peak memory 201436 kb
Host smart-4dd30d5b-ea73-4f14-95f6-49aa7615dd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749836964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.749836964
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2347935025
Short name T165
Test name
Test status
Simulation time 164640105222 ps
CPU time 26.6 seconds
Started Apr 16 02:21:36 PM PDT 24
Finished Apr 16 02:22:04 PM PDT 24
Peak memory 202244 kb
Host smart-12a9cebd-fd72-473e-867a-d7ea9197de57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347935025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2347935025
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3393861376
Short name T311
Test name
Test status
Simulation time 498424601145 ps
CPU time 600.26 seconds
Started Apr 16 02:21:32 PM PDT 24
Finished Apr 16 02:31:33 PM PDT 24
Peak memory 202260 kb
Host smart-79497024-1236-45b2-9907-e5f657326e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393861376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3393861376
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.240424523
Short name T718
Test name
Test status
Simulation time 161726199000 ps
CPU time 92.2 seconds
Started Apr 16 02:21:31 PM PDT 24
Finished Apr 16 02:23:04 PM PDT 24
Peak memory 202344 kb
Host smart-dbc5c894-c18f-4531-8864-b9cac5d3f98c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=240424523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.240424523
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2467252571
Short name T326
Test name
Test status
Simulation time 549436611437 ps
CPU time 345.42 seconds
Started Apr 16 02:21:36 PM PDT 24
Finished Apr 16 02:27:22 PM PDT 24
Peak memory 202256 kb
Host smart-7fdc370c-47df-4696-ad71-44a19495bc6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467252571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2467252571
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3009946445
Short name T556
Test name
Test status
Simulation time 197043080009 ps
CPU time 142.64 seconds
Started Apr 16 02:21:38 PM PDT 24
Finished Apr 16 02:24:02 PM PDT 24
Peak memory 202220 kb
Host smart-222aa323-c4ff-4ddd-9040-cfb263c2aa55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009946445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3009946445
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.767736306
Short name T759
Test name
Test status
Simulation time 33272516054 ps
CPU time 38.7 seconds
Started Apr 16 02:21:35 PM PDT 24
Finished Apr 16 02:22:14 PM PDT 24
Peak memory 202048 kb
Host smart-7a3f6e7b-1aec-4630-be08-2bab5e1441bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767736306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.767736306
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.808558819
Short name T391
Test name
Test status
Simulation time 3132620986 ps
CPU time 2.37 seconds
Started Apr 16 02:21:37 PM PDT 24
Finished Apr 16 02:21:40 PM PDT 24
Peak memory 202056 kb
Host smart-934c9a90-3cdf-4fa6-b478-81e8f2888e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808558819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.808558819
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1551839253
Short name T687
Test name
Test status
Simulation time 5748659347 ps
CPU time 7.93 seconds
Started Apr 16 02:21:31 PM PDT 24
Finished Apr 16 02:21:40 PM PDT 24
Peak memory 202056 kb
Host smart-d11206b9-c920-4157-9b19-98dd8f9eb3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551839253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1551839253
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.629577226
Short name T714
Test name
Test status
Simulation time 258978330392 ps
CPU time 374.58 seconds
Started Apr 16 02:21:42 PM PDT 24
Finished Apr 16 02:27:59 PM PDT 24
Peak memory 202692 kb
Host smart-59424f21-0b2f-4a78-9a6f-64021d46ff0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629577226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
629577226
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2714809360
Short name T503
Test name
Test status
Simulation time 334502700783 ps
CPU time 199.78 seconds
Started Apr 16 02:21:36 PM PDT 24
Finished Apr 16 02:24:57 PM PDT 24
Peak memory 210856 kb
Host smart-a8bca445-da3f-430c-b636-387c3b70d15c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714809360 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2714809360
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.119916798
Short name T379
Test name
Test status
Simulation time 347670477 ps
CPU time 1.42 seconds
Started Apr 16 02:21:45 PM PDT 24
Finished Apr 16 02:21:48 PM PDT 24
Peak memory 201936 kb
Host smart-c169cbc3-08c3-4c2d-9d04-f6a4d1177da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119916798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.119916798
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2516562447
Short name T765
Test name
Test status
Simulation time 334683501939 ps
CPU time 197 seconds
Started Apr 16 02:21:40 PM PDT 24
Finished Apr 16 02:24:59 PM PDT 24
Peak memory 202224 kb
Host smart-011839b6-52ce-4dfc-82b7-250556fcc866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516562447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2516562447
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2092661538
Short name T58
Test name
Test status
Simulation time 160907455628 ps
CPU time 89.42 seconds
Started Apr 16 02:21:42 PM PDT 24
Finished Apr 16 02:23:13 PM PDT 24
Peak memory 202180 kb
Host smart-b1ed295d-1ac7-4a38-affb-8d215194856c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092661538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2092661538
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3517252089
Short name T751
Test name
Test status
Simulation time 326986891415 ps
CPU time 388.92 seconds
Started Apr 16 02:21:41 PM PDT 24
Finished Apr 16 02:28:12 PM PDT 24
Peak memory 202316 kb
Host smart-ed5a620d-f1e6-4fee-ac68-b8ea74a95e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517252089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3517252089
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3677209246
Short name T623
Test name
Test status
Simulation time 485853591400 ps
CPU time 1071.34 seconds
Started Apr 16 02:21:41 PM PDT 24
Finished Apr 16 02:39:35 PM PDT 24
Peak memory 202264 kb
Host smart-4f78eccb-8387-44ef-a37f-52e126a24a01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677209246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3677209246
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3254903643
Short name T274
Test name
Test status
Simulation time 525704132661 ps
CPU time 1278.74 seconds
Started Apr 16 02:21:42 PM PDT 24
Finished Apr 16 02:43:03 PM PDT 24
Peak memory 202228 kb
Host smart-92287042-73f7-4e36-a1bc-35500951e742
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254903643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3254903643
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1737630511
Short name T438
Test name
Test status
Simulation time 194091198507 ps
CPU time 80.19 seconds
Started Apr 16 02:21:42 PM PDT 24
Finished Apr 16 02:23:05 PM PDT 24
Peak memory 202176 kb
Host smart-5b5f5c37-d126-46ee-8bf5-731ab7581ad0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737630511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1737630511
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2884688031
Short name T744
Test name
Test status
Simulation time 23920535667 ps
CPU time 14.48 seconds
Started Apr 16 02:21:40 PM PDT 24
Finished Apr 16 02:21:56 PM PDT 24
Peak memory 201952 kb
Host smart-9cdaafb7-345e-4514-a214-a204e805616d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884688031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2884688031
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3334310616
Short name T610
Test name
Test status
Simulation time 3427614041 ps
CPU time 4.97 seconds
Started Apr 16 02:21:41 PM PDT 24
Finished Apr 16 02:21:48 PM PDT 24
Peak memory 202048 kb
Host smart-883a1855-2796-4654-9935-c42c8ae834f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334310616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3334310616
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3970369896
Short name T691
Test name
Test status
Simulation time 5785666430 ps
CPU time 3.93 seconds
Started Apr 16 02:21:42 PM PDT 24
Finished Apr 16 02:21:48 PM PDT 24
Peak memory 202052 kb
Host smart-ea4a989b-2bbe-4764-b820-23f35ae5005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970369896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3970369896
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3442689584
Short name T16
Test name
Test status
Simulation time 23400328892 ps
CPU time 26.92 seconds
Started Apr 16 02:21:44 PM PDT 24
Finished Apr 16 02:22:12 PM PDT 24
Peak memory 202496 kb
Host smart-da28826b-ed6a-4fa7-9454-c6d72feebe68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442689584 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3442689584
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3938867245
Short name T555
Test name
Test status
Simulation time 307004933 ps
CPU time 1.26 seconds
Started Apr 16 02:21:55 PM PDT 24
Finished Apr 16 02:21:59 PM PDT 24
Peak memory 201920 kb
Host smart-a928a256-f7e3-4b8f-b9c1-629c9d21a8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938867245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3938867245
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2951672988
Short name T325
Test name
Test status
Simulation time 203596950929 ps
CPU time 463.31 seconds
Started Apr 16 02:21:46 PM PDT 24
Finished Apr 16 02:29:30 PM PDT 24
Peak memory 202344 kb
Host smart-ddabd2f2-24be-4c7e-86a5-5658d51aeb1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951672988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2951672988
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.341055825
Short name T450
Test name
Test status
Simulation time 492436362878 ps
CPU time 438.73 seconds
Started Apr 16 02:21:46 PM PDT 24
Finished Apr 16 02:29:06 PM PDT 24
Peak memory 202184 kb
Host smart-33d49ac2-808e-4a25-bbb8-ff48a1ac4eb7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=341055825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.341055825
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1165722871
Short name T291
Test name
Test status
Simulation time 492084576420 ps
CPU time 1116.94 seconds
Started Apr 16 02:21:46 PM PDT 24
Finished Apr 16 02:40:24 PM PDT 24
Peak memory 202248 kb
Host smart-c6496a9e-25ab-495b-ae5d-22164ce6f5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165722871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1165722871
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3008643299
Short name T772
Test name
Test status
Simulation time 335114051841 ps
CPU time 419.49 seconds
Started Apr 16 02:21:46 PM PDT 24
Finished Apr 16 02:28:46 PM PDT 24
Peak memory 202372 kb
Host smart-cc403004-ca2a-4cb8-9b39-8469b6b4b6d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008643299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3008643299
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1248577795
Short name T684
Test name
Test status
Simulation time 402726005732 ps
CPU time 224.45 seconds
Started Apr 16 02:21:47 PM PDT 24
Finished Apr 16 02:25:32 PM PDT 24
Peak memory 202240 kb
Host smart-21972d93-1245-43cb-8239-0b0f28f7c23f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248577795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1248577795
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3417102800
Short name T553
Test name
Test status
Simulation time 112640182684 ps
CPU time 566.33 seconds
Started Apr 16 02:21:50 PM PDT 24
Finished Apr 16 02:31:17 PM PDT 24
Peak memory 202520 kb
Host smart-c8455613-7784-421a-8288-7369b93cf32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417102800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3417102800
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1028114338
Short name T629
Test name
Test status
Simulation time 38804981699 ps
CPU time 45.17 seconds
Started Apr 16 02:21:55 PM PDT 24
Finished Apr 16 02:22:43 PM PDT 24
Peak memory 202032 kb
Host smart-61bf7d2c-4a01-4001-861d-0f9d5174f109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028114338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1028114338
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1223855449
Short name T480
Test name
Test status
Simulation time 3895953044 ps
CPU time 10.59 seconds
Started Apr 16 02:21:51 PM PDT 24
Finished Apr 16 02:22:02 PM PDT 24
Peak memory 202060 kb
Host smart-21731984-44ba-4de8-bbe8-58c5d00064f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223855449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1223855449
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2915357380
Short name T131
Test name
Test status
Simulation time 6068788501 ps
CPU time 14.71 seconds
Started Apr 16 02:21:46 PM PDT 24
Finished Apr 16 02:22:02 PM PDT 24
Peak memory 201988 kb
Host smart-72afd0f9-0522-4a5b-9426-bdd2efe028b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915357380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2915357380
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2292066056
Short name T23
Test name
Test status
Simulation time 91000587347 ps
CPU time 227.73 seconds
Started Apr 16 02:21:51 PM PDT 24
Finished Apr 16 02:25:40 PM PDT 24
Peak memory 210940 kb
Host smart-5618f753-feeb-4c17-b20c-703eb55ccfa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292066056 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2292066056
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3139230484
Short name T444
Test name
Test status
Simulation time 519140135 ps
CPU time 1.8 seconds
Started Apr 16 02:22:00 PM PDT 24
Finished Apr 16 02:22:04 PM PDT 24
Peak memory 201980 kb
Host smart-4ec3fdff-8594-4d4e-a79d-bde85fd4f3bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139230484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3139230484
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2277855240
Short name T266
Test name
Test status
Simulation time 521882697390 ps
CPU time 192.97 seconds
Started Apr 16 02:21:55 PM PDT 24
Finished Apr 16 02:25:10 PM PDT 24
Peak memory 202220 kb
Host smart-0606ba97-d86c-4fbd-964a-630e1f1e7b58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277855240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2277855240
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1988394138
Short name T207
Test name
Test status
Simulation time 344399449283 ps
CPU time 214.56 seconds
Started Apr 16 02:21:56 PM PDT 24
Finished Apr 16 02:25:33 PM PDT 24
Peak memory 202172 kb
Host smart-fa99dcc8-fbf1-44d9-9eb2-13b1426309fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988394138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1988394138
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2494295269
Short name T196
Test name
Test status
Simulation time 499881335488 ps
CPU time 1156.04 seconds
Started Apr 16 02:21:55 PM PDT 24
Finished Apr 16 02:41:14 PM PDT 24
Peak memory 202200 kb
Host smart-005dbfa1-788b-4c15-953a-e5c5b0c1533f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494295269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2494295269
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2005499933
Short name T522
Test name
Test status
Simulation time 485268177617 ps
CPU time 1143.74 seconds
Started Apr 16 02:21:52 PM PDT 24
Finished Apr 16 02:40:57 PM PDT 24
Peak memory 202144 kb
Host smart-fa56f437-5126-4750-ac21-16c8a3c42505
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005499933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2005499933
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1647927296
Short name T298
Test name
Test status
Simulation time 325207380952 ps
CPU time 689.98 seconds
Started Apr 16 02:21:49 PM PDT 24
Finished Apr 16 02:33:19 PM PDT 24
Peak memory 202264 kb
Host smart-d0cb1f09-d29a-4faf-b85f-363749e474e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647927296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1647927296
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.725087187
Short name T437
Test name
Test status
Simulation time 320184643706 ps
CPU time 772.5 seconds
Started Apr 16 02:21:51 PM PDT 24
Finished Apr 16 02:34:44 PM PDT 24
Peak memory 202200 kb
Host smart-0eaa8577-ce99-448e-b7b8-a22721cf7546
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=725087187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.725087187
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2450579808
Short name T284
Test name
Test status
Simulation time 248770093245 ps
CPU time 293.37 seconds
Started Apr 16 02:21:55 PM PDT 24
Finished Apr 16 02:26:50 PM PDT 24
Peak memory 202352 kb
Host smart-91d7ee6b-b9fc-4d89-84db-ac0258fb2495
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450579808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2450579808
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1008418425
Short name T421
Test name
Test status
Simulation time 203919656156 ps
CPU time 445.02 seconds
Started Apr 16 02:21:55 PM PDT 24
Finished Apr 16 02:29:23 PM PDT 24
Peak memory 202324 kb
Host smart-683a84b2-be1b-4c64-8cc7-6a8947f2193c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008418425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1008418425
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.162437722
Short name T686
Test name
Test status
Simulation time 80603640765 ps
CPU time 435.57 seconds
Started Apr 16 02:21:59 PM PDT 24
Finished Apr 16 02:29:17 PM PDT 24
Peak memory 202648 kb
Host smart-5a4ada99-95c6-4b61-9e6e-9985a278852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162437722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.162437722
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3092289193
Short name T375
Test name
Test status
Simulation time 40840223527 ps
CPU time 25.71 seconds
Started Apr 16 02:21:55 PM PDT 24
Finished Apr 16 02:22:24 PM PDT 24
Peak memory 202096 kb
Host smart-374c8032-67ee-47d5-8260-beeefe1e0d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092289193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3092289193
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2041273267
Short name T786
Test name
Test status
Simulation time 4713872788 ps
CPU time 3.65 seconds
Started Apr 16 02:21:55 PM PDT 24
Finished Apr 16 02:22:02 PM PDT 24
Peak memory 202056 kb
Host smart-37aa9eaf-b518-4fbc-9d58-eaf46904b1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041273267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2041273267
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1477999902
Short name T499
Test name
Test status
Simulation time 6171542580 ps
CPU time 14.48 seconds
Started Apr 16 02:21:55 PM PDT 24
Finished Apr 16 02:22:12 PM PDT 24
Peak memory 202016 kb
Host smart-2fa44573-3877-4e00-b325-eb23b44fc4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477999902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1477999902
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.99572249
Short name T754
Test name
Test status
Simulation time 193741096065 ps
CPU time 457.03 seconds
Started Apr 16 02:22:01 PM PDT 24
Finished Apr 16 02:29:40 PM PDT 24
Peak memory 202296 kb
Host smart-688b072d-2009-446f-9776-697711dd21ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99572249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.99572249
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.944823258
Short name T785
Test name
Test status
Simulation time 35194250908 ps
CPU time 125.12 seconds
Started Apr 16 02:21:59 PM PDT 24
Finished Apr 16 02:24:06 PM PDT 24
Peak memory 210968 kb
Host smart-837401b5-88c9-487c-bfdd-de8056dd6dbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944823258 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.944823258
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4193090350
Short name T401
Test name
Test status
Simulation time 398194771 ps
CPU time 1.56 seconds
Started Apr 16 02:22:09 PM PDT 24
Finished Apr 16 02:22:11 PM PDT 24
Peak memory 201976 kb
Host smart-fb04a793-58ff-4feb-ac41-37335f4224c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193090350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4193090350
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3593804243
Short name T71
Test name
Test status
Simulation time 329431311400 ps
CPU time 187.96 seconds
Started Apr 16 02:22:05 PM PDT 24
Finished Apr 16 02:25:14 PM PDT 24
Peak memory 202240 kb
Host smart-9a2c620e-f79b-447c-bc36-2f82cefa7f30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593804243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3593804243
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3697430544
Short name T273
Test name
Test status
Simulation time 509890714969 ps
CPU time 1052.94 seconds
Started Apr 16 02:22:07 PM PDT 24
Finished Apr 16 02:39:40 PM PDT 24
Peak memory 202228 kb
Host smart-4246fe1a-3b3d-4680-8ccb-79bd1a1894bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697430544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3697430544
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1921979846
Short name T612
Test name
Test status
Simulation time 325322390931 ps
CPU time 386.47 seconds
Started Apr 16 02:22:02 PM PDT 24
Finished Apr 16 02:28:31 PM PDT 24
Peak memory 202320 kb
Host smart-8e2e8bc7-2007-4a84-b5f7-ca168dac7961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921979846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1921979846
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.571593661
Short name T609
Test name
Test status
Simulation time 489709552835 ps
CPU time 561.13 seconds
Started Apr 16 02:22:04 PM PDT 24
Finished Apr 16 02:31:27 PM PDT 24
Peak memory 202212 kb
Host smart-37a28914-3718-4ae1-b40f-607d32dcf659
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=571593661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.571593661
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2895953154
Short name T717
Test name
Test status
Simulation time 486642753949 ps
CPU time 1046.75 seconds
Started Apr 16 02:22:00 PM PDT 24
Finished Apr 16 02:39:29 PM PDT 24
Peak memory 202296 kb
Host smart-1a43f09f-099e-4526-adb6-084d5795223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895953154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2895953154
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2052820777
Short name T502
Test name
Test status
Simulation time 493349059024 ps
CPU time 1155.71 seconds
Started Apr 16 02:22:02 PM PDT 24
Finished Apr 16 02:41:19 PM PDT 24
Peak memory 202300 kb
Host smart-b1c2e32c-64c0-486a-a0a2-b1f22c7559be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052820777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2052820777
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1046417897
Short name T701
Test name
Test status
Simulation time 399120177379 ps
CPU time 235.58 seconds
Started Apr 16 02:22:05 PM PDT 24
Finished Apr 16 02:26:02 PM PDT 24
Peak memory 202128 kb
Host smart-bc46ea02-747f-489c-87b2-f1e43c180007
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046417897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1046417897
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3052403217
Short name T589
Test name
Test status
Simulation time 83296587416 ps
CPU time 482.95 seconds
Started Apr 16 02:22:10 PM PDT 24
Finished Apr 16 02:30:14 PM PDT 24
Peak memory 202628 kb
Host smart-e68a962a-e9f7-405c-bdc5-2767999c5f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052403217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3052403217
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.907660124
Short name T476
Test name
Test status
Simulation time 44735107870 ps
CPU time 25.05 seconds
Started Apr 16 02:22:10 PM PDT 24
Finished Apr 16 02:22:35 PM PDT 24
Peak memory 202008 kb
Host smart-11003951-5c7b-44b1-8379-a7f4a36c8980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907660124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.907660124
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1856993258
Short name T512
Test name
Test status
Simulation time 4215043994 ps
CPU time 4.19 seconds
Started Apr 16 02:22:07 PM PDT 24
Finished Apr 16 02:22:11 PM PDT 24
Peak memory 202044 kb
Host smart-a978d662-3d86-4616-88a0-ce1145aada73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856993258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1856993258
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.367256637
Short name T107
Test name
Test status
Simulation time 5897394569 ps
CPU time 7.73 seconds
Started Apr 16 02:21:59 PM PDT 24
Finished Apr 16 02:22:09 PM PDT 24
Peak memory 202088 kb
Host smart-f30d2bb1-0bc7-4ec7-a4b9-8e06cef2fea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367256637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.367256637
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3855942127
Short name T726
Test name
Test status
Simulation time 171481437252 ps
CPU time 75.07 seconds
Started Apr 16 02:22:11 PM PDT 24
Finished Apr 16 02:23:27 PM PDT 24
Peak memory 202256 kb
Host smart-44c9f6fa-0a5d-4062-a5f7-8d193f3c88dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855942127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3855942127
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.721744810
Short name T11
Test name
Test status
Simulation time 249829318228 ps
CPU time 62.61 seconds
Started Apr 16 02:22:11 PM PDT 24
Finished Apr 16 02:23:14 PM PDT 24
Peak memory 218972 kb
Host smart-2321dda2-4a1d-4b17-b456-8799f87efb62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721744810 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.721744810
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1723132124
Short name T86
Test name
Test status
Simulation time 394290314 ps
CPU time 1.57 seconds
Started Apr 16 02:22:20 PM PDT 24
Finished Apr 16 02:22:22 PM PDT 24
Peak memory 201952 kb
Host smart-7da9f804-7c78-4c6d-a2d4-263272804046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723132124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1723132124
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2085042306
Short name T667
Test name
Test status
Simulation time 162818018234 ps
CPU time 104.38 seconds
Started Apr 16 02:22:21 PM PDT 24
Finished Apr 16 02:24:06 PM PDT 24
Peak memory 202260 kb
Host smart-cbd652ed-cf3e-4310-a379-45bf57fc33ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085042306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2085042306
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1136326772
Short name T678
Test name
Test status
Simulation time 328764695695 ps
CPU time 197.47 seconds
Started Apr 16 02:22:20 PM PDT 24
Finished Apr 16 02:25:38 PM PDT 24
Peak memory 202184 kb
Host smart-256ef949-7263-4d0f-80ad-ccfe0428997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136326772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1136326772
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.4053660133
Short name T658
Test name
Test status
Simulation time 493822966244 ps
CPU time 741.8 seconds
Started Apr 16 02:22:16 PM PDT 24
Finished Apr 16 02:34:38 PM PDT 24
Peak memory 202216 kb
Host smart-12b27b57-8c04-450f-9211-3b984efde07b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053660133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.4053660133
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1477239769
Short name T782
Test name
Test status
Simulation time 328393267310 ps
CPU time 418.7 seconds
Started Apr 16 02:22:11 PM PDT 24
Finished Apr 16 02:29:11 PM PDT 24
Peak memory 202228 kb
Host smart-11469288-d01e-47bb-b76e-99b25edcc32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477239769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1477239769
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1459863091
Short name T722
Test name
Test status
Simulation time 323852160873 ps
CPU time 749.34 seconds
Started Apr 16 02:22:15 PM PDT 24
Finished Apr 16 02:34:45 PM PDT 24
Peak memory 202176 kb
Host smart-10c97baa-3bb4-44ab-9ed9-4e929a3cd410
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459863091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1459863091
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.583723015
Short name T129
Test name
Test status
Simulation time 402908755367 ps
CPU time 477.26 seconds
Started Apr 16 02:22:15 PM PDT 24
Finished Apr 16 02:30:13 PM PDT 24
Peak memory 202124 kb
Host smart-f9c9f94d-7972-4c63-a521-4cae723ed32c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583723015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.583723015
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3801777337
Short name T762
Test name
Test status
Simulation time 99157901212 ps
CPU time 424.41 seconds
Started Apr 16 02:22:20 PM PDT 24
Finished Apr 16 02:29:25 PM PDT 24
Peak memory 202516 kb
Host smart-e09fbd68-5dc2-4d39-b6ed-762f350b6900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801777337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3801777337
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.602076824
Short name T634
Test name
Test status
Simulation time 34457764430 ps
CPU time 6.54 seconds
Started Apr 16 02:22:20 PM PDT 24
Finished Apr 16 02:22:28 PM PDT 24
Peak memory 202068 kb
Host smart-09778d86-94eb-49b2-baa0-965e5ac2ebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602076824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.602076824
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1067166042
Short name T619
Test name
Test status
Simulation time 2892393063 ps
CPU time 2.32 seconds
Started Apr 16 02:22:20 PM PDT 24
Finished Apr 16 02:22:23 PM PDT 24
Peak memory 202044 kb
Host smart-9bebd85a-b508-42a4-b889-1d47fbad6d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067166042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1067166042
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2779212807
Short name T558
Test name
Test status
Simulation time 5489314525 ps
CPU time 13.41 seconds
Started Apr 16 02:22:10 PM PDT 24
Finished Apr 16 02:22:24 PM PDT 24
Peak memory 202084 kb
Host smart-2b3dc932-9358-4f13-98cf-da77715fdfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779212807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2779212807
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1025705748
Short name T133
Test name
Test status
Simulation time 269698551935 ps
CPU time 952.7 seconds
Started Apr 16 02:22:18 PM PDT 24
Finished Apr 16 02:38:12 PM PDT 24
Peak memory 210848 kb
Host smart-4dd00bed-634e-4c38-905c-015806090efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025705748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1025705748
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3687762381
Short name T327
Test name
Test status
Simulation time 255234049927 ps
CPU time 313.4 seconds
Started Apr 16 02:22:20 PM PDT 24
Finished Apr 16 02:27:34 PM PDT 24
Peak memory 210952 kb
Host smart-1dc1e7f1-4ea1-4d84-85b2-6a5c26dc4a28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687762381 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3687762381
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3694328804
Short name T729
Test name
Test status
Simulation time 342423903 ps
CPU time 1.48 seconds
Started Apr 16 02:20:49 PM PDT 24
Finished Apr 16 02:20:51 PM PDT 24
Peak memory 201960 kb
Host smart-11f35a8c-84d4-4b2a-8015-d6ebbaadd115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694328804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3694328804
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.171928909
Short name T487
Test name
Test status
Simulation time 183379861848 ps
CPU time 430.86 seconds
Started Apr 16 02:20:47 PM PDT 24
Finished Apr 16 02:27:58 PM PDT 24
Peak memory 202324 kb
Host smart-c10a884d-6163-400b-9470-bd3712ceecbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171928909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.171928909
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.506056079
Short name T735
Test name
Test status
Simulation time 156376771077 ps
CPU time 266.13 seconds
Started Apr 16 02:20:44 PM PDT 24
Finished Apr 16 02:25:11 PM PDT 24
Peak memory 202252 kb
Host smart-b14b39b0-eb68-4114-98b8-ba0e0da87852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506056079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.506056079
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.67740197
Short name T738
Test name
Test status
Simulation time 499125288631 ps
CPU time 1164.21 seconds
Started Apr 16 02:20:47 PM PDT 24
Finished Apr 16 02:40:12 PM PDT 24
Peak memory 202252 kb
Host smart-165a0b51-73ad-407e-8b58-94a932dbd9e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=67740197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_
fixed.67740197
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3547676732
Short name T488
Test name
Test status
Simulation time 165581059900 ps
CPU time 27.89 seconds
Started Apr 16 02:20:45 PM PDT 24
Finished Apr 16 02:21:14 PM PDT 24
Peak memory 202256 kb
Host smart-e31b26ed-9807-40f3-ad10-10f8f9415d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547676732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3547676732
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2039634613
Short name T163
Test name
Test status
Simulation time 160232971049 ps
CPU time 39.46 seconds
Started Apr 16 02:20:46 PM PDT 24
Finished Apr 16 02:21:26 PM PDT 24
Peak memory 202264 kb
Host smart-f5539238-321a-4396-b4dc-5d3c4a893145
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039634613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2039634613
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3201190002
Short name T792
Test name
Test status
Simulation time 219768324151 ps
CPU time 467.38 seconds
Started Apr 16 02:20:45 PM PDT 24
Finished Apr 16 02:28:33 PM PDT 24
Peak memory 202232 kb
Host smart-fcb250dd-c960-4f30-abc1-794a9afb7f62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201190002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3201190002
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2803823190
Short name T365
Test name
Test status
Simulation time 118510654369 ps
CPU time 676.19 seconds
Started Apr 16 02:20:53 PM PDT 24
Finished Apr 16 02:32:10 PM PDT 24
Peak memory 202676 kb
Host smart-5f30029f-1a2f-416d-b629-c03a947e695d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803823190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2803823190
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3252250556
Short name T472
Test name
Test status
Simulation time 48251811504 ps
CPU time 60.86 seconds
Started Apr 16 02:20:54 PM PDT 24
Finished Apr 16 02:21:56 PM PDT 24
Peak memory 202072 kb
Host smart-9278a58f-5ced-4c28-88cc-e2a938207b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252250556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3252250556
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3454728225
Short name T448
Test name
Test status
Simulation time 5070803420 ps
CPU time 10.04 seconds
Started Apr 16 02:20:46 PM PDT 24
Finished Apr 16 02:20:57 PM PDT 24
Peak memory 202036 kb
Host smart-67f3d257-abba-49ec-8444-1fcf055f3453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454728225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3454728225
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1593225527
Short name T80
Test name
Test status
Simulation time 4264176289 ps
CPU time 11.08 seconds
Started Apr 16 02:20:58 PM PDT 24
Finished Apr 16 02:21:10 PM PDT 24
Peak memory 217760 kb
Host smart-1cc0f1ad-5a51-4cf2-afe2-ceb49bd2e40e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593225527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1593225527
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3658283226
Short name T741
Test name
Test status
Simulation time 5888795071 ps
CPU time 8.04 seconds
Started Apr 16 02:20:46 PM PDT 24
Finished Apr 16 02:20:55 PM PDT 24
Peak memory 202064 kb
Host smart-af935450-318d-462d-9388-dbeca8d865a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658283226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3658283226
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2757323604
Short name T219
Test name
Test status
Simulation time 376836189311 ps
CPU time 782.85 seconds
Started Apr 16 02:20:47 PM PDT 24
Finished Apr 16 02:33:51 PM PDT 24
Peak memory 202268 kb
Host smart-d155370f-afa4-42ac-a9cb-3258527b79dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757323604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2757323604
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3091824127
Short name T233
Test name
Test status
Simulation time 206559562354 ps
CPU time 90 seconds
Started Apr 16 02:20:52 PM PDT 24
Finished Apr 16 02:22:22 PM PDT 24
Peak memory 211888 kb
Host smart-5800e1e6-b075-4d74-a5f3-e242293977bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091824127 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3091824127
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.201694924
Short name T430
Test name
Test status
Simulation time 352631256 ps
CPU time 0.84 seconds
Started Apr 16 02:22:37 PM PDT 24
Finished Apr 16 02:22:39 PM PDT 24
Peak memory 201932 kb
Host smart-409bda0d-f689-4a4b-b114-c55f4443d3d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201694924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.201694924
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1935676498
Short name T243
Test name
Test status
Simulation time 355172914469 ps
CPU time 332.11 seconds
Started Apr 16 02:22:36 PM PDT 24
Finished Apr 16 02:28:09 PM PDT 24
Peak memory 202316 kb
Host smart-fde56a8a-a167-47a0-95ad-ce4890cdcdca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935676498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1935676498
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3009795715
Short name T795
Test name
Test status
Simulation time 351357914764 ps
CPU time 749.91 seconds
Started Apr 16 02:22:34 PM PDT 24
Finished Apr 16 02:35:05 PM PDT 24
Peak memory 202184 kb
Host smart-8e6027e1-f9a8-4462-af38-a0f5e0f5ba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009795715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3009795715
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.776596915
Short name T191
Test name
Test status
Simulation time 325554437286 ps
CPU time 211.46 seconds
Started Apr 16 02:22:26 PM PDT 24
Finished Apr 16 02:25:59 PM PDT 24
Peak memory 202200 kb
Host smart-30176a6d-3754-4676-8fcb-94bf31982828
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=776596915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.776596915
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2883854770
Short name T183
Test name
Test status
Simulation time 487578874700 ps
CPU time 438.98 seconds
Started Apr 16 02:22:26 PM PDT 24
Finished Apr 16 02:29:45 PM PDT 24
Peak memory 202288 kb
Host smart-2d382b08-6174-4bce-a517-0036975d980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883854770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2883854770
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1214146563
Short name T526
Test name
Test status
Simulation time 160999807250 ps
CPU time 400.89 seconds
Started Apr 16 02:22:24 PM PDT 24
Finished Apr 16 02:29:06 PM PDT 24
Peak memory 202216 kb
Host smart-c1b0e16c-c770-4fe4-a5a8-ab3fafa0c990
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214146563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1214146563
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3229664515
Short name T108
Test name
Test status
Simulation time 390781432177 ps
CPU time 204.25 seconds
Started Apr 16 02:22:26 PM PDT 24
Finished Apr 16 02:25:51 PM PDT 24
Peak memory 202276 kb
Host smart-b3e398d3-07c1-48aa-aeb6-e4854ee12286
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229664515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3229664515
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.4276467366
Short name T694
Test name
Test status
Simulation time 583319086408 ps
CPU time 664.35 seconds
Started Apr 16 02:22:27 PM PDT 24
Finished Apr 16 02:33:32 PM PDT 24
Peak memory 202124 kb
Host smart-0474d149-bc9e-41fd-9172-2647ba7aba13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276467366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.4276467366
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2369882289
Short name T359
Test name
Test status
Simulation time 64673100462 ps
CPU time 288.04 seconds
Started Apr 16 02:22:38 PM PDT 24
Finished Apr 16 02:27:27 PM PDT 24
Peak memory 202632 kb
Host smart-a433ae7d-2903-4d17-8c03-ec7523025e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369882289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2369882289
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.84977920
Short name T622
Test name
Test status
Simulation time 27663396364 ps
CPU time 23.66 seconds
Started Apr 16 02:22:35 PM PDT 24
Finished Apr 16 02:22:59 PM PDT 24
Peak memory 202072 kb
Host smart-be3b6fac-b157-44e1-b1cb-8b676bccd046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84977920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.84977920
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2583704795
Short name T659
Test name
Test status
Simulation time 5513587049 ps
CPU time 15.42 seconds
Started Apr 16 02:22:33 PM PDT 24
Finished Apr 16 02:22:50 PM PDT 24
Peak memory 202052 kb
Host smart-36ab6a6e-5297-4ca4-9cc7-6456e84df6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583704795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2583704795
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2247790781
Short name T528
Test name
Test status
Simulation time 5572275545 ps
CPU time 2.46 seconds
Started Apr 16 02:22:23 PM PDT 24
Finished Apr 16 02:22:26 PM PDT 24
Peak memory 202052 kb
Host smart-10ba473f-d544-41ea-b968-49e966234c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247790781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2247790781
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3490295721
Short name T323
Test name
Test status
Simulation time 25501796599 ps
CPU time 32.24 seconds
Started Apr 16 02:22:37 PM PDT 24
Finished Apr 16 02:23:10 PM PDT 24
Peak memory 210608 kb
Host smart-feb51a49-3f4f-4bd7-b85b-594168f41d56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490295721 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3490295721
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4203449852
Short name T374
Test name
Test status
Simulation time 513169224 ps
CPU time 0.93 seconds
Started Apr 16 02:22:46 PM PDT 24
Finished Apr 16 02:22:47 PM PDT 24
Peak memory 202008 kb
Host smart-a88aa28d-7a5d-4734-b89c-d2c363c08d01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203449852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4203449852
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3493628826
Short name T201
Test name
Test status
Simulation time 555292582870 ps
CPU time 312.33 seconds
Started Apr 16 02:22:40 PM PDT 24
Finished Apr 16 02:27:53 PM PDT 24
Peak memory 202220 kb
Host smart-f2439bf5-fe47-46ca-ab60-c996f22d2336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493628826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3493628826
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1466572717
Short name T336
Test name
Test status
Simulation time 492955926316 ps
CPU time 1118.32 seconds
Started Apr 16 02:22:37 PM PDT 24
Finished Apr 16 02:41:16 PM PDT 24
Peak memory 202352 kb
Host smart-517bd619-35bd-4e44-b7e1-1f4f117cc39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466572717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1466572717
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3338006567
Short name T433
Test name
Test status
Simulation time 486045681813 ps
CPU time 293.34 seconds
Started Apr 16 02:22:38 PM PDT 24
Finished Apr 16 02:27:32 PM PDT 24
Peak memory 202212 kb
Host smart-199e4bed-8e14-4f6a-8b22-4e642280febe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338006567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3338006567
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.194350167
Short name T763
Test name
Test status
Simulation time 495833831485 ps
CPU time 268.52 seconds
Started Apr 16 02:22:37 PM PDT 24
Finished Apr 16 02:27:06 PM PDT 24
Peak memory 202328 kb
Host smart-47a195ea-6449-4a38-bdb5-0da31f3798ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194350167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.194350167
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2535564846
Short name T655
Test name
Test status
Simulation time 332158969294 ps
CPU time 189.11 seconds
Started Apr 16 02:22:38 PM PDT 24
Finished Apr 16 02:25:48 PM PDT 24
Peak memory 202156 kb
Host smart-55dfe16c-ca21-40c7-b76b-db0b7231c3a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535564846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2535564846
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2511223476
Short name T585
Test name
Test status
Simulation time 192212906049 ps
CPU time 391.5 seconds
Started Apr 16 02:22:39 PM PDT 24
Finished Apr 16 02:29:11 PM PDT 24
Peak memory 202264 kb
Host smart-0fb2cc0e-2ff0-4995-8338-b7f8a14fe0e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511223476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2511223476
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.124921028
Short name T753
Test name
Test status
Simulation time 576638651977 ps
CPU time 673.21 seconds
Started Apr 16 02:22:36 PM PDT 24
Finished Apr 16 02:33:50 PM PDT 24
Peak memory 202208 kb
Host smart-214e075e-cc87-40ee-8b7c-4c0a7c775e1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124921028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.124921028
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2714053701
Short name T65
Test name
Test status
Simulation time 90686448353 ps
CPU time 489.83 seconds
Started Apr 16 02:22:40 PM PDT 24
Finished Apr 16 02:30:50 PM PDT 24
Peak memory 202668 kb
Host smart-e589f0b1-10ee-48bd-912e-64cb4acefc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714053701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2714053701
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.25855348
Short name T671
Test name
Test status
Simulation time 42546037132 ps
CPU time 98.09 seconds
Started Apr 16 02:22:42 PM PDT 24
Finished Apr 16 02:24:20 PM PDT 24
Peak memory 202064 kb
Host smart-efbc8710-3ab6-429c-b9c0-76f967bf5e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25855348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.25855348
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.4023587069
Short name T592
Test name
Test status
Simulation time 3241103076 ps
CPU time 1.69 seconds
Started Apr 16 02:22:40 PM PDT 24
Finished Apr 16 02:22:42 PM PDT 24
Peak memory 202032 kb
Host smart-5a8dd1a9-55a7-4f79-8e59-e09861d08727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023587069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4023587069
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2243499599
Short name T569
Test name
Test status
Simulation time 5809303847 ps
CPU time 14.88 seconds
Started Apr 16 02:22:36 PM PDT 24
Finished Apr 16 02:22:52 PM PDT 24
Peak memory 202068 kb
Host smart-f816d4f9-f098-4845-8920-78cd716b04e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243499599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2243499599
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3246254326
Short name T581
Test name
Test status
Simulation time 204433148275 ps
CPU time 258.01 seconds
Started Apr 16 02:22:46 PM PDT 24
Finished Apr 16 02:27:05 PM PDT 24
Peak memory 202272 kb
Host smart-93c61dc5-e513-455b-a7d0-ff8922465557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246254326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3246254326
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.686887885
Short name T319
Test name
Test status
Simulation time 512746778078 ps
CPU time 909.23 seconds
Started Apr 16 02:22:48 PM PDT 24
Finished Apr 16 02:37:58 PM PDT 24
Peak memory 210856 kb
Host smart-8ad966f2-9058-41e2-a1d0-62e9c8be3c21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686887885 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.686887885
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.976296062
Short name T198
Test name
Test status
Simulation time 485166673 ps
CPU time 1.35 seconds
Started Apr 16 02:22:51 PM PDT 24
Finished Apr 16 02:22:53 PM PDT 24
Peak memory 201960 kb
Host smart-47998a22-3f62-46f2-b488-ffb11527d520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976296062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.976296062
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3628513424
Short name T312
Test name
Test status
Simulation time 328301545736 ps
CPU time 336.16 seconds
Started Apr 16 02:22:47 PM PDT 24
Finished Apr 16 02:28:24 PM PDT 24
Peak memory 202244 kb
Host smart-9735b583-fc3c-421e-9cb6-2ad74b7ff447
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628513424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3628513424
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1520698335
Short name T334
Test name
Test status
Simulation time 327894472420 ps
CPU time 768.94 seconds
Started Apr 16 02:22:49 PM PDT 24
Finished Apr 16 02:35:39 PM PDT 24
Peak memory 202304 kb
Host smart-7cfba9d4-f2b6-4a33-85a5-5e2a0851dbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520698335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1520698335
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3571059372
Short name T707
Test name
Test status
Simulation time 478658018174 ps
CPU time 1136.06 seconds
Started Apr 16 02:22:48 PM PDT 24
Finished Apr 16 02:41:44 PM PDT 24
Peak memory 202332 kb
Host smart-cbc44a3a-590e-4208-8bcf-7524f004d065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571059372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3571059372
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1601151844
Short name T377
Test name
Test status
Simulation time 168652067895 ps
CPU time 94.78 seconds
Started Apr 16 02:22:46 PM PDT 24
Finished Apr 16 02:24:21 PM PDT 24
Peak memory 202188 kb
Host smart-612d8afd-c84f-4e6c-a44a-0f9b9ee727c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601151844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1601151844
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.982596333
Short name T194
Test name
Test status
Simulation time 491791710306 ps
CPU time 269.12 seconds
Started Apr 16 02:22:47 PM PDT 24
Finished Apr 16 02:27:17 PM PDT 24
Peak memory 202176 kb
Host smart-dbd053e3-95b8-456f-9b89-5d1168f85a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982596333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.982596333
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.439417573
Short name T693
Test name
Test status
Simulation time 164823344135 ps
CPU time 410.06 seconds
Started Apr 16 02:22:48 PM PDT 24
Finished Apr 16 02:29:39 PM PDT 24
Peak memory 202152 kb
Host smart-b1398bae-662b-4bba-bcff-aaf2140d153b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=439417573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.439417573
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3911825348
Short name T615
Test name
Test status
Simulation time 181377874376 ps
CPU time 417.09 seconds
Started Apr 16 02:22:48 PM PDT 24
Finished Apr 16 02:29:46 PM PDT 24
Peak memory 202260 kb
Host smart-678b7e89-96e9-4056-95fa-fd8c0d2c8a8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911825348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3911825348
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2365100495
Short name T547
Test name
Test status
Simulation time 398378765448 ps
CPU time 223.09 seconds
Started Apr 16 02:22:45 PM PDT 24
Finished Apr 16 02:26:28 PM PDT 24
Peak memory 202208 kb
Host smart-b11be355-9146-4eb5-9acb-57b6c8bb171a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365100495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2365100495
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2856204587
Short name T800
Test name
Test status
Simulation time 122426582456 ps
CPU time 651.89 seconds
Started Apr 16 02:22:50 PM PDT 24
Finished Apr 16 02:33:43 PM PDT 24
Peak memory 202616 kb
Host smart-0a3601ca-858d-42a6-b74a-b62e5c61c26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856204587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2856204587
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1385575137
Short name T382
Test name
Test status
Simulation time 38747205226 ps
CPU time 87.62 seconds
Started Apr 16 02:22:50 PM PDT 24
Finished Apr 16 02:24:18 PM PDT 24
Peak memory 201256 kb
Host smart-223d3f0b-5c5b-476d-8333-889597dd8911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385575137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1385575137
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.4052830783
Short name T666
Test name
Test status
Simulation time 4253214317 ps
CPU time 3.3 seconds
Started Apr 16 02:22:51 PM PDT 24
Finished Apr 16 02:22:55 PM PDT 24
Peak memory 201248 kb
Host smart-13b46f63-8488-4ad2-9e41-6c3ae2966fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052830783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.4052830783
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2184685918
Short name T778
Test name
Test status
Simulation time 5621683728 ps
CPU time 4.01 seconds
Started Apr 16 02:22:47 PM PDT 24
Finished Apr 16 02:22:52 PM PDT 24
Peak memory 202056 kb
Host smart-4babfd23-68e7-4c02-8ef5-4bdeb9287cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184685918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2184685918
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.607200525
Short name T279
Test name
Test status
Simulation time 331615199333 ps
CPU time 196.24 seconds
Started Apr 16 02:22:49 PM PDT 24
Finished Apr 16 02:26:06 PM PDT 24
Peak memory 202212 kb
Host smart-597f1b64-2d83-4f05-992b-c8108a640bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607200525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
607200525
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1837459053
Short name T114
Test name
Test status
Simulation time 110575321694 ps
CPU time 155.64 seconds
Started Apr 16 02:22:51 PM PDT 24
Finished Apr 16 02:25:27 PM PDT 24
Peak memory 210824 kb
Host smart-52d5dbee-2e03-483f-a45b-916cd337bb59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837459053 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1837459053
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2989111685
Short name T793
Test name
Test status
Simulation time 441443842 ps
CPU time 0.94 seconds
Started Apr 16 02:23:03 PM PDT 24
Finished Apr 16 02:23:05 PM PDT 24
Peak memory 201968 kb
Host smart-23938e9c-b663-4745-a673-553832a66b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989111685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2989111685
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1057185857
Short name T697
Test name
Test status
Simulation time 328739682358 ps
CPU time 406.48 seconds
Started Apr 16 02:22:54 PM PDT 24
Finished Apr 16 02:29:42 PM PDT 24
Peak memory 202364 kb
Host smart-390c072c-29f4-466b-bcf4-8f9eadb2d88d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057185857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1057185857
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.4142770206
Short name T624
Test name
Test status
Simulation time 520346948986 ps
CPU time 617.59 seconds
Started Apr 16 02:22:55 PM PDT 24
Finished Apr 16 02:33:14 PM PDT 24
Peak memory 202176 kb
Host smart-7a19fe66-c67b-4035-ae25-d37ed7ccca64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142770206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4142770206
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2552108466
Short name T574
Test name
Test status
Simulation time 491688008918 ps
CPU time 559.51 seconds
Started Apr 16 02:22:54 PM PDT 24
Finished Apr 16 02:32:14 PM PDT 24
Peak memory 202216 kb
Host smart-b7031ca8-f719-4047-9a0d-60a9c58579e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552108466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2552108466
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2483629291
Short name T780
Test name
Test status
Simulation time 327297558648 ps
CPU time 133.66 seconds
Started Apr 16 02:22:54 PM PDT 24
Finished Apr 16 02:25:09 PM PDT 24
Peak memory 202172 kb
Host smart-835657da-8975-4afb-96c2-f46e91f66bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483629291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2483629291
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.569955499
Short name T554
Test name
Test status
Simulation time 162297900586 ps
CPU time 90.22 seconds
Started Apr 16 02:22:52 PM PDT 24
Finished Apr 16 02:24:23 PM PDT 24
Peak memory 202180 kb
Host smart-4c18cde2-54c2-4791-8893-e711464ef2ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=569955499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.569955499
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.662337476
Short name T533
Test name
Test status
Simulation time 168132599514 ps
CPU time 23.83 seconds
Started Apr 16 02:22:56 PM PDT 24
Finished Apr 16 02:23:20 PM PDT 24
Peak memory 202180 kb
Host smart-d0218234-2457-45e3-aaa8-32f507baf124
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662337476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.662337476
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2777010417
Short name T406
Test name
Test status
Simulation time 602605685552 ps
CPU time 1347.13 seconds
Started Apr 16 02:22:53 PM PDT 24
Finished Apr 16 02:45:20 PM PDT 24
Peak memory 202216 kb
Host smart-6fd1acbf-6c34-41fa-bcad-efcd0bfe1624
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777010417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2777010417
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3347433757
Short name T358
Test name
Test status
Simulation time 124971985056 ps
CPU time 647.25 seconds
Started Apr 16 02:22:57 PM PDT 24
Finished Apr 16 02:33:45 PM PDT 24
Peak memory 202548 kb
Host smart-26f62ae4-6a25-4d04-aea2-155bd242d9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347433757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3347433757
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1080480989
Short name T393
Test name
Test status
Simulation time 47056047092 ps
CPU time 55.85 seconds
Started Apr 16 02:23:02 PM PDT 24
Finished Apr 16 02:23:59 PM PDT 24
Peak memory 202100 kb
Host smart-06058473-558a-4190-9077-c98d26d32f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080480989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1080480989
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2024585964
Short name T113
Test name
Test status
Simulation time 4125710383 ps
CPU time 10.42 seconds
Started Apr 16 02:22:54 PM PDT 24
Finished Apr 16 02:23:05 PM PDT 24
Peak memory 202008 kb
Host smart-7d2561d3-1fe0-4260-9762-a0367c88a78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024585964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2024585964
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2489601768
Short name T455
Test name
Test status
Simulation time 5851702533 ps
CPU time 14.83 seconds
Started Apr 16 02:22:49 PM PDT 24
Finished Apr 16 02:23:05 PM PDT 24
Peak memory 202060 kb
Host smart-3346d795-3df5-4a36-a1ca-147c94b70a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489601768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2489601768
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2894491238
Short name T733
Test name
Test status
Simulation time 311397691506 ps
CPU time 870.86 seconds
Started Apr 16 02:23:03 PM PDT 24
Finished Apr 16 02:37:35 PM PDT 24
Peak memory 210764 kb
Host smart-c8ff26c6-c52d-45b2-9d0a-a704f8bdc8bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894491238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2894491238
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.634604180
Short name T267
Test name
Test status
Simulation time 32559138792 ps
CPU time 72.05 seconds
Started Apr 16 02:22:59 PM PDT 24
Finished Apr 16 02:24:12 PM PDT 24
Peak memory 210900 kb
Host smart-2f53904b-a508-4635-a943-3e91bfa7b9e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634604180 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.634604180
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3347690541
Short name T4
Test name
Test status
Simulation time 502485440 ps
CPU time 1.79 seconds
Started Apr 16 02:23:06 PM PDT 24
Finished Apr 16 02:23:09 PM PDT 24
Peak memory 202004 kb
Host smart-634269ea-c6b3-4280-ac31-aca6d552d319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347690541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3347690541
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.547655522
Short name T122
Test name
Test status
Simulation time 565093689385 ps
CPU time 118.61 seconds
Started Apr 16 02:23:03 PM PDT 24
Finished Apr 16 02:25:03 PM PDT 24
Peak memory 202328 kb
Host smart-02c99ab3-cc92-4d99-b795-9afc8f591f31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547655522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.547655522
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.4207197320
Short name T749
Test name
Test status
Simulation time 191577440462 ps
CPU time 71.72 seconds
Started Apr 16 02:23:03 PM PDT 24
Finished Apr 16 02:24:16 PM PDT 24
Peak memory 202248 kb
Host smart-4a596224-777d-43fb-90c9-6b161334792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207197320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4207197320
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1381039488
Short name T177
Test name
Test status
Simulation time 168277615095 ps
CPU time 360.04 seconds
Started Apr 16 02:22:57 PM PDT 24
Finished Apr 16 02:28:58 PM PDT 24
Peak memory 202352 kb
Host smart-36e75544-a8ab-4f5e-a367-efa0aaf291e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381039488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1381039488
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4066584119
Short name T789
Test name
Test status
Simulation time 488665702988 ps
CPU time 1227.02 seconds
Started Apr 16 02:22:57 PM PDT 24
Finished Apr 16 02:43:25 PM PDT 24
Peak memory 202200 kb
Host smart-a234cf29-d182-48c2-99f1-380117f5c8aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066584119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.4066584119
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1793144240
Short name T203
Test name
Test status
Simulation time 494086600232 ps
CPU time 371.81 seconds
Started Apr 16 02:22:57 PM PDT 24
Finished Apr 16 02:29:10 PM PDT 24
Peak memory 202232 kb
Host smart-bddd76a6-254a-417b-923e-0504724ae1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793144240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1793144240
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2172033592
Short name T188
Test name
Test status
Simulation time 326755386099 ps
CPU time 724.3 seconds
Started Apr 16 02:22:58 PM PDT 24
Finished Apr 16 02:35:03 PM PDT 24
Peak memory 202324 kb
Host smart-f4ef0ce2-9617-4f39-8086-6e99a7e80902
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172033592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2172033592
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3595341286
Short name T250
Test name
Test status
Simulation time 560606480939 ps
CPU time 224.82 seconds
Started Apr 16 02:22:58 PM PDT 24
Finished Apr 16 02:26:43 PM PDT 24
Peak memory 202368 kb
Host smart-fe4d88bf-13ea-4a1a-89e8-be3d485f756c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595341286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3595341286
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.789838486
Short name T586
Test name
Test status
Simulation time 598314756465 ps
CPU time 366.32 seconds
Started Apr 16 02:23:01 PM PDT 24
Finished Apr 16 02:29:07 PM PDT 24
Peak memory 202288 kb
Host smart-20d91d2e-4112-45e6-a575-225b1badef65
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789838486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.789838486
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2457144010
Short name T568
Test name
Test status
Simulation time 125276941454 ps
CPU time 514.89 seconds
Started Apr 16 02:23:03 PM PDT 24
Finished Apr 16 02:31:39 PM PDT 24
Peak memory 202604 kb
Host smart-4be729e9-7fe7-4197-affb-0cebb670a7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457144010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2457144010
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3784531251
Short name T643
Test name
Test status
Simulation time 41191117280 ps
CPU time 22.93 seconds
Started Apr 16 02:23:03 PM PDT 24
Finished Apr 16 02:23:27 PM PDT 24
Peak memory 202040 kb
Host smart-eacdec53-4a88-4dad-8e71-4d6fd483200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784531251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3784531251
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1339578047
Short name T618
Test name
Test status
Simulation time 4922454577 ps
CPU time 3.95 seconds
Started Apr 16 02:23:01 PM PDT 24
Finished Apr 16 02:23:06 PM PDT 24
Peak memory 202072 kb
Host smart-f937fd7f-b96a-4d50-bc1c-ffe3cd8606fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339578047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1339578047
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2510739433
Short name T709
Test name
Test status
Simulation time 5639923162 ps
CPU time 7.2 seconds
Started Apr 16 02:22:58 PM PDT 24
Finished Apr 16 02:23:06 PM PDT 24
Peak memory 202052 kb
Host smart-43178bd5-48ed-4aa0-a68a-68b5dd8934c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510739433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2510739433
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2484479779
Short name T285
Test name
Test status
Simulation time 379043607293 ps
CPU time 1146.86 seconds
Started Apr 16 02:23:08 PM PDT 24
Finished Apr 16 02:42:16 PM PDT 24
Peak memory 210864 kb
Host smart-61709e30-2529-4fe9-812c-efc955eff511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484479779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2484479779
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1221226587
Short name T384
Test name
Test status
Simulation time 291827439 ps
CPU time 1.29 seconds
Started Apr 16 02:23:20 PM PDT 24
Finished Apr 16 02:23:22 PM PDT 24
Peak memory 201948 kb
Host smart-6dc6f2a1-288c-4a45-b551-34d742500e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221226587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1221226587
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.91784123
Short name T185
Test name
Test status
Simulation time 493050763824 ps
CPU time 104.54 seconds
Started Apr 16 02:23:14 PM PDT 24
Finished Apr 16 02:24:59 PM PDT 24
Peak memory 202296 kb
Host smart-96c813c4-3b5a-477b-8fd6-dc16f9fe4b84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91784123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gatin
g.91784123
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.403413935
Short name T213
Test name
Test status
Simulation time 173040165826 ps
CPU time 253.07 seconds
Started Apr 16 02:23:16 PM PDT 24
Finished Apr 16 02:27:29 PM PDT 24
Peak memory 202296 kb
Host smart-e4a935b8-d87f-4cf2-bdbc-f2588c83e23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403413935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.403413935
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3977495770
Short name T195
Test name
Test status
Simulation time 493094957890 ps
CPU time 246.99 seconds
Started Apr 16 02:23:09 PM PDT 24
Finished Apr 16 02:27:17 PM PDT 24
Peak memory 202220 kb
Host smart-8391c80d-170d-4ff9-842d-363d5ba6e68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977495770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3977495770
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3854761559
Short name T550
Test name
Test status
Simulation time 329776117416 ps
CPU time 654.31 seconds
Started Apr 16 02:23:12 PM PDT 24
Finished Apr 16 02:34:07 PM PDT 24
Peak memory 202148 kb
Host smart-25df8d00-dee7-45ee-bfc4-0319da619c02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854761559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3854761559
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3238775133
Short name T584
Test name
Test status
Simulation time 160561137888 ps
CPU time 370.12 seconds
Started Apr 16 02:23:06 PM PDT 24
Finished Apr 16 02:29:17 PM PDT 24
Peak memory 202128 kb
Host smart-95497fbb-346f-40c1-881e-03ffe18b014a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238775133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3238775133
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2799618704
Short name T725
Test name
Test status
Simulation time 493169636782 ps
CPU time 1160.57 seconds
Started Apr 16 02:23:12 PM PDT 24
Finished Apr 16 02:42:34 PM PDT 24
Peak memory 201492 kb
Host smart-3e19e479-4391-4efc-b7e5-3b8e19d22fb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799618704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2799618704
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.382506962
Short name T642
Test name
Test status
Simulation time 193047071139 ps
CPU time 411.36 seconds
Started Apr 16 02:23:10 PM PDT 24
Finished Apr 16 02:30:02 PM PDT 24
Peak memory 202192 kb
Host smart-37750149-cb42-4476-8639-9604041a5e8e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382506962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.382506962
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2027592801
Short name T720
Test name
Test status
Simulation time 105269280551 ps
CPU time 370.69 seconds
Started Apr 16 02:23:14 PM PDT 24
Finished Apr 16 02:29:25 PM PDT 24
Peak memory 202412 kb
Host smart-afb2ce79-e372-4d8e-8041-8f185540eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027592801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2027592801
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.611358951
Short name T408
Test name
Test status
Simulation time 24280212077 ps
CPU time 15.36 seconds
Started Apr 16 02:23:13 PM PDT 24
Finished Apr 16 02:23:29 PM PDT 24
Peak memory 201232 kb
Host smart-9d8d5048-e433-4367-8ddb-238df4f8e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611358951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.611358951
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2634593822
Short name T6
Test name
Test status
Simulation time 4675752578 ps
CPU time 10.56 seconds
Started Apr 16 02:23:15 PM PDT 24
Finished Apr 16 02:23:26 PM PDT 24
Peak memory 202044 kb
Host smart-6c848d2e-f909-476e-84d5-f41c893efe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634593822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2634593822
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1306671247
Short name T613
Test name
Test status
Simulation time 6043473822 ps
CPU time 14.09 seconds
Started Apr 16 02:23:06 PM PDT 24
Finished Apr 16 02:23:21 PM PDT 24
Peak memory 202076 kb
Host smart-fc3db96e-2451-42fc-9731-29cbc0e760aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306671247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1306671247
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2051674704
Short name T303
Test name
Test status
Simulation time 693792679329 ps
CPU time 273.46 seconds
Started Apr 16 02:23:18 PM PDT 24
Finished Apr 16 02:27:52 PM PDT 24
Peak memory 202328 kb
Host smart-930b5549-e9d5-4990-afd2-2991d43a8aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051674704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2051674704
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3042857952
Short name T654
Test name
Test status
Simulation time 60565224739 ps
CPU time 132.85 seconds
Started Apr 16 02:23:15 PM PDT 24
Finished Apr 16 02:25:29 PM PDT 24
Peak memory 210560 kb
Host smart-0cc5b183-80f0-4195-bb50-575aeea90b79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042857952 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3042857952
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4048775941
Short name T460
Test name
Test status
Simulation time 434845325 ps
CPU time 0.8 seconds
Started Apr 16 02:23:34 PM PDT 24
Finished Apr 16 02:23:36 PM PDT 24
Peak memory 201952 kb
Host smart-abed5de1-d954-498f-8fb2-161572574ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048775941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4048775941
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1864805705
Short name T695
Test name
Test status
Simulation time 167582822248 ps
CPU time 98.45 seconds
Started Apr 16 02:23:24 PM PDT 24
Finished Apr 16 02:25:03 PM PDT 24
Peak memory 202320 kb
Host smart-7f708e62-93b1-4edf-9171-b72d955cd903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864805705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1864805705
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1202285386
Short name T330
Test name
Test status
Simulation time 323658591533 ps
CPU time 749.28 seconds
Started Apr 16 02:23:24 PM PDT 24
Finished Apr 16 02:35:54 PM PDT 24
Peak memory 202276 kb
Host smart-4e9620e7-2622-4fe9-be42-ba96be2931e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202285386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1202285386
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3973706707
Short name T591
Test name
Test status
Simulation time 510708393056 ps
CPU time 1300.08 seconds
Started Apr 16 02:23:24 PM PDT 24
Finished Apr 16 02:45:04 PM PDT 24
Peak memory 202204 kb
Host smart-33380c66-a9ef-469a-8130-08cba0628bc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973706707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3973706707
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1292710203
Short name T731
Test name
Test status
Simulation time 326330133916 ps
CPU time 769.92 seconds
Started Apr 16 02:23:20 PM PDT 24
Finished Apr 16 02:36:10 PM PDT 24
Peak memory 202224 kb
Host smart-68f276d6-2fec-4868-94ac-a83ec892d25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292710203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1292710203
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1876396729
Short name T394
Test name
Test status
Simulation time 328776243718 ps
CPU time 360.01 seconds
Started Apr 16 02:23:19 PM PDT 24
Finished Apr 16 02:29:19 PM PDT 24
Peak memory 202240 kb
Host smart-5335e766-e6f2-44f1-9e97-6bb4af4c092f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876396729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1876396729
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.836091230
Short name T674
Test name
Test status
Simulation time 343953063569 ps
CPU time 335.21 seconds
Started Apr 16 02:23:24 PM PDT 24
Finished Apr 16 02:29:00 PM PDT 24
Peak memory 202260 kb
Host smart-f800694b-d27f-4bf9-8f37-8fe905ad5e7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836091230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.836091230
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.732459008
Short name T447
Test name
Test status
Simulation time 389567386763 ps
CPU time 211.3 seconds
Started Apr 16 02:23:22 PM PDT 24
Finished Apr 16 02:26:53 PM PDT 24
Peak memory 202300 kb
Host smart-fb868036-1b25-49ea-a185-6ac504d0d408
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732459008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.732459008
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1612131081
Short name T500
Test name
Test status
Simulation time 98231315030 ps
CPU time 322.56 seconds
Started Apr 16 02:23:28 PM PDT 24
Finished Apr 16 02:28:51 PM PDT 24
Peak memory 202652 kb
Host smart-1a39969a-79c6-4eb2-b322-fef60030b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612131081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1612131081
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3091566852
Short name T106
Test name
Test status
Simulation time 34133307399 ps
CPU time 87.71 seconds
Started Apr 16 02:23:30 PM PDT 24
Finished Apr 16 02:24:58 PM PDT 24
Peak memory 202084 kb
Host smart-79521857-2efc-4b19-a29c-413561332c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091566852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3091566852
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.388039823
Short name T783
Test name
Test status
Simulation time 4029457533 ps
CPU time 5.55 seconds
Started Apr 16 02:23:27 PM PDT 24
Finished Apr 16 02:23:34 PM PDT 24
Peak memory 202064 kb
Host smart-9bfec378-c06c-4754-b293-cb4cd96a2cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388039823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.388039823
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1950645217
Short name T699
Test name
Test status
Simulation time 5903831661 ps
CPU time 6.97 seconds
Started Apr 16 02:23:18 PM PDT 24
Finished Apr 16 02:23:25 PM PDT 24
Peak memory 202004 kb
Host smart-cad853e7-9e89-4010-8452-fb78691bec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950645217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1950645217
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2596845207
Short name T237
Test name
Test status
Simulation time 332566137267 ps
CPU time 371.01 seconds
Started Apr 16 02:23:35 PM PDT 24
Finished Apr 16 02:29:46 PM PDT 24
Peak memory 202252 kb
Host smart-a4891da5-47a5-4236-b092-5aeaafac2877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596845207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2596845207
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.852562857
Short name T317
Test name
Test status
Simulation time 62466535053 ps
CPU time 122.83 seconds
Started Apr 16 02:23:29 PM PDT 24
Finished Apr 16 02:25:33 PM PDT 24
Peak memory 210588 kb
Host smart-70adb43f-297c-4801-9518-f82e000f29f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852562857 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.852562857
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3560601958
Short name T656
Test name
Test status
Simulation time 429055950 ps
CPU time 1.1 seconds
Started Apr 16 02:23:38 PM PDT 24
Finished Apr 16 02:23:40 PM PDT 24
Peak memory 202008 kb
Host smart-dddd2e6d-0fe6-4709-9598-86fdc5b4ce7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560601958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3560601958
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.926362593
Short name T162
Test name
Test status
Simulation time 351150200523 ps
CPU time 115.73 seconds
Started Apr 16 02:23:38 PM PDT 24
Finished Apr 16 02:25:34 PM PDT 24
Peak memory 202324 kb
Host smart-2dc029a9-7ac6-4b24-bc86-7770843cc9dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926362593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.926362593
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1272716689
Short name T708
Test name
Test status
Simulation time 161568548434 ps
CPU time 59.83 seconds
Started Apr 16 02:23:37 PM PDT 24
Finished Apr 16 02:24:38 PM PDT 24
Peak memory 202228 kb
Host smart-17a3721c-ab44-413a-a075-4abf2e364f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272716689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1272716689
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.409429009
Short name T552
Test name
Test status
Simulation time 329286481291 ps
CPU time 300.77 seconds
Started Apr 16 02:23:38 PM PDT 24
Finished Apr 16 02:28:39 PM PDT 24
Peak memory 202236 kb
Host smart-a6d4c54b-30b0-4ea6-9e8d-29387e5eb0f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=409429009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.409429009
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.96418943
Short name T160
Test name
Test status
Simulation time 494555751536 ps
CPU time 1121.71 seconds
Started Apr 16 02:23:34 PM PDT 24
Finished Apr 16 02:42:16 PM PDT 24
Peak memory 202284 kb
Host smart-0932f07a-8fa3-49a6-aca3-d2e50a82877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96418943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.96418943
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1679504887
Short name T597
Test name
Test status
Simulation time 162689654397 ps
CPU time 91.39 seconds
Started Apr 16 02:23:42 PM PDT 24
Finished Apr 16 02:25:14 PM PDT 24
Peak memory 202176 kb
Host smart-8e0eca62-d783-43a4-b181-214f6ee0f827
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679504887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1679504887
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3858937271
Short name T178
Test name
Test status
Simulation time 538510123525 ps
CPU time 1175.03 seconds
Started Apr 16 02:23:42 PM PDT 24
Finished Apr 16 02:43:17 PM PDT 24
Peak memory 202124 kb
Host smart-02870ba8-1bb1-448e-aa8a-710501ae6538
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858937271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3858937271
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2525929823
Short name T464
Test name
Test status
Simulation time 595438325858 ps
CPU time 335.38 seconds
Started Apr 16 02:23:41 PM PDT 24
Finished Apr 16 02:29:17 PM PDT 24
Peak memory 202124 kb
Host smart-a5e0cf16-c0f4-4aec-ab68-06014e9f1df0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525929823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2525929823
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.498837845
Short name T350
Test name
Test status
Simulation time 64170800513 ps
CPU time 295.36 seconds
Started Apr 16 02:23:43 PM PDT 24
Finished Apr 16 02:28:39 PM PDT 24
Peak memory 202448 kb
Host smart-4301c55f-1593-40e1-9ed2-8c2447e51c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498837845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.498837845
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2215851613
Short name T727
Test name
Test status
Simulation time 36054735561 ps
CPU time 83.96 seconds
Started Apr 16 02:23:38 PM PDT 24
Finished Apr 16 02:25:03 PM PDT 24
Peak memory 202048 kb
Host smart-889aece7-3eb9-4a28-afc0-372a23b61f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215851613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2215851613
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1724155819
Short name T484
Test name
Test status
Simulation time 3609530543 ps
CPU time 9.41 seconds
Started Apr 16 02:23:38 PM PDT 24
Finished Apr 16 02:23:48 PM PDT 24
Peak memory 202060 kb
Host smart-b4ef4f59-6b55-4692-b099-cfb495c1e1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724155819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1724155819
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.961398814
Short name T449
Test name
Test status
Simulation time 6015954475 ps
CPU time 14.62 seconds
Started Apr 16 02:23:34 PM PDT 24
Finished Apr 16 02:23:49 PM PDT 24
Peak memory 202308 kb
Host smart-1f6b0ff0-d2f5-4897-8f87-df46ca4f99bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961398814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.961398814
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.4250458428
Short name T127
Test name
Test status
Simulation time 168475122443 ps
CPU time 379.27 seconds
Started Apr 16 02:23:38 PM PDT 24
Finished Apr 16 02:29:58 PM PDT 24
Peak memory 201500 kb
Host smart-1d378bba-e6a2-4d99-918e-ed88a4ffacaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250458428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.4250458428
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2881260266
Short name T35
Test name
Test status
Simulation time 29635184628 ps
CPU time 54.42 seconds
Started Apr 16 02:23:38 PM PDT 24
Finished Apr 16 02:24:33 PM PDT 24
Peak memory 210476 kb
Host smart-e835083a-f24a-45a7-bb55-f9943fedb326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881260266 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2881260266
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2891821642
Short name T440
Test name
Test status
Simulation time 523507660 ps
CPU time 0.81 seconds
Started Apr 16 02:23:54 PM PDT 24
Finished Apr 16 02:23:55 PM PDT 24
Peak memory 201988 kb
Host smart-fc5856c7-f83e-49a8-8fb1-123c5e499eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891821642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2891821642
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2721836043
Short name T168
Test name
Test status
Simulation time 549982861695 ps
CPU time 993.66 seconds
Started Apr 16 02:23:44 PM PDT 24
Finished Apr 16 02:40:18 PM PDT 24
Peak memory 202264 kb
Host smart-105cda7b-24c5-466e-a0c0-a9ecf34c14e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721836043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2721836043
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2463621352
Short name T294
Test name
Test status
Simulation time 339542017907 ps
CPU time 216.53 seconds
Started Apr 16 02:23:48 PM PDT 24
Finished Apr 16 02:27:25 PM PDT 24
Peak memory 202228 kb
Host smart-871c79d6-5939-4414-95e0-b64e23aa2880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463621352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2463621352
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1576045152
Short name T404
Test name
Test status
Simulation time 498292248947 ps
CPU time 104.31 seconds
Started Apr 16 02:23:44 PM PDT 24
Finished Apr 16 02:25:29 PM PDT 24
Peak memory 202232 kb
Host smart-63b7607d-c3a2-40a8-bc0b-41d04b3eba36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576045152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1576045152
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3666993978
Short name T614
Test name
Test status
Simulation time 168696611972 ps
CPU time 98.44 seconds
Started Apr 16 02:23:42 PM PDT 24
Finished Apr 16 02:25:21 PM PDT 24
Peak memory 202228 kb
Host smart-a5cc0a37-4c8c-4d29-bd02-ed5ab3fd8ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666993978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3666993978
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3552995501
Short name T529
Test name
Test status
Simulation time 161388920218 ps
CPU time 85.04 seconds
Started Apr 16 02:23:42 PM PDT 24
Finished Apr 16 02:25:08 PM PDT 24
Peak memory 202216 kb
Host smart-afe80316-282b-4c41-abd4-7d51cc188a70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552995501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3552995501
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1450136108
Short name T344
Test name
Test status
Simulation time 170724720669 ps
CPU time 196.23 seconds
Started Apr 16 02:23:44 PM PDT 24
Finished Apr 16 02:27:00 PM PDT 24
Peak memory 202260 kb
Host smart-f19f2fed-331b-475d-9e0c-8cc7d10b8945
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450136108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1450136108
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.389342595
Short name T118
Test name
Test status
Simulation time 192611253349 ps
CPU time 74.55 seconds
Started Apr 16 02:23:43 PM PDT 24
Finished Apr 16 02:24:58 PM PDT 24
Peak memory 202200 kb
Host smart-7fd57bf7-441b-4593-80d5-e2aa555b38d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389342595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.389342595
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.4260283820
Short name T197
Test name
Test status
Simulation time 109243842225 ps
CPU time 329.96 seconds
Started Apr 16 02:23:49 PM PDT 24
Finished Apr 16 02:29:19 PM PDT 24
Peak memory 202596 kb
Host smart-6f19514f-f57d-4181-8c08-a5acb4ec9813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260283820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.4260283820
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1884715413
Short name T647
Test name
Test status
Simulation time 46229189532 ps
CPU time 45.8 seconds
Started Apr 16 02:23:47 PM PDT 24
Finished Apr 16 02:24:33 PM PDT 24
Peak memory 202092 kb
Host smart-c0a8d977-3bd1-4ef0-9cfc-8e220479cda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884715413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1884715413
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1354893856
Short name T527
Test name
Test status
Simulation time 3214672039 ps
CPU time 2.58 seconds
Started Apr 16 02:23:48 PM PDT 24
Finished Apr 16 02:23:51 PM PDT 24
Peak memory 202040 kb
Host smart-3ce77721-4573-46e9-ab6b-03c2f98213fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354893856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1354893856
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.394425142
Short name T103
Test name
Test status
Simulation time 5742140264 ps
CPU time 7.63 seconds
Started Apr 16 02:23:42 PM PDT 24
Finished Apr 16 02:23:51 PM PDT 24
Peak memory 202080 kb
Host smart-86332896-d19a-4ccb-b43d-7f41b6df6fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394425142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.394425142
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.228253514
Short name T549
Test name
Test status
Simulation time 298404297690 ps
CPU time 492.67 seconds
Started Apr 16 02:23:52 PM PDT 24
Finished Apr 16 02:32:05 PM PDT 24
Peak memory 202536 kb
Host smart-913b2c5c-2bc5-4d52-a580-73629ee29a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228253514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
228253514
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2711015320
Short name T34
Test name
Test status
Simulation time 612248345282 ps
CPU time 303.96 seconds
Started Apr 16 02:23:47 PM PDT 24
Finished Apr 16 02:28:51 PM PDT 24
Peak memory 218440 kb
Host smart-9b1f601b-67b4-4a11-a142-4942ca27c9f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711015320 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2711015320
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2849145593
Short name T424
Test name
Test status
Simulation time 306050831 ps
CPU time 0.93 seconds
Started Apr 16 02:24:02 PM PDT 24
Finished Apr 16 02:24:03 PM PDT 24
Peak memory 201924 kb
Host smart-08810a4a-d0eb-4185-aa6d-87ca0d631830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849145593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2849145593
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2226649398
Short name T1
Test name
Test status
Simulation time 166060930889 ps
CPU time 382.57 seconds
Started Apr 16 02:24:05 PM PDT 24
Finished Apr 16 02:30:28 PM PDT 24
Peak memory 202176 kb
Host smart-00b473de-d793-411a-a7ab-4a7472f481b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226649398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2226649398
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1009904165
Short name T601
Test name
Test status
Simulation time 319230756104 ps
CPU time 742.82 seconds
Started Apr 16 02:23:59 PM PDT 24
Finished Apr 16 02:36:22 PM PDT 24
Peak memory 202288 kb
Host smart-be3903b7-9420-4f0c-a75a-fe285af5eacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009904165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1009904165
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.994102034
Short name T737
Test name
Test status
Simulation time 166057347079 ps
CPU time 394.66 seconds
Started Apr 16 02:23:58 PM PDT 24
Finished Apr 16 02:30:33 PM PDT 24
Peak memory 202148 kb
Host smart-aa89b109-33e0-421d-a13f-2cf281744419
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=994102034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.994102034
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3391524820
Short name T545
Test name
Test status
Simulation time 334301407958 ps
CPU time 188.72 seconds
Started Apr 16 02:23:54 PM PDT 24
Finished Apr 16 02:27:03 PM PDT 24
Peak memory 202312 kb
Host smart-e4ca0d87-9cba-4a68-b8f9-cccbc592a4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391524820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3391524820
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3182358684
Short name T492
Test name
Test status
Simulation time 327257577613 ps
CPU time 378.82 seconds
Started Apr 16 02:23:54 PM PDT 24
Finished Apr 16 02:30:13 PM PDT 24
Peak memory 202196 kb
Host smart-35e81549-1335-451b-9b0b-5dc25f323e52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182358684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3182358684
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1959800207
Short name T739
Test name
Test status
Simulation time 206142726237 ps
CPU time 254.36 seconds
Started Apr 16 02:23:59 PM PDT 24
Finished Apr 16 02:28:14 PM PDT 24
Peak memory 202216 kb
Host smart-6aca9696-949f-42fa-82ed-33f5c28344ed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959800207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1959800207
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3899320885
Short name T442
Test name
Test status
Simulation time 74216204967 ps
CPU time 263.42 seconds
Started Apr 16 02:24:02 PM PDT 24
Finished Apr 16 02:28:26 PM PDT 24
Peak memory 202620 kb
Host smart-a953c5db-58e8-452b-bbc7-becfcd4e8675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899320885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3899320885
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4180144057
Short name T478
Test name
Test status
Simulation time 34183181284 ps
CPU time 75.87 seconds
Started Apr 16 02:24:02 PM PDT 24
Finished Apr 16 02:25:18 PM PDT 24
Peak memory 202060 kb
Host smart-6c2dfe03-d104-4491-b1ca-9062621875eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180144057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4180144057
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3544525458
Short name T617
Test name
Test status
Simulation time 5414476478 ps
CPU time 3.87 seconds
Started Apr 16 02:24:01 PM PDT 24
Finished Apr 16 02:24:06 PM PDT 24
Peak memory 201228 kb
Host smart-d84ba55d-5568-4e85-84c9-30e041399e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544525458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3544525458
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1067962170
Short name T760
Test name
Test status
Simulation time 5983751664 ps
CPU time 16.34 seconds
Started Apr 16 02:23:53 PM PDT 24
Finished Apr 16 02:24:10 PM PDT 24
Peak memory 202064 kb
Host smart-d494456b-426d-4376-9500-ba18893ff10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067962170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1067962170
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1240608939
Short name T700
Test name
Test status
Simulation time 447227517733 ps
CPU time 618.25 seconds
Started Apr 16 02:24:05 PM PDT 24
Finished Apr 16 02:34:24 PM PDT 24
Peak memory 202560 kb
Host smart-479c6561-d1a9-4137-ae80-81d6f29f796d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240608939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1240608939
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1945179112
Short name T299
Test name
Test status
Simulation time 155214814968 ps
CPU time 38.96 seconds
Started Apr 16 02:24:03 PM PDT 24
Finished Apr 16 02:24:42 PM PDT 24
Peak memory 202336 kb
Host smart-34cd4fa9-87b7-418c-9586-1f7bdf0f39f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945179112 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1945179112
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.289618399
Short name T510
Test name
Test status
Simulation time 479268570 ps
CPU time 1.82 seconds
Started Apr 16 02:20:53 PM PDT 24
Finished Apr 16 02:20:56 PM PDT 24
Peak memory 201984 kb
Host smart-687915b5-1b9f-47fa-b158-98a3fd5de28c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289618399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.289618399
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2608681853
Short name T255
Test name
Test status
Simulation time 367083987398 ps
CPU time 391.33 seconds
Started Apr 16 02:20:50 PM PDT 24
Finished Apr 16 02:27:22 PM PDT 24
Peak memory 202232 kb
Host smart-0b51ba0d-266c-47e6-ba86-74f86a9e8c1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608681853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2608681853
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2289663405
Short name T661
Test name
Test status
Simulation time 252464258177 ps
CPU time 290.43 seconds
Started Apr 16 02:20:51 PM PDT 24
Finished Apr 16 02:25:42 PM PDT 24
Peak memory 202220 kb
Host smart-325fa94c-f8ed-4946-8d21-7c221db76f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289663405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2289663405
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1363734423
Short name T313
Test name
Test status
Simulation time 171422346815 ps
CPU time 62.48 seconds
Started Apr 16 02:20:58 PM PDT 24
Finished Apr 16 02:22:01 PM PDT 24
Peak memory 202232 kb
Host smart-ecd45451-67a4-4c6f-bc5c-ec8d5338aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363734423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1363734423
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3844115361
Short name T423
Test name
Test status
Simulation time 323307838899 ps
CPU time 745.02 seconds
Started Apr 16 02:20:50 PM PDT 24
Finished Apr 16 02:33:15 PM PDT 24
Peak memory 202228 kb
Host smart-6e8f6db3-4f96-461f-982f-bdfbe03042ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844115361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3844115361
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2187587387
Short name T43
Test name
Test status
Simulation time 162789114478 ps
CPU time 95.95 seconds
Started Apr 16 02:20:50 PM PDT 24
Finished Apr 16 02:22:27 PM PDT 24
Peak memory 202332 kb
Host smart-5c6551f9-9067-47db-8cd4-80af2d7c58ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187587387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2187587387
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3314264819
Short name T540
Test name
Test status
Simulation time 162783068810 ps
CPU time 397.7 seconds
Started Apr 16 02:20:47 PM PDT 24
Finished Apr 16 02:27:25 PM PDT 24
Peak memory 202312 kb
Host smart-3174cc3e-d1bf-47ed-9fd3-3cee91dfd548
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314264819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3314264819
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.194181578
Short name T321
Test name
Test status
Simulation time 173771353834 ps
CPU time 189.88 seconds
Started Apr 16 02:20:53 PM PDT 24
Finished Apr 16 02:24:04 PM PDT 24
Peak memory 202256 kb
Host smart-452fb29e-e145-4d25-80df-ce35568ffca9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194181578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.194181578
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3790400025
Short name T685
Test name
Test status
Simulation time 395221581194 ps
CPU time 237.59 seconds
Started Apr 16 02:20:52 PM PDT 24
Finished Apr 16 02:24:50 PM PDT 24
Peak memory 202180 kb
Host smart-c27d54e5-6b28-4bbc-a985-f25e3c1a65df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790400025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3790400025
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3125190636
Short name T364
Test name
Test status
Simulation time 95469586539 ps
CPU time 439.72 seconds
Started Apr 16 02:20:54 PM PDT 24
Finished Apr 16 02:28:14 PM PDT 24
Peak memory 202576 kb
Host smart-fd4ea5ff-bd6d-440d-b48e-7b57e0180070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125190636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3125190636
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2013529145
Short name T381
Test name
Test status
Simulation time 30844626283 ps
CPU time 37.77 seconds
Started Apr 16 02:20:52 PM PDT 24
Finished Apr 16 02:21:30 PM PDT 24
Peak memory 202044 kb
Host smart-8f7bb942-fa0b-4eb9-8353-36160bd0dee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013529145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2013529145
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3468448097
Short name T537
Test name
Test status
Simulation time 5068169417 ps
CPU time 6.49 seconds
Started Apr 16 02:20:51 PM PDT 24
Finished Apr 16 02:20:58 PM PDT 24
Peak memory 202060 kb
Host smart-837daac9-81f1-48fc-873c-99866dd04e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468448097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3468448097
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.124919061
Short name T99
Test name
Test status
Simulation time 4302641845 ps
CPU time 9.59 seconds
Started Apr 16 02:20:50 PM PDT 24
Finished Apr 16 02:21:00 PM PDT 24
Peak memory 217788 kb
Host smart-844f4e4b-afe5-40a2-a3e5-d6f510acde8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124919061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.124919061
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3242003363
Short name T532
Test name
Test status
Simulation time 5879312598 ps
CPU time 13.73 seconds
Started Apr 16 02:20:50 PM PDT 24
Finished Apr 16 02:21:05 PM PDT 24
Peak memory 202044 kb
Host smart-3c812c26-a4f5-472b-836a-f13cb9c514b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242003363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3242003363
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2286623274
Short name T770
Test name
Test status
Simulation time 247362036081 ps
CPU time 743.22 seconds
Started Apr 16 02:20:49 PM PDT 24
Finished Apr 16 02:33:13 PM PDT 24
Peak memory 210836 kb
Host smart-d7918f89-c17d-4c58-b967-3d6842f14117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286623274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2286623274
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.4244585283
Short name T571
Test name
Test status
Simulation time 561190743 ps
CPU time 0.88 seconds
Started Apr 16 02:24:19 PM PDT 24
Finished Apr 16 02:24:21 PM PDT 24
Peak memory 201928 kb
Host smart-c03de3c4-87a5-4122-bf61-0dedad5870af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244585283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.4244585283
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3379611873
Short name T112
Test name
Test status
Simulation time 171594223436 ps
CPU time 86.28 seconds
Started Apr 16 02:24:11 PM PDT 24
Finished Apr 16 02:25:39 PM PDT 24
Peak memory 202260 kb
Host smart-2cdf114d-dc31-4fd1-88e2-03e3524eb6ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379611873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3379611873
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3513458020
Short name T523
Test name
Test status
Simulation time 171907116133 ps
CPU time 190.42 seconds
Started Apr 16 02:24:08 PM PDT 24
Finished Apr 16 02:27:19 PM PDT 24
Peak memory 202224 kb
Host smart-a22c2be6-35a6-40ad-8eca-6e9fe948ed4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513458020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3513458020
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2991440381
Short name T531
Test name
Test status
Simulation time 162924996805 ps
CPU time 386.4 seconds
Started Apr 16 02:24:11 PM PDT 24
Finished Apr 16 02:30:38 PM PDT 24
Peak memory 202316 kb
Host smart-1e5d371b-45a0-4152-879a-daee72f9a35b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991440381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2991440381
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1230509191
Short name T238
Test name
Test status
Simulation time 327922782678 ps
CPU time 718.9 seconds
Started Apr 16 02:24:03 PM PDT 24
Finished Apr 16 02:36:02 PM PDT 24
Peak memory 202276 kb
Host smart-4045120b-5f7d-410e-97ec-c4f91b8f6539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230509191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1230509191
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.628011294
Short name T414
Test name
Test status
Simulation time 333198912130 ps
CPU time 280.05 seconds
Started Apr 16 02:24:08 PM PDT 24
Finished Apr 16 02:28:48 PM PDT 24
Peak memory 202336 kb
Host smart-41ad00fa-e0f2-4819-b213-df4a69d7f007
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=628011294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.628011294
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3186758122
Short name T192
Test name
Test status
Simulation time 544698339178 ps
CPU time 180.43 seconds
Started Apr 16 02:24:08 PM PDT 24
Finished Apr 16 02:27:09 PM PDT 24
Peak memory 202260 kb
Host smart-bfc70211-a38d-48b1-bc6e-26a295897a1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186758122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3186758122
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1168467573
Short name T761
Test name
Test status
Simulation time 198545162026 ps
CPU time 105.07 seconds
Started Apr 16 02:24:13 PM PDT 24
Finished Apr 16 02:25:59 PM PDT 24
Peak memory 202180 kb
Host smart-7985ecba-ef8c-4632-a41d-baf0ed29d5e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168467573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1168467573
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3002271851
Short name T514
Test name
Test status
Simulation time 86552471279 ps
CPU time 338.68 seconds
Started Apr 16 02:24:18 PM PDT 24
Finished Apr 16 02:29:57 PM PDT 24
Peak memory 202648 kb
Host smart-b456dc13-d671-4a44-94ab-a4fa961404b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002271851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3002271851
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2116228435
Short name T457
Test name
Test status
Simulation time 24535389221 ps
CPU time 26.86 seconds
Started Apr 16 02:24:15 PM PDT 24
Finished Apr 16 02:24:43 PM PDT 24
Peak memory 202116 kb
Host smart-dbc4fa0b-4b0b-49a7-830c-f5739690cb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116228435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2116228435
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3489702432
Short name T543
Test name
Test status
Simulation time 5124592527 ps
CPU time 12.6 seconds
Started Apr 16 02:24:14 PM PDT 24
Finished Apr 16 02:24:28 PM PDT 24
Peak memory 202060 kb
Host smart-389d5beb-c6d8-457b-b296-3aeef5315e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489702432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3489702432
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3449460677
Short name T575
Test name
Test status
Simulation time 5666847586 ps
CPU time 7.3 seconds
Started Apr 16 02:24:03 PM PDT 24
Finished Apr 16 02:24:11 PM PDT 24
Peak memory 202032 kb
Host smart-d8113483-15ae-4ec4-8166-de2eacb6adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449460677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3449460677
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1296716338
Short name T230
Test name
Test status
Simulation time 380652022977 ps
CPU time 868.16 seconds
Started Apr 16 02:24:19 PM PDT 24
Finished Apr 16 02:38:48 PM PDT 24
Peak memory 202184 kb
Host smart-189ef558-6ce1-4127-9f43-7139ffd62805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296716338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1296716338
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2430285696
Short name T20
Test name
Test status
Simulation time 147151919592 ps
CPU time 21.69 seconds
Started Apr 16 02:24:19 PM PDT 24
Finished Apr 16 02:24:42 PM PDT 24
Peak memory 210904 kb
Host smart-66da5e84-557a-40bd-a278-e0fb25a3aaa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430285696 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2430285696
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3771673955
Short name T97
Test name
Test status
Simulation time 586012244 ps
CPU time 0.76 seconds
Started Apr 16 02:24:36 PM PDT 24
Finished Apr 16 02:24:37 PM PDT 24
Peak memory 201980 kb
Host smart-00224e10-d162-4de5-ae8c-9d0076a201d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771673955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3771673955
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1869821729
Short name T295
Test name
Test status
Simulation time 363022285293 ps
CPU time 878.97 seconds
Started Apr 16 02:24:27 PM PDT 24
Finished Apr 16 02:39:06 PM PDT 24
Peak memory 202232 kb
Host smart-a0d4d057-d1cc-47df-91b6-e9fd52847668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869821729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1869821729
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2051688937
Short name T297
Test name
Test status
Simulation time 490407959485 ps
CPU time 585.17 seconds
Started Apr 16 02:24:20 PM PDT 24
Finished Apr 16 02:34:06 PM PDT 24
Peak memory 202272 kb
Host smart-b52c9b6e-40f4-4c52-862d-f9805e4d24cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051688937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2051688937
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4160356788
Short name T486
Test name
Test status
Simulation time 333935913939 ps
CPU time 371.58 seconds
Started Apr 16 02:24:21 PM PDT 24
Finished Apr 16 02:30:33 PM PDT 24
Peak memory 202296 kb
Host smart-dd23df3d-f061-4752-8032-e1eca0e4e003
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160356788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4160356788
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.384485583
Short name T262
Test name
Test status
Simulation time 332249458869 ps
CPU time 209.92 seconds
Started Apr 16 02:24:20 PM PDT 24
Finished Apr 16 02:27:51 PM PDT 24
Peak memory 202280 kb
Host smart-56cea17e-7d29-4883-8914-0b57efc8605d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384485583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.384485583
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.415586940
Short name T794
Test name
Test status
Simulation time 487332347751 ps
CPU time 272.03 seconds
Started Apr 16 02:24:22 PM PDT 24
Finished Apr 16 02:28:55 PM PDT 24
Peak memory 202244 kb
Host smart-33d653c2-a63c-48cc-913e-60084ede9887
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=415586940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.415586940
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1216866340
Short name T489
Test name
Test status
Simulation time 408884302727 ps
CPU time 111.74 seconds
Started Apr 16 02:24:27 PM PDT 24
Finished Apr 16 02:26:19 PM PDT 24
Peak memory 202236 kb
Host smart-6cc3aad7-16bc-4210-a66a-878a7d8c7d52
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216866340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1216866340
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3047583670
Short name T66
Test name
Test status
Simulation time 69875930748 ps
CPU time 246.27 seconds
Started Apr 16 02:24:34 PM PDT 24
Finished Apr 16 02:28:41 PM PDT 24
Peak memory 202552 kb
Host smart-d00c897a-ac52-4694-aaee-5aee575aa299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047583670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3047583670
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.484448166
Short name T396
Test name
Test status
Simulation time 35814383362 ps
CPU time 40.09 seconds
Started Apr 16 02:24:33 PM PDT 24
Finished Apr 16 02:25:14 PM PDT 24
Peak memory 202072 kb
Host smart-677b2c92-e8df-430d-9b27-b73dfda79499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484448166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.484448166
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1733615427
Short name T370
Test name
Test status
Simulation time 4051249322 ps
CPU time 3.79 seconds
Started Apr 16 02:24:28 PM PDT 24
Finished Apr 16 02:24:32 PM PDT 24
Peak memory 202032 kb
Host smart-26a21504-2d2f-47af-b51d-5665486c608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733615427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1733615427
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2023873803
Short name T680
Test name
Test status
Simulation time 5649262931 ps
CPU time 8.57 seconds
Started Apr 16 02:24:21 PM PDT 24
Finished Apr 16 02:24:30 PM PDT 24
Peak memory 202076 kb
Host smart-6753772f-1b9c-4185-b222-e668db79a583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023873803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2023873803
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1645439044
Short name T85
Test name
Test status
Simulation time 332321745040 ps
CPU time 764.25 seconds
Started Apr 16 02:24:32 PM PDT 24
Finished Apr 16 02:37:17 PM PDT 24
Peak memory 202240 kb
Host smart-f0d28110-05ab-41c9-b7a5-429f2a694ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645439044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1645439044
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.999251956
Short name T758
Test name
Test status
Simulation time 480566931 ps
CPU time 1.2 seconds
Started Apr 16 02:24:42 PM PDT 24
Finished Apr 16 02:24:43 PM PDT 24
Peak memory 201984 kb
Host smart-abe99597-a4e3-42d2-88d1-38f0274de55f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999251956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.999251956
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1474123094
Short name T732
Test name
Test status
Simulation time 526887649685 ps
CPU time 1272.93 seconds
Started Apr 16 02:24:45 PM PDT 24
Finished Apr 16 02:45:59 PM PDT 24
Peak memory 202480 kb
Host smart-c0a0cac7-d269-44a6-8d3c-22f2dfe6155b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474123094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1474123094
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.117837887
Short name T204
Test name
Test status
Simulation time 358163315650 ps
CPU time 206.29 seconds
Started Apr 16 02:24:38 PM PDT 24
Finished Apr 16 02:28:05 PM PDT 24
Peak memory 202216 kb
Host smart-e5739d51-d5d1-4527-9837-acba6b14223e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117837887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.117837887
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.500839105
Short name T223
Test name
Test status
Simulation time 167695936489 ps
CPU time 110.54 seconds
Started Apr 16 02:24:37 PM PDT 24
Finished Apr 16 02:26:28 PM PDT 24
Peak memory 202228 kb
Host smart-8942f67a-fcba-4a35-8583-e79ba67a727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500839105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.500839105
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.764801523
Short name T513
Test name
Test status
Simulation time 482243825795 ps
CPU time 1170.1 seconds
Started Apr 16 02:24:38 PM PDT 24
Finished Apr 16 02:44:08 PM PDT 24
Peak memory 202244 kb
Host smart-ea2ef47c-ef5a-4f96-a35b-1ff9a0e90454
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=764801523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.764801523
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3862424257
Short name T277
Test name
Test status
Simulation time 483287817420 ps
CPU time 163.51 seconds
Started Apr 16 02:24:38 PM PDT 24
Finished Apr 16 02:27:22 PM PDT 24
Peak memory 202192 kb
Host smart-bfd95f47-0c21-4d8c-9989-4a6ddab9bb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862424257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3862424257
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1966262408
Short name T627
Test name
Test status
Simulation time 485411303540 ps
CPU time 378.37 seconds
Started Apr 16 02:24:39 PM PDT 24
Finished Apr 16 02:30:58 PM PDT 24
Peak memory 202440 kb
Host smart-bf0f30fa-ebf6-435f-ad8f-409fb4eba238
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966262408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1966262408
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2168838037
Short name T775
Test name
Test status
Simulation time 163169669926 ps
CPU time 102.31 seconds
Started Apr 16 02:24:39 PM PDT 24
Finished Apr 16 02:26:22 PM PDT 24
Peak memory 202292 kb
Host smart-efccebae-f655-48fe-a233-92d9d4aada2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168838037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2168838037
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3627211960
Short name T116
Test name
Test status
Simulation time 603753021439 ps
CPU time 722.95 seconds
Started Apr 16 02:24:37 PM PDT 24
Finished Apr 16 02:36:40 PM PDT 24
Peak memory 202240 kb
Host smart-9b7e9246-f579-41e6-9e52-6ddf43797987
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627211960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3627211960
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2633323222
Short name T101
Test name
Test status
Simulation time 25455532215 ps
CPU time 60.24 seconds
Started Apr 16 02:24:39 PM PDT 24
Finished Apr 16 02:25:40 PM PDT 24
Peak memory 202056 kb
Host smart-9267c0be-b195-4935-9766-0df0f88fa446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633323222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2633323222
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.331899025
Short name T157
Test name
Test status
Simulation time 4433154117 ps
CPU time 10.83 seconds
Started Apr 16 02:24:39 PM PDT 24
Finished Apr 16 02:24:51 PM PDT 24
Peak memory 202048 kb
Host smart-c309eca4-70fd-41f2-a1e6-c19bbb6a7a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331899025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.331899025
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1070204114
Short name T452
Test name
Test status
Simulation time 5954295391 ps
CPU time 4.32 seconds
Started Apr 16 02:24:32 PM PDT 24
Finished Apr 16 02:24:37 PM PDT 24
Peak memory 202064 kb
Host smart-99b059ef-05af-4db1-be7d-7769c5d994f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070204114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1070204114
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1205382006
Short name T264
Test name
Test status
Simulation time 185085492745 ps
CPU time 43.14 seconds
Started Apr 16 02:24:41 PM PDT 24
Finished Apr 16 02:25:25 PM PDT 24
Peak memory 202276 kb
Host smart-030ee996-0b39-4bec-bec2-40f94da650a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205382006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1205382006
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3735293217
Short name T538
Test name
Test status
Simulation time 562779808 ps
CPU time 0.78 seconds
Started Apr 16 02:24:52 PM PDT 24
Finished Apr 16 02:24:54 PM PDT 24
Peak memory 201988 kb
Host smart-cece6ad6-04cb-4e9c-bca5-6b1256d4be74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735293217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3735293217
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1638783645
Short name T332
Test name
Test status
Simulation time 165495502084 ps
CPU time 98.61 seconds
Started Apr 16 02:24:48 PM PDT 24
Finished Apr 16 02:26:27 PM PDT 24
Peak memory 202252 kb
Host smart-e8e2463c-8ca2-4cef-9b27-2ae975235458
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638783645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1638783645
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3752823575
Short name T468
Test name
Test status
Simulation time 321029900879 ps
CPU time 766.16 seconds
Started Apr 16 02:24:52 PM PDT 24
Finished Apr 16 02:37:39 PM PDT 24
Peak memory 202248 kb
Host smart-ed3e5dec-8871-451f-afe2-61fb842e011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752823575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3752823575
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2501099629
Short name T335
Test name
Test status
Simulation time 334700580642 ps
CPU time 702.99 seconds
Started Apr 16 02:24:49 PM PDT 24
Finished Apr 16 02:36:32 PM PDT 24
Peak memory 202252 kb
Host smart-ef0b79ca-aaee-4063-82cb-df639e96b155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501099629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2501099629
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.345717437
Short name T57
Test name
Test status
Simulation time 324049122690 ps
CPU time 784.37 seconds
Started Apr 16 02:24:47 PM PDT 24
Finished Apr 16 02:37:52 PM PDT 24
Peak memory 202284 kb
Host smart-d0d2627d-4192-476c-bc9d-228952e84ca2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=345717437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.345717437
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.4145838828
Short name T287
Test name
Test status
Simulation time 164199947327 ps
CPU time 337.9 seconds
Started Apr 16 02:24:42 PM PDT 24
Finished Apr 16 02:30:20 PM PDT 24
Peak memory 202320 kb
Host smart-cb9615f2-a82f-4419-a1d0-bc8dac731b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145838828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.4145838828
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.983784932
Short name T769
Test name
Test status
Simulation time 160850810611 ps
CPU time 92.1 seconds
Started Apr 16 02:24:43 PM PDT 24
Finished Apr 16 02:26:15 PM PDT 24
Peak memory 202144 kb
Host smart-32711f97-b72b-4fdf-bc04-4152f4fc3153
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=983784932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.983784932
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.4286045930
Short name T234
Test name
Test status
Simulation time 350259396319 ps
CPU time 195.22 seconds
Started Apr 16 02:24:48 PM PDT 24
Finished Apr 16 02:28:03 PM PDT 24
Peak memory 202316 kb
Host smart-cd06fa39-4a6a-4f10-ba9d-951e62f307e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286045930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.4286045930
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2720788572
Short name T453
Test name
Test status
Simulation time 206411419135 ps
CPU time 236.45 seconds
Started Apr 16 02:24:48 PM PDT 24
Finished Apr 16 02:28:45 PM PDT 24
Peak memory 202224 kb
Host smart-c5f43675-06cb-4eb8-b332-0a64ece08cf3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720788572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2720788572
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1157556532
Short name T354
Test name
Test status
Simulation time 100765631418 ps
CPU time 387.73 seconds
Started Apr 16 02:24:53 PM PDT 24
Finished Apr 16 02:31:22 PM PDT 24
Peak memory 202636 kb
Host smart-24d0c042-ea8c-41c2-bfa4-53e5935c9294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157556532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1157556532
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3587116951
Short name T665
Test name
Test status
Simulation time 38523560010 ps
CPU time 83.98 seconds
Started Apr 16 02:24:52 PM PDT 24
Finished Apr 16 02:26:16 PM PDT 24
Peak memory 202096 kb
Host smart-672a0250-d5cd-4fa9-bd56-1fd6b0504f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587116951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3587116951
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2242897977
Short name T802
Test name
Test status
Simulation time 3583192849 ps
CPU time 9.02 seconds
Started Apr 16 02:24:53 PM PDT 24
Finished Apr 16 02:25:02 PM PDT 24
Peak memory 201980 kb
Host smart-19b7946d-d13e-4251-8c0d-e09da4c1d782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242897977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2242897977
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3508162986
Short name T515
Test name
Test status
Simulation time 6127048870 ps
CPU time 15.24 seconds
Started Apr 16 02:24:43 PM PDT 24
Finished Apr 16 02:24:59 PM PDT 24
Peak memory 202016 kb
Host smart-91c71360-f81c-49ca-9389-9026903c7ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508162986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3508162986
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4166936835
Short name T53
Test name
Test status
Simulation time 249622989111 ps
CPU time 56.36 seconds
Started Apr 16 02:24:52 PM PDT 24
Finished Apr 16 02:25:49 PM PDT 24
Peak memory 210592 kb
Host smart-c3f852fd-2ca4-4e3d-a417-bdbc7b5d20c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166936835 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4166936835
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3281258168
Short name T509
Test name
Test status
Simulation time 406990135 ps
CPU time 1.58 seconds
Started Apr 16 02:25:08 PM PDT 24
Finished Apr 16 02:25:10 PM PDT 24
Peak memory 201952 kb
Host smart-132b25cc-17de-40df-90a0-4096a221dfe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281258168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3281258168
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2765707869
Short name T226
Test name
Test status
Simulation time 526135289457 ps
CPU time 646.03 seconds
Started Apr 16 02:25:01 PM PDT 24
Finished Apr 16 02:35:48 PM PDT 24
Peak memory 202276 kb
Host smart-62233345-5fdd-44c3-92f7-b7ef39f5ed94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765707869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2765707869
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3102087018
Short name T41
Test name
Test status
Simulation time 165799131081 ps
CPU time 207.33 seconds
Started Apr 16 02:25:06 PM PDT 24
Finished Apr 16 02:28:34 PM PDT 24
Peak memory 202260 kb
Host smart-bb937578-cda4-480f-b51a-195225d9d8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102087018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3102087018
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1084838475
Short name T756
Test name
Test status
Simulation time 492287748337 ps
CPU time 1043.04 seconds
Started Apr 16 02:24:58 PM PDT 24
Finished Apr 16 02:42:22 PM PDT 24
Peak memory 202200 kb
Host smart-f8ff0f32-53d3-4dc3-99c7-225acb3e2f05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084838475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1084838475
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1564228975
Short name T475
Test name
Test status
Simulation time 165814701766 ps
CPU time 362.03 seconds
Started Apr 16 02:24:58 PM PDT 24
Finished Apr 16 02:31:00 PM PDT 24
Peak memory 202320 kb
Host smart-e09c1d9e-1fb9-4cc4-b426-a2ea58f1c511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564228975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1564228975
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1977896239
Short name T398
Test name
Test status
Simulation time 327749062579 ps
CPU time 767.5 seconds
Started Apr 16 02:24:58 PM PDT 24
Finished Apr 16 02:37:46 PM PDT 24
Peak memory 202260 kb
Host smart-b4f1ec4f-4a11-409f-a0c4-b0b8b97f1848
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977896239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1977896239
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1385415828
Short name T338
Test name
Test status
Simulation time 179306829357 ps
CPU time 417.34 seconds
Started Apr 16 02:25:03 PM PDT 24
Finished Apr 16 02:32:01 PM PDT 24
Peak memory 202220 kb
Host smart-9e95f717-0291-41f7-8576-4f938f378727
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385415828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1385415828
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1532171797
Short name T418
Test name
Test status
Simulation time 611290780446 ps
CPU time 673.21 seconds
Started Apr 16 02:25:03 PM PDT 24
Finished Apr 16 02:36:17 PM PDT 24
Peak memory 202296 kb
Host smart-23229ba7-1209-41c4-9f1c-965feca8c001
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532171797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1532171797
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2899534629
Short name T356
Test name
Test status
Simulation time 113243161308 ps
CPU time 423.29 seconds
Started Apr 16 02:25:08 PM PDT 24
Finished Apr 16 02:32:12 PM PDT 24
Peak memory 202636 kb
Host smart-451862ab-45a5-4feb-9be5-b65dd3de0550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899534629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2899534629
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.913851650
Short name T626
Test name
Test status
Simulation time 43454194536 ps
CPU time 104.07 seconds
Started Apr 16 02:25:07 PM PDT 24
Finished Apr 16 02:26:52 PM PDT 24
Peak memory 201972 kb
Host smart-983f0046-9e7b-4562-9e60-629eb4c94d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913851650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.913851650
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3528124487
Short name T577
Test name
Test status
Simulation time 5538493356 ps
CPU time 3.84 seconds
Started Apr 16 02:25:09 PM PDT 24
Finished Apr 16 02:25:13 PM PDT 24
Peak memory 202064 kb
Host smart-94f3be37-e926-44db-9c17-e46dd9c9d211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528124487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3528124487
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.999655259
Short name T587
Test name
Test status
Simulation time 5848524330 ps
CPU time 3.99 seconds
Started Apr 16 02:24:58 PM PDT 24
Finished Apr 16 02:25:03 PM PDT 24
Peak memory 202068 kb
Host smart-520bc9ec-3eb2-48cc-88ed-dafc45752e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999655259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.999655259
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.353758626
Short name T105
Test name
Test status
Simulation time 11228796782 ps
CPU time 7.4 seconds
Started Apr 16 02:25:08 PM PDT 24
Finished Apr 16 02:25:16 PM PDT 24
Peak memory 202040 kb
Host smart-823241e8-edb3-4bdf-a6b1-40301d213e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353758626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
353758626
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4163259219
Short name T175
Test name
Test status
Simulation time 98650955204 ps
CPU time 228.86 seconds
Started Apr 16 02:25:08 PM PDT 24
Finished Apr 16 02:28:58 PM PDT 24
Peak memory 210952 kb
Host smart-f4dcbfb4-e77d-46f6-9b39-97d2df7b7593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163259219 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4163259219
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1339327021
Short name T466
Test name
Test status
Simulation time 459049625 ps
CPU time 1.65 seconds
Started Apr 16 02:25:17 PM PDT 24
Finished Apr 16 02:25:20 PM PDT 24
Peak memory 201956 kb
Host smart-692f27f9-e698-4cf8-b261-425426392604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339327021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1339327021
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1010029832
Short name T696
Test name
Test status
Simulation time 182469757844 ps
CPU time 214.93 seconds
Started Apr 16 02:25:16 PM PDT 24
Finished Apr 16 02:28:52 PM PDT 24
Peak memory 202256 kb
Host smart-ea0336a4-aa2b-4772-a29e-941e828a46aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010029832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1010029832
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.4292209430
Short name T490
Test name
Test status
Simulation time 163428752012 ps
CPU time 64.1 seconds
Started Apr 16 02:25:14 PM PDT 24
Finished Apr 16 02:26:18 PM PDT 24
Peak memory 202272 kb
Host smart-9b9a7d37-0f6c-4338-8426-bb9ef8ed5f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292209430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.4292209430
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1028748714
Short name T611
Test name
Test status
Simulation time 165330765332 ps
CPU time 204.72 seconds
Started Apr 16 02:25:13 PM PDT 24
Finished Apr 16 02:28:38 PM PDT 24
Peak memory 202460 kb
Host smart-1a28484d-c950-416d-9ba7-0341ef1c1042
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028748714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1028748714
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3168335911
Short name T124
Test name
Test status
Simulation time 155992696166 ps
CPU time 356.59 seconds
Started Apr 16 02:25:13 PM PDT 24
Finished Apr 16 02:31:10 PM PDT 24
Peak memory 202216 kb
Host smart-27131b0a-7cff-4fa8-8a65-723f7be26dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168335911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3168335911
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3841623138
Short name T541
Test name
Test status
Simulation time 331643400023 ps
CPU time 392.13 seconds
Started Apr 16 02:25:14 PM PDT 24
Finished Apr 16 02:31:46 PM PDT 24
Peak memory 202248 kb
Host smart-0c90b92f-addf-4fc9-904e-8d1a966ccf4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841623138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3841623138
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.765212954
Short name T372
Test name
Test status
Simulation time 604539597105 ps
CPU time 1363.52 seconds
Started Apr 16 02:25:16 PM PDT 24
Finished Apr 16 02:48:00 PM PDT 24
Peak memory 202204 kb
Host smart-6008caa0-144b-4ffa-bfec-2abf8d1ffb05
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765212954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.765212954
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.619934396
Short name T355
Test name
Test status
Simulation time 82252551077 ps
CPU time 314.1 seconds
Started Apr 16 02:25:16 PM PDT 24
Finished Apr 16 02:30:31 PM PDT 24
Peak memory 202596 kb
Host smart-21c3e525-d715-4a36-bbdd-9bc2a2c0eaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619934396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.619934396
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1553423589
Short name T752
Test name
Test status
Simulation time 33274640141 ps
CPU time 74.27 seconds
Started Apr 16 02:25:18 PM PDT 24
Finished Apr 16 02:26:33 PM PDT 24
Peak memory 201992 kb
Host smart-b2cba24f-61ca-4867-995e-704634abd3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553423589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1553423589
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2863028168
Short name T416
Test name
Test status
Simulation time 5039043765 ps
CPU time 3.21 seconds
Started Apr 16 02:25:16 PM PDT 24
Finished Apr 16 02:25:20 PM PDT 24
Peak memory 202096 kb
Host smart-75068be5-a181-4eb8-bea1-1b97ad78299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863028168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2863028168
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3243740199
Short name T417
Test name
Test status
Simulation time 6073454044 ps
CPU time 4.21 seconds
Started Apr 16 02:25:13 PM PDT 24
Finished Apr 16 02:25:18 PM PDT 24
Peak memory 202040 kb
Host smart-065f3f59-ff1e-4992-86fe-c24a93a532de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243740199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3243740199
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1817027035
Short name T170
Test name
Test status
Simulation time 367876295293 ps
CPU time 783.3 seconds
Started Apr 16 02:25:18 PM PDT 24
Finished Apr 16 02:38:22 PM PDT 24
Peak memory 202576 kb
Host smart-503dab47-4557-4dee-8de8-7bd45029409b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817027035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1817027035
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2961762884
Short name T339
Test name
Test status
Simulation time 20819271629 ps
CPU time 49.96 seconds
Started Apr 16 02:25:21 PM PDT 24
Finished Apr 16 02:26:11 PM PDT 24
Peak memory 210868 kb
Host smart-9db4dcd9-f055-43c3-aed6-b54edba04279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961762884 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2961762884
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.357242475
Short name T485
Test name
Test status
Simulation time 503286345 ps
CPU time 1.05 seconds
Started Apr 16 02:25:35 PM PDT 24
Finished Apr 16 02:25:36 PM PDT 24
Peak memory 201960 kb
Host smart-320117b2-03be-4711-8a38-eb376ba68afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357242475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.357242475
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1082900085
Short name T184
Test name
Test status
Simulation time 511070589294 ps
CPU time 74.25 seconds
Started Apr 16 02:25:34 PM PDT 24
Finished Apr 16 02:26:49 PM PDT 24
Peak memory 202268 kb
Host smart-e8226143-ecef-4734-a6e0-afd01e5fcf3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082900085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1082900085
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1610640029
Short name T491
Test name
Test status
Simulation time 192241432100 ps
CPU time 224.91 seconds
Started Apr 16 02:25:34 PM PDT 24
Finished Apr 16 02:29:19 PM PDT 24
Peak memory 202204 kb
Host smart-7ee0d7a7-f892-4fc9-a41d-4d5a64b23c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610640029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1610640029
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3116128839
Short name T535
Test name
Test status
Simulation time 163018227377 ps
CPU time 180.74 seconds
Started Apr 16 02:25:27 PM PDT 24
Finished Apr 16 02:28:28 PM PDT 24
Peak memory 202352 kb
Host smart-f80d70cf-1f50-430f-b529-215cf9cb31fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116128839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3116128839
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1465896720
Short name T721
Test name
Test status
Simulation time 329231201545 ps
CPU time 369.89 seconds
Started Apr 16 02:25:27 PM PDT 24
Finished Apr 16 02:31:38 PM PDT 24
Peak memory 202224 kb
Host smart-9c046133-fd18-4b2d-ab20-ba3ec844066c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465896720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1465896720
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3804289250
Short name T551
Test name
Test status
Simulation time 167277737971 ps
CPU time 121.75 seconds
Started Apr 16 02:25:23 PM PDT 24
Finished Apr 16 02:27:25 PM PDT 24
Peak memory 202320 kb
Host smart-e4b1a5c2-94f7-4453-ae4f-495cff6da682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804289250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3804289250
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2325886872
Short name T504
Test name
Test status
Simulation time 325968092235 ps
CPU time 397.62 seconds
Started Apr 16 02:25:22 PM PDT 24
Finished Apr 16 02:32:00 PM PDT 24
Peak memory 202316 kb
Host smart-310e142c-0fa8-418b-9cd9-c28be251a767
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325886872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2325886872
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2758253113
Short name T750
Test name
Test status
Simulation time 539142025539 ps
CPU time 504.21 seconds
Started Apr 16 02:25:31 PM PDT 24
Finished Apr 16 02:33:56 PM PDT 24
Peak memory 202232 kb
Host smart-12971c35-aec3-44e1-b972-a4b4ca0ce6b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758253113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2758253113
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.969202408
Short name T766
Test name
Test status
Simulation time 590767007590 ps
CPU time 699.67 seconds
Started Apr 16 02:25:31 PM PDT 24
Finished Apr 16 02:37:11 PM PDT 24
Peak memory 202216 kb
Host smart-88b1f36e-1254-434d-a377-43707debadeb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969202408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.969202408
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3300550878
Short name T431
Test name
Test status
Simulation time 37638154089 ps
CPU time 38.95 seconds
Started Apr 16 02:25:31 PM PDT 24
Finished Apr 16 02:26:11 PM PDT 24
Peak memory 201992 kb
Host smart-9dcdd3e3-a0b2-4987-a64b-3aad05bc5ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300550878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3300550878
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3215580155
Short name T559
Test name
Test status
Simulation time 3318306470 ps
CPU time 8.94 seconds
Started Apr 16 02:25:33 PM PDT 24
Finished Apr 16 02:25:43 PM PDT 24
Peak memory 202032 kb
Host smart-35bf182f-1db7-4816-a280-b8bbd2d49494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215580155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3215580155
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1545003829
Short name T580
Test name
Test status
Simulation time 5892765114 ps
CPU time 8.15 seconds
Started Apr 16 02:25:23 PM PDT 24
Finished Apr 16 02:25:32 PM PDT 24
Peak memory 202064 kb
Host smart-03b3a5ec-eece-4caf-b480-b3fb65deddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545003829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1545003829
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.608264201
Short name T646
Test name
Test status
Simulation time 18060093585 ps
CPU time 44.79 seconds
Started Apr 16 02:25:33 PM PDT 24
Finished Apr 16 02:26:18 PM PDT 24
Peak memory 202284 kb
Host smart-2e5e47fd-c5ef-4511-aca3-3be3c9318d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608264201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
608264201
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.197958140
Short name T246
Test name
Test status
Simulation time 51743185252 ps
CPU time 144.03 seconds
Started Apr 16 02:25:32 PM PDT 24
Finished Apr 16 02:27:56 PM PDT 24
Peak memory 210880 kb
Host smart-4d733ccc-ca61-4de6-9cf8-95b3d2ba4554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197958140 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.197958140
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.543738663
Short name T473
Test name
Test status
Simulation time 320526465 ps
CPU time 1.42 seconds
Started Apr 16 02:25:42 PM PDT 24
Finished Apr 16 02:25:44 PM PDT 24
Peak memory 201912 kb
Host smart-735e3862-8747-48c8-9b96-2a46b2cb3e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543738663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.543738663
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3840888751
Short name T26
Test name
Test status
Simulation time 162499295120 ps
CPU time 356.14 seconds
Started Apr 16 02:25:38 PM PDT 24
Finished Apr 16 02:31:34 PM PDT 24
Peak memory 202308 kb
Host smart-8a3bdf09-87de-4359-879a-4ac6430aec85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840888751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3840888751
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3433529665
Short name T530
Test name
Test status
Simulation time 165787372726 ps
CPU time 412.17 seconds
Started Apr 16 02:25:36 PM PDT 24
Finished Apr 16 02:32:29 PM PDT 24
Peak memory 202180 kb
Host smart-425cb2c0-881d-4672-ab06-789f277efd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433529665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3433529665
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2273629949
Short name T2
Test name
Test status
Simulation time 328636055096 ps
CPU time 398.15 seconds
Started Apr 16 02:25:38 PM PDT 24
Finished Apr 16 02:32:16 PM PDT 24
Peak memory 202280 kb
Host smart-0b4ec174-bfd5-491f-b3ce-8bd88cfb7f7d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273629949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2273629949
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2503690999
Short name T259
Test name
Test status
Simulation time 172118248468 ps
CPU time 108.97 seconds
Started Apr 16 02:25:37 PM PDT 24
Finished Apr 16 02:27:27 PM PDT 24
Peak memory 202236 kb
Host smart-a81e3121-2e6c-4125-a749-65705496471f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503690999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2503690999
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3775298019
Short name T787
Test name
Test status
Simulation time 497341804252 ps
CPU time 1205.83 seconds
Started Apr 16 02:25:37 PM PDT 24
Finished Apr 16 02:45:43 PM PDT 24
Peak memory 202200 kb
Host smart-2065f68a-b221-4b7e-9bf6-6a6c03177864
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775298019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3775298019
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2294209205
Short name T402
Test name
Test status
Simulation time 208346704416 ps
CPU time 82.59 seconds
Started Apr 16 02:25:37 PM PDT 24
Finished Apr 16 02:27:00 PM PDT 24
Peak memory 202244 kb
Host smart-5bdff0dd-731d-4447-b7f5-b80ccfbe41cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294209205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2294209205
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2239089578
Short name T361
Test name
Test status
Simulation time 151723449988 ps
CPU time 494.15 seconds
Started Apr 16 02:25:41 PM PDT 24
Finished Apr 16 02:33:56 PM PDT 24
Peak memory 202592 kb
Host smart-36c0c45a-d5e7-4630-9a46-4032eadec4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239089578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2239089578
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.711827073
Short name T747
Test name
Test status
Simulation time 27697397505 ps
CPU time 60.75 seconds
Started Apr 16 02:25:41 PM PDT 24
Finished Apr 16 02:26:43 PM PDT 24
Peak memory 202008 kb
Host smart-9eec7542-08c1-44f3-b511-8271084baf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711827073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.711827073
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3295186642
Short name T746
Test name
Test status
Simulation time 5212241661 ps
CPU time 6.96 seconds
Started Apr 16 02:25:42 PM PDT 24
Finished Apr 16 02:25:50 PM PDT 24
Peak memory 202016 kb
Host smart-e9a8e49d-f23f-4df4-9aa6-eddb277ff008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295186642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3295186642
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.962468289
Short name T10
Test name
Test status
Simulation time 5815890897 ps
CPU time 2.65 seconds
Started Apr 16 02:25:32 PM PDT 24
Finished Apr 16 02:25:35 PM PDT 24
Peak memory 202128 kb
Host smart-8ede7f09-58f5-40b3-add3-406fab8a5ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962468289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.962468289
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2188541270
Short name T508
Test name
Test status
Simulation time 396117408219 ps
CPU time 438.54 seconds
Started Apr 16 02:25:43 PM PDT 24
Finished Apr 16 02:33:02 PM PDT 24
Peak memory 202276 kb
Host smart-cda2e55d-4765-4eb0-94d8-a848092d8254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188541270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2188541270
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2592656909
Short name T583
Test name
Test status
Simulation time 314014330 ps
CPU time 1.28 seconds
Started Apr 16 02:25:52 PM PDT 24
Finished Apr 16 02:25:54 PM PDT 24
Peak memory 201956 kb
Host smart-d12d6218-eaab-4e3e-b4cd-78fd92132e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592656909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2592656909
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2400870944
Short name T115
Test name
Test status
Simulation time 163287775089 ps
CPU time 9.73 seconds
Started Apr 16 02:25:46 PM PDT 24
Finished Apr 16 02:25:57 PM PDT 24
Peak memory 202264 kb
Host smart-b634f241-ed02-4fa6-8b7d-7e4e472d7f16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400870944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2400870944
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1892983146
Short name T779
Test name
Test status
Simulation time 185385981808 ps
CPU time 62.94 seconds
Started Apr 16 02:25:46 PM PDT 24
Finished Apr 16 02:26:49 PM PDT 24
Peak memory 202268 kb
Host smart-e3640074-dfad-40a4-a18b-489da46918bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892983146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1892983146
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1363294887
Short name T582
Test name
Test status
Simulation time 163417764960 ps
CPU time 102.29 seconds
Started Apr 16 02:25:47 PM PDT 24
Finished Apr 16 02:27:29 PM PDT 24
Peak memory 202332 kb
Host smart-5fcdd0fd-c8cb-491b-ad68-e903616f54e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363294887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1363294887
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2263056824
Short name T734
Test name
Test status
Simulation time 164374248754 ps
CPU time 199.35 seconds
Started Apr 16 02:25:46 PM PDT 24
Finished Apr 16 02:29:06 PM PDT 24
Peak memory 202276 kb
Host smart-4d9f24e3-9dfd-44b0-a63f-24a93f7c75fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263056824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2263056824
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3209168384
Short name T135
Test name
Test status
Simulation time 166409983009 ps
CPU time 90.84 seconds
Started Apr 16 02:25:41 PM PDT 24
Finished Apr 16 02:27:12 PM PDT 24
Peak memory 202312 kb
Host smart-8d4a72ad-fc11-455d-a926-b102eaac787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209168384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3209168384
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1513212449
Short name T673
Test name
Test status
Simulation time 168148893598 ps
CPU time 97.74 seconds
Started Apr 16 02:25:46 PM PDT 24
Finished Apr 16 02:27:24 PM PDT 24
Peak memory 202268 kb
Host smart-b9e844f8-e06d-47b3-a544-b8472a4b6b05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513212449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1513212449
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1819384281
Short name T764
Test name
Test status
Simulation time 178012429230 ps
CPU time 426.85 seconds
Started Apr 16 02:25:52 PM PDT 24
Finished Apr 16 02:33:00 PM PDT 24
Peak memory 202344 kb
Host smart-615668ce-7118-4a1d-bd30-c2b90176126b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819384281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1819384281
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1300215556
Short name T639
Test name
Test status
Simulation time 399274813824 ps
CPU time 885.55 seconds
Started Apr 16 02:25:45 PM PDT 24
Finished Apr 16 02:40:31 PM PDT 24
Peak memory 202252 kb
Host smart-2a3e1816-7980-4599-93ef-8d032f1e3e66
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300215556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1300215556
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.335407988
Short name T681
Test name
Test status
Simulation time 32452658645 ps
CPU time 75.58 seconds
Started Apr 16 02:25:52 PM PDT 24
Finished Apr 16 02:27:08 PM PDT 24
Peak memory 202056 kb
Host smart-a170004c-eb07-4eb5-860c-afe68ad04155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335407988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.335407988
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3383427630
Short name T657
Test name
Test status
Simulation time 4900057442 ps
CPU time 6.93 seconds
Started Apr 16 02:25:49 PM PDT 24
Finished Apr 16 02:25:57 PM PDT 24
Peak memory 202072 kb
Host smart-1c5ec5ab-f9c1-42d4-af36-39a8a2ad255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383427630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3383427630
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.280687856
Short name T383
Test name
Test status
Simulation time 5746113506 ps
CPU time 3.82 seconds
Started Apr 16 02:25:44 PM PDT 24
Finished Apr 16 02:25:48 PM PDT 24
Peak memory 202080 kb
Host smart-752a6ef6-6210-474b-a5a0-fe60c51b786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280687856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.280687856
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1317988674
Short name T564
Test name
Test status
Simulation time 623419051023 ps
CPU time 750.97 seconds
Started Apr 16 02:25:52 PM PDT 24
Finished Apr 16 02:38:24 PM PDT 24
Peak memory 210840 kb
Host smart-8256dfd2-71fb-4ae5-b6cc-3b7da23ef286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317988674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1317988674
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1057442370
Short name T24
Test name
Test status
Simulation time 34467999336 ps
CPU time 66.79 seconds
Started Apr 16 02:25:52 PM PDT 24
Finished Apr 16 02:26:59 PM PDT 24
Peak memory 210612 kb
Host smart-af52aac1-433b-4f1b-8f6a-44de8353b3bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057442370 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1057442370
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.446152674
Short name T668
Test name
Test status
Simulation time 370837137 ps
CPU time 1.47 seconds
Started Apr 16 02:26:07 PM PDT 24
Finished Apr 16 02:26:09 PM PDT 24
Peak memory 201944 kb
Host smart-ecbeff2e-786e-4df6-b859-55d67ace5998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446152674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.446152674
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1124207540
Short name T648
Test name
Test status
Simulation time 166972560702 ps
CPU time 204.23 seconds
Started Apr 16 02:26:01 PM PDT 24
Finished Apr 16 02:29:26 PM PDT 24
Peak memory 202248 kb
Host smart-5b3f912b-2627-4663-9df4-444432bb8999
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124207540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1124207540
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3762115432
Short name T723
Test name
Test status
Simulation time 324194388925 ps
CPU time 758.84 seconds
Started Apr 16 02:25:59 PM PDT 24
Finished Apr 16 02:38:39 PM PDT 24
Peak memory 202276 kb
Host smart-2f875f0a-ebf5-4f3f-9074-aae4e446982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762115432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3762115432
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2291526405
Short name T518
Test name
Test status
Simulation time 332944225486 ps
CPU time 722.59 seconds
Started Apr 16 02:25:57 PM PDT 24
Finished Apr 16 02:38:00 PM PDT 24
Peak memory 202296 kb
Host smart-f93a05e4-0aa3-4ab8-8e2e-03b2520ea2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291526405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2291526405
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3690461012
Short name T403
Test name
Test status
Simulation time 164612691561 ps
CPU time 409.07 seconds
Started Apr 16 02:25:58 PM PDT 24
Finished Apr 16 02:32:48 PM PDT 24
Peak memory 202276 kb
Host smart-b9fb3940-0453-40e4-b216-cd144018aa3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690461012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3690461012
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3490267008
Short name T49
Test name
Test status
Simulation time 491209158078 ps
CPU time 283.8 seconds
Started Apr 16 02:25:51 PM PDT 24
Finished Apr 16 02:30:35 PM PDT 24
Peak memory 202300 kb
Host smart-62d2de0b-410b-4c0c-9257-9355876e6e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490267008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3490267008
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2843714639
Short name T100
Test name
Test status
Simulation time 327489091401 ps
CPU time 374.75 seconds
Started Apr 16 02:25:57 PM PDT 24
Finished Apr 16 02:32:12 PM PDT 24
Peak memory 202160 kb
Host smart-32811ba2-8efc-4b17-9d65-5b2844246952
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843714639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2843714639
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1048231456
Short name T343
Test name
Test status
Simulation time 518145357379 ps
CPU time 1323.99 seconds
Started Apr 16 02:26:01 PM PDT 24
Finished Apr 16 02:48:06 PM PDT 24
Peak memory 202312 kb
Host smart-b19fbec1-fb0c-48d0-8b43-b737592ed591
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048231456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1048231456
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2853579645
Short name T771
Test name
Test status
Simulation time 193797413186 ps
CPU time 383.84 seconds
Started Apr 16 02:26:01 PM PDT 24
Finished Apr 16 02:32:26 PM PDT 24
Peak memory 202212 kb
Host smart-ff8790ce-7734-4124-94fc-16aa24c88dbd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853579645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2853579645
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1126978040
Short name T640
Test name
Test status
Simulation time 128573289735 ps
CPU time 675.48 seconds
Started Apr 16 02:26:06 PM PDT 24
Finished Apr 16 02:37:22 PM PDT 24
Peak memory 202576 kb
Host smart-62bfa750-38b8-4c7f-917c-9e74ac79b765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126978040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1126978040
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2200130635
Short name T497
Test name
Test status
Simulation time 27461768893 ps
CPU time 64.49 seconds
Started Apr 16 02:26:05 PM PDT 24
Finished Apr 16 02:27:10 PM PDT 24
Peak memory 202056 kb
Host smart-f7ab7ff9-0940-4efd-93c7-385e01555a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200130635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2200130635
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3685677329
Short name T650
Test name
Test status
Simulation time 4716265342 ps
CPU time 12.09 seconds
Started Apr 16 02:26:07 PM PDT 24
Finished Apr 16 02:26:19 PM PDT 24
Peak memory 202080 kb
Host smart-27d6c629-24cf-42bc-9a97-48679ff9c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685677329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3685677329
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1500535457
Short name T40
Test name
Test status
Simulation time 5861721379 ps
CPU time 4.17 seconds
Started Apr 16 02:25:54 PM PDT 24
Finished Apr 16 02:25:58 PM PDT 24
Peak memory 202064 kb
Host smart-fed1fc50-ecbe-4b6b-84b5-311394f6b575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500535457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1500535457
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1458793307
Short name T47
Test name
Test status
Simulation time 330993189995 ps
CPU time 104.02 seconds
Started Apr 16 02:26:06 PM PDT 24
Finished Apr 16 02:27:51 PM PDT 24
Peak memory 202224 kb
Host smart-efaa470d-2a99-4676-9868-442d5da50df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458793307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1458793307
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2010484469
Short name T790
Test name
Test status
Simulation time 299288355 ps
CPU time 1.27 seconds
Started Apr 16 02:20:59 PM PDT 24
Finished Apr 16 02:21:01 PM PDT 24
Peak memory 201964 kb
Host smart-69b18aea-ca2c-45f4-9889-2ad27bdaea05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010484469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2010484469
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3593504012
Short name T742
Test name
Test status
Simulation time 338321274042 ps
CPU time 156.25 seconds
Started Apr 16 02:20:55 PM PDT 24
Finished Apr 16 02:23:32 PM PDT 24
Peak memory 202272 kb
Host smart-417b5949-24f0-4d83-8fba-e5f030eb1c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593504012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3593504012
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2399604445
Short name T590
Test name
Test status
Simulation time 163269795039 ps
CPU time 400.63 seconds
Started Apr 16 02:20:54 PM PDT 24
Finished Apr 16 02:27:35 PM PDT 24
Peak memory 202360 kb
Host smart-6051e66b-8e04-4a67-b93a-ee208ed827ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399604445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2399604445
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3912389046
Short name T683
Test name
Test status
Simulation time 163579564539 ps
CPU time 68.26 seconds
Started Apr 16 02:20:57 PM PDT 24
Finished Apr 16 02:22:06 PM PDT 24
Peak memory 202316 kb
Host smart-11eb05ec-eb6c-423a-87cb-ed5a890a6ea2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912389046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3912389046
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.595018950
Short name T519
Test name
Test status
Simulation time 169020632335 ps
CPU time 389.78 seconds
Started Apr 16 02:20:53 PM PDT 24
Finished Apr 16 02:27:23 PM PDT 24
Peak memory 202304 kb
Host smart-dae046e2-8d6f-45e3-b790-7f495620135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595018950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.595018950
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.473959492
Short name T493
Test name
Test status
Simulation time 164725603825 ps
CPU time 100.6 seconds
Started Apr 16 02:20:56 PM PDT 24
Finished Apr 16 02:22:37 PM PDT 24
Peak memory 202236 kb
Host smart-1942b736-a44b-4f7e-867c-ecafc95d3c82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=473959492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.473959492
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2889781880
Short name T520
Test name
Test status
Simulation time 226715702285 ps
CPU time 494.89 seconds
Started Apr 16 02:20:55 PM PDT 24
Finished Apr 16 02:29:10 PM PDT 24
Peak memory 202332 kb
Host smart-e269db66-152c-41a9-b74b-5e2e12eeefaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889781880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2889781880
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3355628997
Short name T797
Test name
Test status
Simulation time 589303241368 ps
CPU time 1277.02 seconds
Started Apr 16 02:20:55 PM PDT 24
Finished Apr 16 02:42:12 PM PDT 24
Peak memory 202176 kb
Host smart-16a0d8b7-e42d-4b29-8156-2865875dda9b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355628997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3355628997
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3277482972
Short name T799
Test name
Test status
Simulation time 94839442585 ps
CPU time 564.56 seconds
Started Apr 16 02:20:56 PM PDT 24
Finished Apr 16 02:30:21 PM PDT 24
Peak memory 202652 kb
Host smart-2d0fdcbe-a658-4f65-af23-3dfe817a9ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277482972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3277482972
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3639737047
Short name T395
Test name
Test status
Simulation time 36315708100 ps
CPU time 88.81 seconds
Started Apr 16 02:20:56 PM PDT 24
Finished Apr 16 02:22:25 PM PDT 24
Peak memory 202032 kb
Host smart-922978fd-6f15-4096-96ab-1ec6610e986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639737047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3639737047
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.937717180
Short name T534
Test name
Test status
Simulation time 2988786901 ps
CPU time 7.07 seconds
Started Apr 16 02:20:55 PM PDT 24
Finished Apr 16 02:21:03 PM PDT 24
Peak memory 202040 kb
Host smart-f00a9aba-2b90-4f6d-9299-095fb9fbe746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937717180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.937717180
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1081814907
Short name T78
Test name
Test status
Simulation time 7445156724 ps
CPU time 16.82 seconds
Started Apr 16 02:21:00 PM PDT 24
Finished Apr 16 02:21:17 PM PDT 24
Peak memory 217828 kb
Host smart-07f19a89-676f-462e-b12e-e4d279611dbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081814907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1081814907
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1161635957
Short name T636
Test name
Test status
Simulation time 5617411355 ps
CPU time 4.14 seconds
Started Apr 16 02:20:56 PM PDT 24
Finished Apr 16 02:21:00 PM PDT 24
Peak memory 202092 kb
Host smart-984f2a95-0df8-40ec-b255-35e5b2095c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161635957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1161635957
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1966650822
Short name T462
Test name
Test status
Simulation time 208101549025 ps
CPU time 112.86 seconds
Started Apr 16 02:21:00 PM PDT 24
Finished Apr 16 02:22:54 PM PDT 24
Peak memory 202320 kb
Host smart-b15ebd1b-3f02-43d7-9fa9-6a50afa54381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966650822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1966650822
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1482462175
Short name T252
Test name
Test status
Simulation time 259196018842 ps
CPU time 309.37 seconds
Started Apr 16 02:20:59 PM PDT 24
Finished Apr 16 02:26:09 PM PDT 24
Peak memory 218436 kb
Host smart-e9e1e55c-eb11-4250-87c1-229f961387f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482462175 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1482462175
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3437426915
Short name T405
Test name
Test status
Simulation time 536047836 ps
CPU time 1.2 seconds
Started Apr 16 02:26:23 PM PDT 24
Finished Apr 16 02:26:24 PM PDT 24
Peak memory 201944 kb
Host smart-ff23ca3a-4c92-40be-9963-957a796a0da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437426915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3437426915
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2012648270
Short name T776
Test name
Test status
Simulation time 331116800902 ps
CPU time 114.76 seconds
Started Apr 16 02:26:16 PM PDT 24
Finished Apr 16 02:28:11 PM PDT 24
Peak memory 202332 kb
Host smart-2ccce8c3-a83d-4b2c-87ff-92f5232c0a1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012648270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2012648270
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.4102374718
Short name T434
Test name
Test status
Simulation time 173460748575 ps
CPU time 413.65 seconds
Started Apr 16 02:26:19 PM PDT 24
Finished Apr 16 02:33:13 PM PDT 24
Peak memory 202284 kb
Host smart-6ca39953-1062-4569-be13-7f1f82577873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102374718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.4102374718
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3393619030
Short name T289
Test name
Test status
Simulation time 162486902993 ps
CPU time 370.4 seconds
Started Apr 16 02:26:10 PM PDT 24
Finished Apr 16 02:32:21 PM PDT 24
Peak memory 202240 kb
Host smart-51fd266f-88aa-4d1d-aed3-d4ea6e53999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393619030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3393619030
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2205811789
Short name T420
Test name
Test status
Simulation time 163007330518 ps
CPU time 87.09 seconds
Started Apr 16 02:26:14 PM PDT 24
Finished Apr 16 02:27:42 PM PDT 24
Peak memory 202304 kb
Host smart-907a27a7-c2ca-4058-a159-b80e3df98cd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205811789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2205811789
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.4221348822
Short name T566
Test name
Test status
Simulation time 489921429128 ps
CPU time 571.03 seconds
Started Apr 16 02:26:12 PM PDT 24
Finished Apr 16 02:35:43 PM PDT 24
Peak memory 202312 kb
Host smart-1a7f5561-13bf-4522-a704-01daae5bfd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221348822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.4221348822
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2802250447
Short name T548
Test name
Test status
Simulation time 335618521588 ps
CPU time 200.72 seconds
Started Apr 16 02:26:10 PM PDT 24
Finished Apr 16 02:29:32 PM PDT 24
Peak memory 202268 kb
Host smart-fb63f183-0725-4bf2-8643-6bc061d5ca10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802250447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2802250447
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3069403162
Short name T705
Test name
Test status
Simulation time 193383328244 ps
CPU time 462.79 seconds
Started Apr 16 02:26:14 PM PDT 24
Finished Apr 16 02:33:58 PM PDT 24
Peak memory 202260 kb
Host smart-682608bc-87e4-40fe-9445-efdc6e7966cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069403162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3069403162
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.21567525
Short name T593
Test name
Test status
Simulation time 581945293157 ps
CPU time 1378.06 seconds
Started Apr 16 02:26:12 PM PDT 24
Finished Apr 16 02:49:11 PM PDT 24
Peak memory 202220 kb
Host smart-1d17a5b1-bbe8-4eab-aacb-d386092b28ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21567525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.a
dc_ctrl_filters_wakeup_fixed.21567525
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.906789775
Short name T128
Test name
Test status
Simulation time 109609277984 ps
CPU time 512.7 seconds
Started Apr 16 02:26:20 PM PDT 24
Finished Apr 16 02:34:53 PM PDT 24
Peak memory 202624 kb
Host smart-e8d7bb53-8db7-482d-bdc2-1c9138d30b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906789775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.906789775
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.247714682
Short name T773
Test name
Test status
Simulation time 34501896144 ps
CPU time 18.72 seconds
Started Apr 16 02:26:18 PM PDT 24
Finished Apr 16 02:26:37 PM PDT 24
Peak memory 202044 kb
Host smart-fcff60e5-a8f2-436d-bad2-384b1e6065ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247714682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.247714682
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3733550084
Short name T641
Test name
Test status
Simulation time 5135872071 ps
CPU time 7.91 seconds
Started Apr 16 02:26:18 PM PDT 24
Finished Apr 16 02:26:27 PM PDT 24
Peak memory 202032 kb
Host smart-90f74826-0a6f-4211-bfbd-de390b497e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733550084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3733550084
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2253073183
Short name T745
Test name
Test status
Simulation time 6026646427 ps
CPU time 3.02 seconds
Started Apr 16 02:26:09 PM PDT 24
Finished Apr 16 02:26:12 PM PDT 24
Peak memory 202068 kb
Host smart-32ecc29b-1c74-4027-8edf-b2434bd1816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253073183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2253073183
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3873605609
Short name T768
Test name
Test status
Simulation time 72861959584 ps
CPU time 174.73 seconds
Started Apr 16 02:26:24 PM PDT 24
Finished Apr 16 02:29:19 PM PDT 24
Peak memory 202092 kb
Host smart-eb404fb2-1857-48ad-8924-f2022637bbd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873605609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3873605609
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1661135055
Short name T565
Test name
Test status
Simulation time 54248026338 ps
CPU time 31.25 seconds
Started Apr 16 02:26:23 PM PDT 24
Finished Apr 16 02:26:55 PM PDT 24
Peak memory 202392 kb
Host smart-7e146675-6099-4c22-a5cd-5d9eec5b0f59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661135055 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1661135055
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2693585947
Short name T724
Test name
Test status
Simulation time 303956984 ps
CPU time 0.8 seconds
Started Apr 16 02:26:35 PM PDT 24
Finished Apr 16 02:26:37 PM PDT 24
Peak memory 201948 kb
Host smart-7a44f197-f75b-4c5b-b387-9a324e92f34d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693585947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2693585947
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2909238547
Short name T329
Test name
Test status
Simulation time 163341540639 ps
CPU time 107.43 seconds
Started Apr 16 02:26:30 PM PDT 24
Finished Apr 16 02:28:18 PM PDT 24
Peak memory 202252 kb
Host smart-3754b86f-ca09-48c0-be38-ca4cec990412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909238547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2909238547
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1228839556
Short name T456
Test name
Test status
Simulation time 159794335262 ps
CPU time 363.02 seconds
Started Apr 16 02:26:23 PM PDT 24
Finished Apr 16 02:32:27 PM PDT 24
Peak memory 202256 kb
Host smart-e353b059-e638-485b-8a2f-99b8fd917b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228839556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1228839556
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1600196350
Short name T796
Test name
Test status
Simulation time 165343431253 ps
CPU time 177.35 seconds
Started Apr 16 02:26:25 PM PDT 24
Finished Apr 16 02:29:23 PM PDT 24
Peak memory 202348 kb
Host smart-503b9afa-ac75-4e3b-b75c-9478ce92a939
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600196350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1600196350
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1750767663
Short name T397
Test name
Test status
Simulation time 164012985512 ps
CPU time 96.96 seconds
Started Apr 16 02:26:25 PM PDT 24
Finished Apr 16 02:28:03 PM PDT 24
Peak memory 202196 kb
Host smart-1818c596-7b45-47e5-9253-7eb3b86a0f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750767663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1750767663
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.656186797
Short name T660
Test name
Test status
Simulation time 333298387705 ps
CPU time 401.14 seconds
Started Apr 16 02:26:23 PM PDT 24
Finished Apr 16 02:33:05 PM PDT 24
Peak memory 202204 kb
Host smart-5b4be746-e087-4c1e-a465-37aa287edc46
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=656186797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.656186797
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1859147169
Short name T211
Test name
Test status
Simulation time 550261672819 ps
CPU time 321.27 seconds
Started Apr 16 02:26:31 PM PDT 24
Finished Apr 16 02:31:52 PM PDT 24
Peak memory 202356 kb
Host smart-f6a0fd17-1a2d-4368-a339-8b6f2aaeea42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859147169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1859147169
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.801036965
Short name T698
Test name
Test status
Simulation time 405960694608 ps
CPU time 236.76 seconds
Started Apr 16 02:26:31 PM PDT 24
Finished Apr 16 02:30:28 PM PDT 24
Peak memory 202240 kb
Host smart-21ed4c5c-03ed-46a9-b8d6-557d858969bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801036965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.801036965
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.4000750485
Short name T607
Test name
Test status
Simulation time 70815568112 ps
CPU time 254.19 seconds
Started Apr 16 02:26:30 PM PDT 24
Finished Apr 16 02:30:45 PM PDT 24
Peak memory 202524 kb
Host smart-d47ebe78-cb5c-4a59-8ffc-2c38524d02cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000750485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.4000750485
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2544370776
Short name T567
Test name
Test status
Simulation time 45958035739 ps
CPU time 57.04 seconds
Started Apr 16 02:26:29 PM PDT 24
Finished Apr 16 02:27:26 PM PDT 24
Peak memory 202104 kb
Host smart-b54f9ffc-6b5c-47c7-9b07-aebb6971f8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544370776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2544370776
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1066228412
Short name T479
Test name
Test status
Simulation time 4925810708 ps
CPU time 12.99 seconds
Started Apr 16 02:26:33 PM PDT 24
Finished Apr 16 02:26:47 PM PDT 24
Peak memory 202032 kb
Host smart-b9be2f4e-b1f6-4be1-ad8a-d7ef37dcdcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066228412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1066228412
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3880582177
Short name T743
Test name
Test status
Simulation time 5965223074 ps
CPU time 4.57 seconds
Started Apr 16 02:26:25 PM PDT 24
Finished Apr 16 02:26:30 PM PDT 24
Peak memory 202076 kb
Host smart-6adf5a25-423d-4c5b-82d5-51799dd8c9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880582177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3880582177
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2602825331
Short name T368
Test name
Test status
Simulation time 49245088801 ps
CPU time 10.68 seconds
Started Apr 16 02:26:35 PM PDT 24
Finished Apr 16 02:26:46 PM PDT 24
Peak memory 202044 kb
Host smart-8d8fba1b-9897-402c-9ebc-4701b767a303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602825331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2602825331
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2534578687
Short name T481
Test name
Test status
Simulation time 358289069 ps
CPU time 1.43 seconds
Started Apr 16 02:26:48 PM PDT 24
Finished Apr 16 02:26:50 PM PDT 24
Peak memory 201980 kb
Host smart-041c98ae-2377-454a-b740-9b6d2862f81d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534578687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2534578687
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.4086677470
Short name T539
Test name
Test status
Simulation time 414906969143 ps
CPU time 163.21 seconds
Started Apr 16 02:26:46 PM PDT 24
Finished Apr 16 02:29:30 PM PDT 24
Peak memory 202236 kb
Host smart-52b882a7-d4e3-44df-830b-b7edc10a7a3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086677470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.4086677470
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3362674864
Short name T595
Test name
Test status
Simulation time 162906237780 ps
CPU time 249.88 seconds
Started Apr 16 02:26:45 PM PDT 24
Finished Apr 16 02:30:56 PM PDT 24
Peak memory 202256 kb
Host smart-004b7d06-8aab-416f-b782-923f0d0f00cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362674864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3362674864
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2605342371
Short name T239
Test name
Test status
Simulation time 498377815001 ps
CPU time 1185.91 seconds
Started Apr 16 02:26:37 PM PDT 24
Finished Apr 16 02:46:24 PM PDT 24
Peak memory 202172 kb
Host smart-3e566d54-a36e-44e4-8bfc-5aa9ccd8e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605342371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2605342371
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.34282476
Short name T712
Test name
Test status
Simulation time 324443991112 ps
CPU time 201.3 seconds
Started Apr 16 02:26:40 PM PDT 24
Finished Apr 16 02:30:02 PM PDT 24
Peak memory 202228 kb
Host smart-e6183cc4-87c7-4987-bed3-73b197cad60a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=34282476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt
_fixed.34282476
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3554779065
Short name T598
Test name
Test status
Simulation time 166698426125 ps
CPU time 190.63 seconds
Started Apr 16 02:26:36 PM PDT 24
Finished Apr 16 02:29:47 PM PDT 24
Peak memory 202324 kb
Host smart-bac2052a-4a7b-4346-88b8-834a4978d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554779065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3554779065
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3272885027
Short name T628
Test name
Test status
Simulation time 325903299992 ps
CPU time 360.6 seconds
Started Apr 16 02:26:38 PM PDT 24
Finished Apr 16 02:32:39 PM PDT 24
Peak memory 202236 kb
Host smart-52ec332d-09d1-4090-898c-0519bc495570
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272885027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3272885027
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3250988918
Short name T781
Test name
Test status
Simulation time 346709698112 ps
CPU time 203.13 seconds
Started Apr 16 02:26:39 PM PDT 24
Finished Apr 16 02:30:03 PM PDT 24
Peak memory 202344 kb
Host smart-6c5c45be-1b79-4e7c-86d6-d8f4399a6cf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250988918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3250988918
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3735285615
Short name T544
Test name
Test status
Simulation time 196087891596 ps
CPU time 93.85 seconds
Started Apr 16 02:26:44 PM PDT 24
Finished Apr 16 02:28:19 PM PDT 24
Peak memory 202244 kb
Host smart-aeb6af71-6e69-4903-b5bf-7b42f63aca48
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735285615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3735285615
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.89187131
Short name T706
Test name
Test status
Simulation time 72859834686 ps
CPU time 232.91 seconds
Started Apr 16 02:26:46 PM PDT 24
Finished Apr 16 02:30:40 PM PDT 24
Peak memory 202532 kb
Host smart-971e7cb5-6ec8-4ecd-859d-74cdb6c7562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89187131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.89187131
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3858360262
Short name T425
Test name
Test status
Simulation time 28389592594 ps
CPU time 32.21 seconds
Started Apr 16 02:26:45 PM PDT 24
Finished Apr 16 02:27:18 PM PDT 24
Peak memory 202064 kb
Host smart-3646e4ec-dee9-4c73-b735-9996a6fa64e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858360262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3858360262
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2841892956
Short name T645
Test name
Test status
Simulation time 2886633381 ps
CPU time 3.79 seconds
Started Apr 16 02:26:44 PM PDT 24
Finished Apr 16 02:26:48 PM PDT 24
Peak memory 202008 kb
Host smart-eb055622-2535-462e-9c91-a69c53b994e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841892956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2841892956
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3898773660
Short name T605
Test name
Test status
Simulation time 5599384233 ps
CPU time 3.96 seconds
Started Apr 16 02:26:36 PM PDT 24
Finished Apr 16 02:26:41 PM PDT 24
Peak memory 201988 kb
Host smart-5d067017-8393-46ba-bf5d-3d033aa4a9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898773660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3898773660
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.4137071089
Short name T62
Test name
Test status
Simulation time 164612276894 ps
CPU time 101.45 seconds
Started Apr 16 02:26:53 PM PDT 24
Finished Apr 16 02:28:35 PM PDT 24
Peak memory 202272 kb
Host smart-6cc74f3e-df9a-4a21-b996-4996c67bdc64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137071089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.4137071089
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.692788078
Short name T286
Test name
Test status
Simulation time 27046991264 ps
CPU time 50.16 seconds
Started Apr 16 02:26:49 PM PDT 24
Finished Apr 16 02:27:40 PM PDT 24
Peak memory 219020 kb
Host smart-a03c745f-8d60-4060-9ac7-c83b0a767075
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692788078 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.692788078
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2160758038
Short name T410
Test name
Test status
Simulation time 342848140 ps
CPU time 1.42 seconds
Started Apr 16 02:26:58 PM PDT 24
Finished Apr 16 02:27:00 PM PDT 24
Peak memory 201992 kb
Host smart-af7a57e6-0b7c-44db-b4d3-e45feec44fcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160758038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2160758038
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1484916054
Short name T302
Test name
Test status
Simulation time 496493561923 ps
CPU time 552.96 seconds
Started Apr 16 02:26:53 PM PDT 24
Finished Apr 16 02:36:07 PM PDT 24
Peak memory 202328 kb
Host smart-b2ac4bf8-b173-48f1-a04c-5c818e2108e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484916054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1484916054
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2439639576
Short name T293
Test name
Test status
Simulation time 159699843703 ps
CPU time 22.79 seconds
Started Apr 16 02:26:53 PM PDT 24
Finished Apr 16 02:27:17 PM PDT 24
Peak memory 202352 kb
Host smart-5693c08d-8057-4703-845b-cdaa91e34199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439639576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2439639576
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3690547588
Short name T240
Test name
Test status
Simulation time 161494734680 ps
CPU time 110.05 seconds
Started Apr 16 02:26:50 PM PDT 24
Finished Apr 16 02:28:41 PM PDT 24
Peak memory 202248 kb
Host smart-9482b4d2-acfd-4341-8573-f1a69a1e5a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690547588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3690547588
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3382237677
Short name T483
Test name
Test status
Simulation time 324830399534 ps
CPU time 789.29 seconds
Started Apr 16 02:26:52 PM PDT 24
Finished Apr 16 02:40:02 PM PDT 24
Peak memory 202236 kb
Host smart-24dcf2af-ef85-408a-b864-1bb268ac4cda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382237677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3382237677
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2419691889
Short name T588
Test name
Test status
Simulation time 486605206451 ps
CPU time 1063.4 seconds
Started Apr 16 02:26:53 PM PDT 24
Finished Apr 16 02:44:37 PM PDT 24
Peak memory 202316 kb
Host smart-3b4405ce-f375-41df-a7a1-809adbaf31c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419691889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2419691889
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.4267198901
Short name T400
Test name
Test status
Simulation time 330540088725 ps
CPU time 804.56 seconds
Started Apr 16 02:26:49 PM PDT 24
Finished Apr 16 02:40:15 PM PDT 24
Peak memory 202132 kb
Host smart-ee8b980d-fe7f-49f7-a376-e59a1be3bb00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267198901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.4267198901
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.237830802
Short name T663
Test name
Test status
Simulation time 398484935371 ps
CPU time 887.78 seconds
Started Apr 16 02:26:55 PM PDT 24
Finished Apr 16 02:41:43 PM PDT 24
Peak memory 202264 kb
Host smart-c3300eee-5be3-45e3-9ca9-15a68fa5eb1b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237830802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.237830802
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3211613620
Short name T494
Test name
Test status
Simulation time 123303470055 ps
CPU time 629.02 seconds
Started Apr 16 02:26:53 PM PDT 24
Finished Apr 16 02:37:23 PM PDT 24
Peak memory 202640 kb
Host smart-46e1655a-81a2-4667-bdd8-8c64b52832e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211613620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3211613620
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.688508841
Short name T172
Test name
Test status
Simulation time 39363218663 ps
CPU time 86.45 seconds
Started Apr 16 02:26:55 PM PDT 24
Finished Apr 16 02:28:22 PM PDT 24
Peak memory 202064 kb
Host smart-4b94d696-62cf-45ca-bf83-342af526deb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688508841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.688508841
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2211378338
Short name T427
Test name
Test status
Simulation time 4037225924 ps
CPU time 3.25 seconds
Started Apr 16 02:26:55 PM PDT 24
Finished Apr 16 02:26:59 PM PDT 24
Peak memory 201992 kb
Host smart-8c2589d8-9bf0-477f-9cd5-53dbc22ef55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211378338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2211378338
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.554053835
Short name T670
Test name
Test status
Simulation time 5757740151 ps
CPU time 7.37 seconds
Started Apr 16 02:26:49 PM PDT 24
Finished Apr 16 02:26:57 PM PDT 24
Peak memory 202100 kb
Host smart-e5ffd957-0441-4393-9fb8-9ebbec80942f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554053835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.554053835
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3389465271
Short name T360
Test name
Test status
Simulation time 453603968544 ps
CPU time 427.9 seconds
Started Apr 16 02:26:57 PM PDT 24
Finished Apr 16 02:34:06 PM PDT 24
Peak memory 210756 kb
Host smart-2591171d-4ef7-4df5-b2a5-39e67727cb52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389465271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3389465271
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1747874035
Short name T17
Test name
Test status
Simulation time 32837457284 ps
CPU time 36.1 seconds
Started Apr 16 02:26:58 PM PDT 24
Finished Apr 16 02:27:35 PM PDT 24
Peak memory 210888 kb
Host smart-9709e853-bb8d-41ec-858d-469e12fc0790
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747874035 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1747874035
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2336057576
Short name T126
Test name
Test status
Simulation time 286991543 ps
CPU time 0.95 seconds
Started Apr 16 02:27:08 PM PDT 24
Finished Apr 16 02:27:10 PM PDT 24
Peak memory 201856 kb
Host smart-5a021ea2-4206-4f82-8b46-e55271dc2d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336057576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2336057576
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1427047163
Short name T110
Test name
Test status
Simulation time 327220068182 ps
CPU time 714.66 seconds
Started Apr 16 02:27:04 PM PDT 24
Finished Apr 16 02:39:00 PM PDT 24
Peak memory 202324 kb
Host smart-93e723c6-b1a6-48c7-9ccb-78ef7d6bc89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427047163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1427047163
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2745531724
Short name T710
Test name
Test status
Simulation time 488523804550 ps
CPU time 356.46 seconds
Started Apr 16 02:27:03 PM PDT 24
Finished Apr 16 02:33:00 PM PDT 24
Peak memory 202196 kb
Host smart-f770164e-bc0a-4f8e-877f-8ecf3645aa2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745531724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2745531724
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1356734958
Short name T390
Test name
Test status
Simulation time 163628273705 ps
CPU time 359.54 seconds
Started Apr 16 02:26:58 PM PDT 24
Finished Apr 16 02:32:58 PM PDT 24
Peak memory 202192 kb
Host smart-6e1c4794-a7e0-444f-aebc-5096c0e755ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356734958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1356734958
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.4148070971
Short name T205
Test name
Test status
Simulation time 524671586320 ps
CPU time 340.94 seconds
Started Apr 16 02:27:03 PM PDT 24
Finished Apr 16 02:32:45 PM PDT 24
Peak memory 202256 kb
Host smart-cadfa4b0-504d-40f6-bb5d-4653d71ced8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148070971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.4148070971
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2649260247
Short name T501
Test name
Test status
Simulation time 609081452820 ps
CPU time 427.79 seconds
Started Apr 16 02:27:05 PM PDT 24
Finished Apr 16 02:34:14 PM PDT 24
Peak memory 202196 kb
Host smart-e3d5a76c-2e39-4f54-a191-6da555c8fc99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649260247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2649260247
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1790324692
Short name T351
Test name
Test status
Simulation time 125968616397 ps
CPU time 477.82 seconds
Started Apr 16 02:27:06 PM PDT 24
Finished Apr 16 02:35:05 PM PDT 24
Peak memory 202656 kb
Host smart-95e99947-f172-4df9-96e7-76c417173518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790324692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1790324692
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.204173845
Short name T415
Test name
Test status
Simulation time 25908362392 ps
CPU time 60.21 seconds
Started Apr 16 02:27:04 PM PDT 24
Finished Apr 16 02:28:05 PM PDT 24
Peak memory 202032 kb
Host smart-2af464b9-279c-4e7f-80c8-494a6848185a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204173845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.204173845
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2912446483
Short name T158
Test name
Test status
Simulation time 3100749844 ps
CPU time 2.51 seconds
Started Apr 16 02:27:02 PM PDT 24
Finished Apr 16 02:27:05 PM PDT 24
Peak memory 202048 kb
Host smart-8d3061ed-a765-4d3f-bb05-227fdb21b2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912446483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2912446483
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1227251619
Short name T130
Test name
Test status
Simulation time 5988455718 ps
CPU time 4.56 seconds
Started Apr 16 02:26:57 PM PDT 24
Finished Apr 16 02:27:02 PM PDT 24
Peak memory 202084 kb
Host smart-634cbbaf-301f-476f-a6ca-815ac18504fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227251619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1227251619
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.498978089
Short name T117
Test name
Test status
Simulation time 458961435255 ps
CPU time 318.43 seconds
Started Apr 16 02:27:10 PM PDT 24
Finished Apr 16 02:32:30 PM PDT 24
Peak memory 210680 kb
Host smart-ec1f273e-652e-4e64-8aea-6b2cf6377ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498978089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
498978089
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1769755096
Short name T51
Test name
Test status
Simulation time 382160487199 ps
CPU time 226.94 seconds
Started Apr 16 02:27:05 PM PDT 24
Finished Apr 16 02:30:53 PM PDT 24
Peak memory 210868 kb
Host smart-a9f25fbe-f4c9-47d9-8d4f-b1e8848b8bdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769755096 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1769755096
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.862836263
Short name T465
Test name
Test status
Simulation time 363657023 ps
CPU time 1.33 seconds
Started Apr 16 02:27:19 PM PDT 24
Finished Apr 16 02:27:21 PM PDT 24
Peak memory 201960 kb
Host smart-70903166-9f3e-4791-bc61-9ecc99d03bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862836263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.862836263
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.190594064
Short name T689
Test name
Test status
Simulation time 166307981423 ps
CPU time 400.84 seconds
Started Apr 16 02:27:17 PM PDT 24
Finished Apr 16 02:33:58 PM PDT 24
Peak memory 202016 kb
Host smart-a3cdf762-4331-4529-ac83-5ae14db3c224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190594064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.190594064
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1362698573
Short name T225
Test name
Test status
Simulation time 165249968680 ps
CPU time 89.05 seconds
Started Apr 16 02:27:11 PM PDT 24
Finished Apr 16 02:28:41 PM PDT 24
Peak memory 202264 kb
Host smart-6eb571cf-c9ae-46ed-9bbd-44f2399f8c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362698573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1362698573
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1961052683
Short name T536
Test name
Test status
Simulation time 323234124831 ps
CPU time 789.61 seconds
Started Apr 16 02:27:17 PM PDT 24
Finished Apr 16 02:40:27 PM PDT 24
Peak memory 201896 kb
Host smart-4803ef13-788f-4b5d-ae21-c87d40753a6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961052683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1961052683
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1457672621
Short name T208
Test name
Test status
Simulation time 492046520713 ps
CPU time 585.11 seconds
Started Apr 16 02:27:09 PM PDT 24
Finished Apr 16 02:36:56 PM PDT 24
Peak memory 202180 kb
Host smart-4e36e516-d296-4c87-a071-8dd4da9a9cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457672621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1457672621
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2073950424
Short name T436
Test name
Test status
Simulation time 491363982610 ps
CPU time 1084.98 seconds
Started Apr 16 02:27:15 PM PDT 24
Finished Apr 16 02:45:21 PM PDT 24
Peak memory 202212 kb
Host smart-b6e15a8b-ab20-4ef0-911a-c758435bfc81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073950424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2073950424
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1696272505
Short name T180
Test name
Test status
Simulation time 197291306363 ps
CPU time 97.34 seconds
Started Apr 16 02:27:14 PM PDT 24
Finished Apr 16 02:28:52 PM PDT 24
Peak memory 202220 kb
Host smart-fb283ad1-ea06-488e-a7e2-4730558f8613
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696272505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1696272505
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1080685515
Short name T677
Test name
Test status
Simulation time 105845630056 ps
CPU time 372.22 seconds
Started Apr 16 02:27:17 PM PDT 24
Finished Apr 16 02:33:31 PM PDT 24
Peak memory 202624 kb
Host smart-6f777aae-00c2-4b20-bc61-096bffc21d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080685515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1080685515
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.945464302
Short name T608
Test name
Test status
Simulation time 27699588638 ps
CPU time 65.11 seconds
Started Apr 16 02:27:17 PM PDT 24
Finished Apr 16 02:28:23 PM PDT 24
Peak memory 202048 kb
Host smart-098df6a6-0252-4664-97d1-3690951188ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945464302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.945464302
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2076720715
Short name T376
Test name
Test status
Simulation time 3446649742 ps
CPU time 2.68 seconds
Started Apr 16 02:27:13 PM PDT 24
Finished Apr 16 02:27:16 PM PDT 24
Peak memory 202088 kb
Host smart-d0f40ded-6ff6-4edb-ae0b-dfdb0b6099d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076720715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2076720715
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2103063511
Short name T631
Test name
Test status
Simulation time 6098225140 ps
CPU time 3.77 seconds
Started Apr 16 02:27:09 PM PDT 24
Finished Apr 16 02:27:14 PM PDT 24
Peak memory 202072 kb
Host smart-6466f506-59ce-4c74-abcd-ef27d0fbf124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103063511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2103063511
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1424107572
Short name T120
Test name
Test status
Simulation time 340499966931 ps
CPU time 54.93 seconds
Started Apr 16 02:27:18 PM PDT 24
Finished Apr 16 02:28:14 PM PDT 24
Peak memory 202292 kb
Host smart-b0e70aaa-d445-46ab-b466-b59a5e5706e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424107572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1424107572
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.765127606
Short name T342
Test name
Test status
Simulation time 234463389443 ps
CPU time 187.83 seconds
Started Apr 16 02:27:18 PM PDT 24
Finished Apr 16 02:30:27 PM PDT 24
Peak memory 210952 kb
Host smart-434c011c-7bc7-4c67-a6c4-91cb74d14ef4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765127606 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.765127606
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2972493360
Short name T389
Test name
Test status
Simulation time 484906972 ps
CPU time 1.68 seconds
Started Apr 16 02:27:25 PM PDT 24
Finished Apr 16 02:27:28 PM PDT 24
Peak memory 201964 kb
Host smart-0bfee343-40bc-464e-bab2-dedfcad39192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972493360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2972493360
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.687348422
Short name T318
Test name
Test status
Simulation time 162682352324 ps
CPU time 144.94 seconds
Started Apr 16 02:27:23 PM PDT 24
Finished Apr 16 02:29:49 PM PDT 24
Peak memory 202296 kb
Host smart-26d8825e-4979-466d-949e-c37d6efc6ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687348422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.687348422
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2433017408
Short name T367
Test name
Test status
Simulation time 491347329978 ps
CPU time 289.68 seconds
Started Apr 16 02:27:23 PM PDT 24
Finished Apr 16 02:32:13 PM PDT 24
Peak memory 202240 kb
Host smart-f60524d6-81a8-4d02-858b-5fb67ef6f692
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433017408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2433017408
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2378864924
Short name T288
Test name
Test status
Simulation time 325956291363 ps
CPU time 60.43 seconds
Started Apr 16 02:27:18 PM PDT 24
Finished Apr 16 02:28:20 PM PDT 24
Peak memory 202168 kb
Host smart-2d29aa94-a889-4894-8a7b-3e6b0a8223df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378864924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2378864924
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1812748116
Short name T788
Test name
Test status
Simulation time 166349114569 ps
CPU time 70.36 seconds
Started Apr 16 02:27:18 PM PDT 24
Finished Apr 16 02:28:29 PM PDT 24
Peak memory 202324 kb
Host smart-849d59f0-6e62-4f76-9c8e-8ec8e84fa4f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812748116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1812748116
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3337777452
Short name T134
Test name
Test status
Simulation time 525213986319 ps
CPU time 1244.41 seconds
Started Apr 16 02:27:22 PM PDT 24
Finished Apr 16 02:48:07 PM PDT 24
Peak memory 202368 kb
Host smart-a9a43eff-fe3a-4c77-a187-6b6cf48f1e21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337777452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3337777452
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.4062209567
Short name T247
Test name
Test status
Simulation time 394041441295 ps
CPU time 245.86 seconds
Started Apr 16 02:27:22 PM PDT 24
Finished Apr 16 02:31:29 PM PDT 24
Peak memory 202220 kb
Host smart-d50082f7-c6d6-4f79-8968-3fc63d9c07da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062209567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.4062209567
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.269075556
Short name T757
Test name
Test status
Simulation time 75185535679 ps
CPU time 258.49 seconds
Started Apr 16 02:27:21 PM PDT 24
Finished Apr 16 02:31:40 PM PDT 24
Peak memory 202656 kb
Host smart-87630f86-1288-4a19-a03d-df51bc19d185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269075556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.269075556
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.923909415
Short name T711
Test name
Test status
Simulation time 28519465788 ps
CPU time 24.93 seconds
Started Apr 16 02:27:22 PM PDT 24
Finished Apr 16 02:27:47 PM PDT 24
Peak memory 202072 kb
Host smart-e879bfd5-72ef-41d2-b9e6-a7b8dc0845f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923909415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.923909415
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.130210871
Short name T573
Test name
Test status
Simulation time 3881261505 ps
CPU time 8.77 seconds
Started Apr 16 02:27:24 PM PDT 24
Finished Apr 16 02:27:33 PM PDT 24
Peak memory 202044 kb
Host smart-21789f76-c43c-4cac-acfb-bc8867475ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130210871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.130210871
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.839150079
Short name T435
Test name
Test status
Simulation time 5967276250 ps
CPU time 1.83 seconds
Started Apr 16 02:27:17 PM PDT 24
Finished Apr 16 02:27:20 PM PDT 24
Peak memory 202076 kb
Host smart-74de9f4c-4b34-4a55-b611-9670eb3faa11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839150079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.839150079
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3867738278
Short name T525
Test name
Test status
Simulation time 327651116959 ps
CPU time 359.11 seconds
Started Apr 16 02:27:27 PM PDT 24
Finished Apr 16 02:33:27 PM PDT 24
Peak memory 202272 kb
Host smart-1c3757b0-51b2-4f7f-91f9-c428fba79e5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867738278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3867738278
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3986626062
Short name T102
Test name
Test status
Simulation time 378398446 ps
CPU time 0.86 seconds
Started Apr 16 02:27:35 PM PDT 24
Finished Apr 16 02:27:37 PM PDT 24
Peak memory 201940 kb
Host smart-704ecbbf-8825-4feb-a30f-eccb956b50ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986626062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3986626062
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2799429896
Short name T801
Test name
Test status
Simulation time 540466871477 ps
CPU time 537.87 seconds
Started Apr 16 02:27:31 PM PDT 24
Finished Apr 16 02:36:29 PM PDT 24
Peak memory 202200 kb
Host smart-856ab78c-6faf-4f59-bc36-ba811b682dc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799429896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2799429896
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1202836283
Short name T704
Test name
Test status
Simulation time 202573958359 ps
CPU time 510.34 seconds
Started Apr 16 02:27:30 PM PDT 24
Finished Apr 16 02:36:01 PM PDT 24
Peak memory 202228 kb
Host smart-46a9e08c-31d0-4316-bc51-c98efdf7849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202836283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1202836283
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3967197532
Short name T429
Test name
Test status
Simulation time 332993280834 ps
CPU time 212.25 seconds
Started Apr 16 02:27:32 PM PDT 24
Finished Apr 16 02:31:04 PM PDT 24
Peak memory 202312 kb
Host smart-e18a20b7-8429-4760-b204-08ad0f7f3a5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967197532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3967197532
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3814558820
Short name T270
Test name
Test status
Simulation time 332493743496 ps
CPU time 807.06 seconds
Started Apr 16 02:27:24 PM PDT 24
Finished Apr 16 02:40:52 PM PDT 24
Peak memory 202360 kb
Host smart-61afbaf6-7309-4896-b093-ba5af2346f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814558820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3814558820
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4130475770
Short name T496
Test name
Test status
Simulation time 329598443717 ps
CPU time 45.52 seconds
Started Apr 16 02:27:25 PM PDT 24
Finished Apr 16 02:28:12 PM PDT 24
Peak memory 202204 kb
Host smart-9076ff06-57fb-47e8-a5d4-b80fbb4bc74f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130475770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4130475770
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2384858567
Short name T251
Test name
Test status
Simulation time 188627856141 ps
CPU time 405.63 seconds
Started Apr 16 02:27:32 PM PDT 24
Finished Apr 16 02:34:18 PM PDT 24
Peak memory 202352 kb
Host smart-3f9f9ab9-7e0a-431e-951c-613cba79bfb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384858567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2384858567
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.4144640230
Short name T542
Test name
Test status
Simulation time 397515159699 ps
CPU time 136.04 seconds
Started Apr 16 02:27:32 PM PDT 24
Finished Apr 16 02:29:48 PM PDT 24
Peak memory 202232 kb
Host smart-ac766304-a1be-4901-9a5c-a043a159b7e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144640230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.4144640230
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1163602799
Short name T474
Test name
Test status
Simulation time 106421967912 ps
CPU time 602.35 seconds
Started Apr 16 02:27:35 PM PDT 24
Finished Apr 16 02:37:38 PM PDT 24
Peak memory 202660 kb
Host smart-eb8e2dd1-f0cb-4988-bc21-235b623a4417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163602799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1163602799
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3046682040
Short name T459
Test name
Test status
Simulation time 33270180410 ps
CPU time 81.95 seconds
Started Apr 16 02:27:31 PM PDT 24
Finished Apr 16 02:28:54 PM PDT 24
Peak memory 202036 kb
Host smart-88a31d6f-c197-466a-8e98-194b6bb0b3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046682040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3046682040
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1156817191
Short name T561
Test name
Test status
Simulation time 3869648600 ps
CPU time 9.54 seconds
Started Apr 16 02:27:31 PM PDT 24
Finished Apr 16 02:27:42 PM PDT 24
Peak memory 201968 kb
Host smart-4ec759a6-933b-449a-9f11-6a1acb24c462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156817191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1156817191
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2224950720
Short name T602
Test name
Test status
Simulation time 5910093058 ps
CPU time 13 seconds
Started Apr 16 02:27:29 PM PDT 24
Finished Apr 16 02:27:43 PM PDT 24
Peak memory 202064 kb
Host smart-16b44a65-7fc4-4b7f-9355-8c3f7f253bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224950720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2224950720
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.539688560
Short name T36
Test name
Test status
Simulation time 166802963059 ps
CPU time 320.75 seconds
Started Apr 16 02:27:34 PM PDT 24
Finished Apr 16 02:32:55 PM PDT 24
Peak memory 202240 kb
Host smart-a216d10c-e1fa-4d32-8440-c1d44f69aa73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539688560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
539688560
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3938253182
Short name T231
Test name
Test status
Simulation time 28205141114 ps
CPU time 91.77 seconds
Started Apr 16 02:27:34 PM PDT 24
Finished Apr 16 02:29:07 PM PDT 24
Peak memory 210936 kb
Host smart-6ae69967-2e3c-4f34-b487-e76d941c6808
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938253182 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3938253182
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1889370721
Short name T14
Test name
Test status
Simulation time 326740941 ps
CPU time 0.8 seconds
Started Apr 16 02:27:44 PM PDT 24
Finished Apr 16 02:27:46 PM PDT 24
Peak memory 201988 kb
Host smart-bea394bb-52bb-4d7d-acef-c8c40a710f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889370721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1889370721
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2257880743
Short name T621
Test name
Test status
Simulation time 165772402784 ps
CPU time 355.38 seconds
Started Apr 16 02:27:45 PM PDT 24
Finished Apr 16 02:33:42 PM PDT 24
Peak memory 202248 kb
Host smart-a7bff287-6d66-4c89-af23-1da496db0763
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257880743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2257880743
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.336383431
Short name T463
Test name
Test status
Simulation time 159184082540 ps
CPU time 72.09 seconds
Started Apr 16 02:27:35 PM PDT 24
Finished Apr 16 02:28:48 PM PDT 24
Peak memory 202348 kb
Host smart-8b394c59-7170-4699-a9b9-fa6957021c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336383431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.336383431
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1940440783
Short name T748
Test name
Test status
Simulation time 498807990426 ps
CPU time 219.43 seconds
Started Apr 16 02:27:35 PM PDT 24
Finished Apr 16 02:31:15 PM PDT 24
Peak memory 202160 kb
Host smart-01314c35-895f-4cd7-ae55-1eac050d3c08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940440783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1940440783
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1857926222
Short name T570
Test name
Test status
Simulation time 365855543336 ps
CPU time 150.34 seconds
Started Apr 16 02:27:42 PM PDT 24
Finished Apr 16 02:30:13 PM PDT 24
Peak memory 202260 kb
Host smart-61df3731-0416-418e-ab34-655ae901b27b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857926222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1857926222
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3113664904
Short name T477
Test name
Test status
Simulation time 199420068318 ps
CPU time 429.58 seconds
Started Apr 16 02:27:45 PM PDT 24
Finished Apr 16 02:34:56 PM PDT 24
Peak memory 202160 kb
Host smart-5240f3dc-3b30-45dc-b6bd-e941b5b5ef4f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113664904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3113664904
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1824825936
Short name T458
Test name
Test status
Simulation time 136589221895 ps
CPU time 701.56 seconds
Started Apr 16 02:27:45 PM PDT 24
Finished Apr 16 02:39:28 PM PDT 24
Peak memory 202512 kb
Host smart-51f53c14-e4e2-4bd7-a485-586e47a34493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824825936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1824825936
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2767373677
Short name T55
Test name
Test status
Simulation time 42957264499 ps
CPU time 21.86 seconds
Started Apr 16 02:27:40 PM PDT 24
Finished Apr 16 02:28:03 PM PDT 24
Peak memory 202068 kb
Host smart-db4c4b72-ceeb-4f70-ab97-406a0b886280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767373677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2767373677
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.4207836620
Short name T652
Test name
Test status
Simulation time 3587141038 ps
CPU time 9.29 seconds
Started Apr 16 02:27:41 PM PDT 24
Finished Apr 16 02:27:51 PM PDT 24
Peak memory 202068 kb
Host smart-65de08c7-506d-4959-babf-c9a74070b92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207836620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.4207836620
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.4132191142
Short name T632
Test name
Test status
Simulation time 5794367697 ps
CPU time 14.61 seconds
Started Apr 16 02:27:35 PM PDT 24
Finished Apr 16 02:27:51 PM PDT 24
Peak memory 202048 kb
Host smart-0d5a3794-1a01-4670-86b5-83663059b1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132191142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.4132191142
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3767091343
Short name T190
Test name
Test status
Simulation time 331957696 ps
CPU time 1.45 seconds
Started Apr 16 02:27:54 PM PDT 24
Finished Apr 16 02:27:56 PM PDT 24
Peak memory 201904 kb
Host smart-1fb3764e-95a0-4bd7-a34d-3d3c7d63992d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767091343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3767091343
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.125194687
Short name T688
Test name
Test status
Simulation time 158868266382 ps
CPU time 253.38 seconds
Started Apr 16 02:27:49 PM PDT 24
Finished Apr 16 02:32:03 PM PDT 24
Peak memory 202256 kb
Host smart-26c70a03-7707-4924-990a-16b139a5a039
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125194687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.125194687
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1570535902
Short name T740
Test name
Test status
Simulation time 161003092022 ps
CPU time 210.29 seconds
Started Apr 16 02:27:48 PM PDT 24
Finished Apr 16 02:31:19 PM PDT 24
Peak memory 202256 kb
Host smart-86ed86df-f12e-418c-8baa-4b15ea97be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570535902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1570535902
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3392448920
Short name T505
Test name
Test status
Simulation time 494784458244 ps
CPU time 285.96 seconds
Started Apr 16 02:27:43 PM PDT 24
Finished Apr 16 02:32:29 PM PDT 24
Peak memory 202224 kb
Host smart-fca42923-d348-4a38-b662-ad92c305fa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392448920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3392448920
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1398949389
Short name T774
Test name
Test status
Simulation time 316658691126 ps
CPU time 786.03 seconds
Started Apr 16 02:27:44 PM PDT 24
Finished Apr 16 02:40:51 PM PDT 24
Peak memory 202160 kb
Host smart-8606d1e9-da9f-49c3-8e2c-29a0ab05861f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398949389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1398949389
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1848253166
Short name T220
Test name
Test status
Simulation time 500665619131 ps
CPU time 1172.1 seconds
Started Apr 16 02:27:45 PM PDT 24
Finished Apr 16 02:47:18 PM PDT 24
Peak memory 202312 kb
Host smart-116bfc06-3505-44c2-9df9-4e18ac8ccab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848253166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1848253166
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1297540935
Short name T676
Test name
Test status
Simulation time 161780403527 ps
CPU time 368.09 seconds
Started Apr 16 02:27:44 PM PDT 24
Finished Apr 16 02:33:53 PM PDT 24
Peak memory 202288 kb
Host smart-52aa5dea-71a2-4449-8ded-5a8e2b503291
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297540935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1297540935
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2182214970
Short name T304
Test name
Test status
Simulation time 558157674217 ps
CPU time 557.6 seconds
Started Apr 16 02:27:44 PM PDT 24
Finished Apr 16 02:37:03 PM PDT 24
Peak memory 202340 kb
Host smart-7038f30e-0904-47d2-adcd-0e5a9e83345d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182214970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2182214970
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1537609027
Short name T380
Test name
Test status
Simulation time 198844977150 ps
CPU time 485.39 seconds
Started Apr 16 02:27:48 PM PDT 24
Finished Apr 16 02:35:54 PM PDT 24
Peak memory 202280 kb
Host smart-54406f0c-6401-4991-8b51-bf4e158a0bcf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537609027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1537609027
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3354906172
Short name T67
Test name
Test status
Simulation time 119122707312 ps
CPU time 621.92 seconds
Started Apr 16 02:27:49 PM PDT 24
Finished Apr 16 02:38:11 PM PDT 24
Peak memory 202512 kb
Host smart-ff8f6285-6be3-47d6-b031-f4408c2724ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354906172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3354906172
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.706549051
Short name T777
Test name
Test status
Simulation time 42740115491 ps
CPU time 35.57 seconds
Started Apr 16 02:27:53 PM PDT 24
Finished Apr 16 02:28:30 PM PDT 24
Peak memory 202008 kb
Host smart-eafb2985-e339-4501-abd0-c42bad42547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706549051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.706549051
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.4208090059
Short name T594
Test name
Test status
Simulation time 3245771108 ps
CPU time 6.98 seconds
Started Apr 16 02:27:47 PM PDT 24
Finished Apr 16 02:27:55 PM PDT 24
Peak memory 202080 kb
Host smart-813d23a6-5441-4311-b74a-b3f84aed8fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208090059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.4208090059
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3264717536
Short name T507
Test name
Test status
Simulation time 5691806120 ps
CPU time 14.15 seconds
Started Apr 16 02:27:47 PM PDT 24
Finished Apr 16 02:28:01 PM PDT 24
Peak memory 202024 kb
Host smart-7bb65a0e-01f4-4a47-bf8d-f15947af5cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264717536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3264717536
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1014375548
Short name T244
Test name
Test status
Simulation time 473979348802 ps
CPU time 424.27 seconds
Started Apr 16 02:27:48 PM PDT 24
Finished Apr 16 02:34:53 PM PDT 24
Peak memory 210820 kb
Host smart-19b02561-8878-4a09-b554-5445dcaee153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014375548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1014375548
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3632817694
Short name T637
Test name
Test status
Simulation time 532538883 ps
CPU time 1.63 seconds
Started Apr 16 02:21:06 PM PDT 24
Finished Apr 16 02:21:09 PM PDT 24
Peak memory 201980 kb
Host smart-6a172791-3d4a-4475-a161-cf55523bfbf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632817694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3632817694
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3194977335
Short name T300
Test name
Test status
Simulation time 166759595431 ps
CPU time 81.16 seconds
Started Apr 16 02:21:00 PM PDT 24
Finished Apr 16 02:22:22 PM PDT 24
Peak memory 202332 kb
Host smart-def8e038-880e-4e34-8e14-7b0773caa009
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194977335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3194977335
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2108076
Short name T798
Test name
Test status
Simulation time 166545157872 ps
CPU time 108.82 seconds
Started Apr 16 02:21:01 PM PDT 24
Finished Apr 16 02:22:50 PM PDT 24
Peak memory 202260 kb
Host smart-10aa44da-4fff-4a2f-b52c-eedabe3eb9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2108076
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1742371609
Short name T301
Test name
Test status
Simulation time 486027944414 ps
CPU time 315.45 seconds
Started Apr 16 02:21:01 PM PDT 24
Finished Apr 16 02:26:17 PM PDT 24
Peak memory 202244 kb
Host smart-7f5dae34-0ec1-434f-aeb3-1500d70717ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742371609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1742371609
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3799361243
Short name T672
Test name
Test status
Simulation time 330311244972 ps
CPU time 379.71 seconds
Started Apr 16 02:20:58 PM PDT 24
Finished Apr 16 02:27:19 PM PDT 24
Peak memory 202296 kb
Host smart-38841ee3-80b1-4c62-9c92-88cba6689c1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799361243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3799361243
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2475099141
Short name T307
Test name
Test status
Simulation time 162070141750 ps
CPU time 99.73 seconds
Started Apr 16 02:21:01 PM PDT 24
Finished Apr 16 02:22:41 PM PDT 24
Peak memory 202332 kb
Host smart-acdbf055-dade-47d3-bfff-01e2ba55db72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475099141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2475099141
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3319536269
Short name T366
Test name
Test status
Simulation time 485389397078 ps
CPU time 460.88 seconds
Started Apr 16 02:21:03 PM PDT 24
Finished Apr 16 02:28:44 PM PDT 24
Peak memory 202136 kb
Host smart-bd79b971-1567-4d84-8da6-5e74502b7fa9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319536269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3319536269
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.853068158
Short name T104
Test name
Test status
Simulation time 198152529058 ps
CPU time 439.57 seconds
Started Apr 16 02:20:59 PM PDT 24
Finished Apr 16 02:28:19 PM PDT 24
Peak memory 202272 kb
Host smart-5195eec3-66ff-46b2-96c0-5de73e75d984
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853068158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.853068158
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2667839715
Short name T599
Test name
Test status
Simulation time 198718518681 ps
CPU time 196.9 seconds
Started Apr 16 02:20:59 PM PDT 24
Finished Apr 16 02:24:17 PM PDT 24
Peak memory 202176 kb
Host smart-6f216c1c-e37f-4e33-9619-4cc749f6aedf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667839715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2667839715
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1209306031
Short name T715
Test name
Test status
Simulation time 111140563752 ps
CPU time 429.69 seconds
Started Apr 16 02:21:00 PM PDT 24
Finished Apr 16 02:28:11 PM PDT 24
Peak memory 202600 kb
Host smart-8b5c39a3-6bf6-4ef1-99e0-3d11b4c5f7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209306031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1209306031
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3033982521
Short name T42
Test name
Test status
Simulation time 32570931837 ps
CPU time 7.87 seconds
Started Apr 16 02:21:02 PM PDT 24
Finished Apr 16 02:21:10 PM PDT 24
Peak memory 201980 kb
Host smart-94065b33-6e41-4c08-b1fd-9b7869315297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033982521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3033982521
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2404775972
Short name T649
Test name
Test status
Simulation time 4565841674 ps
CPU time 3.61 seconds
Started Apr 16 02:20:59 PM PDT 24
Finished Apr 16 02:21:04 PM PDT 24
Peak memory 202000 kb
Host smart-dcf39b14-829b-484b-b1f6-a5b3948bfab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404775972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2404775972
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2170110295
Short name T369
Test name
Test status
Simulation time 5574970703 ps
CPU time 6.66 seconds
Started Apr 16 02:21:00 PM PDT 24
Finished Apr 16 02:21:07 PM PDT 24
Peak memory 202016 kb
Host smart-481bb644-30b4-4aee-be85-d405caa713eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170110295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2170110295
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.586821967
Short name T39
Test name
Test status
Simulation time 209429240572 ps
CPU time 967.46 seconds
Started Apr 16 02:21:04 PM PDT 24
Finished Apr 16 02:37:13 PM PDT 24
Peak memory 218968 kb
Host smart-f258a37e-bff0-43ff-a1db-e29268caea3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586821967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.586821967
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.833552365
Short name T52
Test name
Test status
Simulation time 161685708164 ps
CPU time 235.92 seconds
Started Apr 16 02:21:00 PM PDT 24
Finished Apr 16 02:24:57 PM PDT 24
Peak memory 210916 kb
Host smart-4df256a6-aa7a-4f49-a977-6e11240712e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833552365 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.833552365
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.4116960690
Short name T578
Test name
Test status
Simulation time 527952405 ps
CPU time 1.88 seconds
Started Apr 16 02:21:04 PM PDT 24
Finished Apr 16 02:21:08 PM PDT 24
Peak memory 201932 kb
Host smart-20100aed-4567-4587-ab16-0779b11ed751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116960690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.4116960690
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.4133984699
Short name T60
Test name
Test status
Simulation time 175651295694 ps
CPU time 359.19 seconds
Started Apr 16 02:21:03 PM PDT 24
Finished Apr 16 02:27:03 PM PDT 24
Peak memory 202348 kb
Host smart-32a421d9-29f6-45db-b50f-3f4ddcb19071
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133984699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.4133984699
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3046009347
Short name T630
Test name
Test status
Simulation time 351387572560 ps
CPU time 448.39 seconds
Started Apr 16 02:21:01 PM PDT 24
Finished Apr 16 02:28:30 PM PDT 24
Peak memory 202260 kb
Host smart-3718c2ff-abe4-47b3-950a-aaef8133c287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046009347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3046009347
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2063332152
Short name T679
Test name
Test status
Simulation time 319898743722 ps
CPU time 752.55 seconds
Started Apr 16 02:21:05 PM PDT 24
Finished Apr 16 02:33:38 PM PDT 24
Peak memory 202296 kb
Host smart-b74ebaa5-5127-45b7-973e-ae48b6b7d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063332152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2063332152
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.416441652
Short name T690
Test name
Test status
Simulation time 484852165744 ps
CPU time 298.13 seconds
Started Apr 16 02:21:04 PM PDT 24
Finished Apr 16 02:26:02 PM PDT 24
Peak memory 202312 kb
Host smart-1380b893-27b9-4c48-9be6-425594f2f89c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=416441652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.416441652
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.4127642009
Short name T651
Test name
Test status
Simulation time 163761854465 ps
CPU time 182.35 seconds
Started Apr 16 02:21:03 PM PDT 24
Finished Apr 16 02:24:06 PM PDT 24
Peak memory 202244 kb
Host smart-27fd593f-baa5-46be-95b5-892798a5365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127642009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.4127642009
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1761189258
Short name T386
Test name
Test status
Simulation time 158362309583 ps
CPU time 341.62 seconds
Started Apr 16 02:21:03 PM PDT 24
Finished Apr 16 02:26:45 PM PDT 24
Peak memory 202220 kb
Host smart-6731c231-ad74-41f6-bc07-dbb86f61799b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761189258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1761189258
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3758218547
Short name T606
Test name
Test status
Simulation time 591187811439 ps
CPU time 1274.74 seconds
Started Apr 16 02:21:08 PM PDT 24
Finished Apr 16 02:42:24 PM PDT 24
Peak memory 202444 kb
Host smart-8c9eab57-873e-46d6-abf4-cbda6740baa9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758218547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3758218547
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1740248191
Short name T728
Test name
Test status
Simulation time 115197209781 ps
CPU time 578.88 seconds
Started Apr 16 02:21:04 PM PDT 24
Finished Apr 16 02:30:45 PM PDT 24
Peak memory 202560 kb
Host smart-f0ab5653-b26f-4d05-86b2-7ba858a504dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740248191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1740248191
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1806184774
Short name T419
Test name
Test status
Simulation time 25507556925 ps
CPU time 7.17 seconds
Started Apr 16 02:21:04 PM PDT 24
Finished Apr 16 02:21:11 PM PDT 24
Peak memory 202036 kb
Host smart-700292da-3241-49d0-85cb-3a572aa5a6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806184774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1806184774
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1479160423
Short name T407
Test name
Test status
Simulation time 3378099514 ps
CPU time 8.21 seconds
Started Apr 16 02:21:02 PM PDT 24
Finished Apr 16 02:21:11 PM PDT 24
Peak memory 202044 kb
Host smart-888b79df-6a3f-4d3e-a188-47806bccb464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479160423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1479160423
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2679676292
Short name T692
Test name
Test status
Simulation time 5830959920 ps
CPU time 4.32 seconds
Started Apr 16 02:21:04 PM PDT 24
Finished Apr 16 02:21:09 PM PDT 24
Peak memory 202076 kb
Host smart-43a029ce-066a-456b-bacd-9a7f940f0b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679676292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2679676292
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.122205748
Short name T471
Test name
Test status
Simulation time 153525980449 ps
CPU time 27.91 seconds
Started Apr 16 02:21:06 PM PDT 24
Finished Apr 16 02:21:35 PM PDT 24
Peak memory 210552 kb
Host smart-eb3a8394-6f43-440d-9dc1-03d6a452ef5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122205748 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.122205748
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.102017082
Short name T409
Test name
Test status
Simulation time 337484969 ps
CPU time 1.04 seconds
Started Apr 16 02:21:09 PM PDT 24
Finished Apr 16 02:21:10 PM PDT 24
Peak memory 201924 kb
Host smart-230c48bd-6944-4f91-9e6b-f6a7381da6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102017082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.102017082
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.161333163
Short name T306
Test name
Test status
Simulation time 327811208290 ps
CPU time 759.3 seconds
Started Apr 16 02:21:07 PM PDT 24
Finished Apr 16 02:33:47 PM PDT 24
Peak memory 202328 kb
Host smart-2be156f3-ee75-4127-8d9c-91f84ca81a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161333163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.161333163
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.280318254
Short name T271
Test name
Test status
Simulation time 327051135582 ps
CPU time 199.51 seconds
Started Apr 16 02:21:03 PM PDT 24
Finished Apr 16 02:24:23 PM PDT 24
Peak memory 202296 kb
Host smart-473fb248-cb44-483a-8579-f151e95c67a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280318254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.280318254
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.546030346
Short name T413
Test name
Test status
Simulation time 337101329113 ps
CPU time 154.22 seconds
Started Apr 16 02:21:07 PM PDT 24
Finished Apr 16 02:23:43 PM PDT 24
Peak memory 202216 kb
Host smart-4bead971-d89a-409d-86d1-a34dc17a090e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=546030346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.546030346
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.723483569
Short name T482
Test name
Test status
Simulation time 495021570603 ps
CPU time 565.55 seconds
Started Apr 16 02:21:04 PM PDT 24
Finished Apr 16 02:30:31 PM PDT 24
Peak memory 202240 kb
Host smart-980a205b-791d-485e-b251-4b156aceff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723483569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.723483569
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2612857429
Short name T388
Test name
Test status
Simulation time 491871696538 ps
CPU time 666.19 seconds
Started Apr 16 02:21:07 PM PDT 24
Finished Apr 16 02:32:15 PM PDT 24
Peak memory 202444 kb
Host smart-7652d02d-342f-44f2-a99a-0ff3e9014962
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612857429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2612857429
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2264487208
Short name T186
Test name
Test status
Simulation time 504874334818 ps
CPU time 303.48 seconds
Started Apr 16 02:21:17 PM PDT 24
Finished Apr 16 02:26:22 PM PDT 24
Peak memory 202324 kb
Host smart-d0d65716-0599-4af8-a1de-21722f4d2162
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264487208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2264487208
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.143119684
Short name T506
Test name
Test status
Simulation time 413616737278 ps
CPU time 927.03 seconds
Started Apr 16 02:21:09 PM PDT 24
Finished Apr 16 02:36:36 PM PDT 24
Peak memory 202260 kb
Host smart-0026c58a-c76c-4b0a-a9df-e797ddb6169f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143119684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.143119684
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1265406430
Short name T64
Test name
Test status
Simulation time 96690623594 ps
CPU time 379.26 seconds
Started Apr 16 02:21:07 PM PDT 24
Finished Apr 16 02:27:28 PM PDT 24
Peak memory 202536 kb
Host smart-68bf6624-30dc-4b06-a953-94bc0e290a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265406430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1265406430
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4293602824
Short name T399
Test name
Test status
Simulation time 26628946969 ps
CPU time 31.88 seconds
Started Apr 16 02:21:10 PM PDT 24
Finished Apr 16 02:21:43 PM PDT 24
Peak memory 202060 kb
Host smart-f6994fd7-522e-4986-aae4-969b8103289a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293602824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4293602824
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1161278307
Short name T600
Test name
Test status
Simulation time 3979462022 ps
CPU time 3.03 seconds
Started Apr 16 02:21:17 PM PDT 24
Finished Apr 16 02:21:21 PM PDT 24
Peak memory 202048 kb
Host smart-cfe9580d-585e-4e3b-a604-63b879b38bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161278307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1161278307
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3165381103
Short name T371
Test name
Test status
Simulation time 6081571976 ps
CPU time 4.29 seconds
Started Apr 16 02:21:05 PM PDT 24
Finished Apr 16 02:21:10 PM PDT 24
Peak memory 202108 kb
Host smart-823ee7b4-80ff-4edc-ad1f-68584b8e6129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165381103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3165381103
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.4174334363
Short name T222
Test name
Test status
Simulation time 9886467044 ps
CPU time 23.73 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:21:35 PM PDT 24
Peak memory 202392 kb
Host smart-9e9436cf-d5d2-4c71-9c93-a2a004c41e10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174334363 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.4174334363
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3545104215
Short name T546
Test name
Test status
Simulation time 438403361 ps
CPU time 0.85 seconds
Started Apr 16 02:21:10 PM PDT 24
Finished Apr 16 02:21:11 PM PDT 24
Peak memory 202004 kb
Host smart-0d9d15a1-fe31-4d41-bd35-bd942b5ca875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545104215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3545104215
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3426550473
Short name T604
Test name
Test status
Simulation time 339088160143 ps
CPU time 208.9 seconds
Started Apr 16 02:21:17 PM PDT 24
Finished Apr 16 02:24:47 PM PDT 24
Peak memory 202324 kb
Host smart-17683556-0308-4838-92e5-ee139de320ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426550473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3426550473
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.410651381
Short name T441
Test name
Test status
Simulation time 164073920816 ps
CPU time 60.41 seconds
Started Apr 16 02:21:15 PM PDT 24
Finished Apr 16 02:22:17 PM PDT 24
Peak memory 202176 kb
Host smart-c416b9b1-2292-4da0-894d-5127064d17c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410651381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.410651381
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1775797972
Short name T730
Test name
Test status
Simulation time 490751369704 ps
CPU time 637.87 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:31:50 PM PDT 24
Peak memory 202444 kb
Host smart-0c9c8fd7-1d85-4a1f-abb0-c6bf1beeb66e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775797972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1775797972
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.130767442
Short name T603
Test name
Test status
Simulation time 491424946169 ps
CPU time 1170.57 seconds
Started Apr 16 02:21:10 PM PDT 24
Finished Apr 16 02:40:42 PM PDT 24
Peak memory 202324 kb
Host smart-242e9f1e-cdf8-434a-ba01-a5761afe7c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130767442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.130767442
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2179863012
Short name T179
Test name
Test status
Simulation time 498422146117 ps
CPU time 149.81 seconds
Started Apr 16 02:21:14 PM PDT 24
Finished Apr 16 02:23:44 PM PDT 24
Peak memory 202236 kb
Host smart-ae9cef4f-0368-401f-9ca0-eb2b6c75a930
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179863012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2179863012
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3969322280
Short name T308
Test name
Test status
Simulation time 184652991362 ps
CPU time 389.11 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:27:41 PM PDT 24
Peak memory 202376 kb
Host smart-6d7e810f-7d8d-4aa3-954f-9303e1efaaa5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969322280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3969322280
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1924553378
Short name T633
Test name
Test status
Simulation time 208536812392 ps
CPU time 239.01 seconds
Started Apr 16 02:21:09 PM PDT 24
Finished Apr 16 02:25:09 PM PDT 24
Peak memory 202292 kb
Host smart-5a9ba6b6-d915-4f01-bb24-1461b644e259
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924553378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1924553378
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3853702307
Short name T63
Test name
Test status
Simulation time 100680920625 ps
CPU time 392.92 seconds
Started Apr 16 02:21:06 PM PDT 24
Finished Apr 16 02:27:40 PM PDT 24
Peak memory 202588 kb
Host smart-d8bab9a0-1a1a-4a00-aadf-24fa67557041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853702307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3853702307
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3664402744
Short name T664
Test name
Test status
Simulation time 35155507715 ps
CPU time 82.64 seconds
Started Apr 16 02:21:08 PM PDT 24
Finished Apr 16 02:22:31 PM PDT 24
Peak memory 202052 kb
Host smart-82c98bb8-2b1d-43a2-a504-70e2da5a82a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664402744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3664402744
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.338953154
Short name T422
Test name
Test status
Simulation time 4302435131 ps
CPU time 5.97 seconds
Started Apr 16 02:21:10 PM PDT 24
Finished Apr 16 02:21:17 PM PDT 24
Peak memory 202080 kb
Host smart-aa8653c4-7b3d-4875-b7dc-81b380ecc490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338953154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.338953154
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3796873566
Short name T557
Test name
Test status
Simulation time 5580460126 ps
CPU time 13.82 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:21:26 PM PDT 24
Peak memory 202308 kb
Host smart-30bebba3-f226-4e50-8ed5-3161e2cbeafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796873566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3796873566
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.779983837
Short name T22
Test name
Test status
Simulation time 96133786058 ps
CPU time 320.93 seconds
Started Apr 16 02:21:14 PM PDT 24
Finished Apr 16 02:26:36 PM PDT 24
Peak memory 210904 kb
Host smart-5062fcc1-2fca-47fb-a7ac-c550c5faaee5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779983837 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.779983837
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1110116524
Short name T702
Test name
Test status
Simulation time 506986108 ps
CPU time 0.96 seconds
Started Apr 16 02:21:12 PM PDT 24
Finished Apr 16 02:21:14 PM PDT 24
Peak memory 201884 kb
Host smart-4ce3eeee-66dc-446c-9be8-816e0e5101a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110116524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1110116524
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2653112696
Short name T644
Test name
Test status
Simulation time 326707969157 ps
CPU time 416.24 seconds
Started Apr 16 02:21:10 PM PDT 24
Finished Apr 16 02:28:07 PM PDT 24
Peak memory 202296 kb
Host smart-a9d15c5a-827d-41e8-be14-4f7131e55d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653112696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2653112696
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3641231039
Short name T123
Test name
Test status
Simulation time 167793636592 ps
CPU time 112.98 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:23:05 PM PDT 24
Peak memory 202232 kb
Host smart-28e61f91-d278-4d2e-92f6-82f84046fc84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641231039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3641231039
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3236889870
Short name T310
Test name
Test status
Simulation time 337347311512 ps
CPU time 48.75 seconds
Started Apr 16 02:21:10 PM PDT 24
Finished Apr 16 02:22:00 PM PDT 24
Peak memory 202260 kb
Host smart-0d231906-2655-4811-9f50-ed34c3edc04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236889870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3236889870
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1190237908
Short name T669
Test name
Test status
Simulation time 325152362258 ps
CPU time 740.39 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:33:33 PM PDT 24
Peak memory 202236 kb
Host smart-7172545e-b88f-4a09-b2e5-e158e10cc310
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190237908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1190237908
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2994271476
Short name T3
Test name
Test status
Simulation time 383840990037 ps
CPU time 823.4 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:34:55 PM PDT 24
Peak memory 202336 kb
Host smart-c3b4f576-00c3-45f1-90ff-0281663c14f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994271476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2994271476
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3784450385
Short name T171
Test name
Test status
Simulation time 199708245368 ps
CPU time 63.33 seconds
Started Apr 16 02:21:08 PM PDT 24
Finished Apr 16 02:22:12 PM PDT 24
Peak memory 202204 kb
Host smart-47f4598a-8195-4917-9db3-b859cca209d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784450385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3784450385
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.38781695
Short name T616
Test name
Test status
Simulation time 112030519712 ps
CPU time 430.67 seconds
Started Apr 16 02:21:14 PM PDT 24
Finished Apr 16 02:28:25 PM PDT 24
Peak memory 202644 kb
Host smart-736fd512-2ab9-4125-b10a-247874e87afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38781695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.38781695
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4018703201
Short name T387
Test name
Test status
Simulation time 23215005859 ps
CPU time 10.44 seconds
Started Apr 16 02:21:11 PM PDT 24
Finished Apr 16 02:21:23 PM PDT 24
Peak memory 202060 kb
Host smart-b178dbb1-0a90-432d-8480-aff453eed2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018703201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4018703201
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3861373173
Short name T716
Test name
Test status
Simulation time 3274362822 ps
CPU time 1.67 seconds
Started Apr 16 02:21:15 PM PDT 24
Finished Apr 16 02:21:18 PM PDT 24
Peak memory 202100 kb
Host smart-d8da1e09-d466-4477-8e36-0296c1fdbb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861373173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3861373173
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3788612465
Short name T461
Test name
Test status
Simulation time 5975292671 ps
CPU time 3.78 seconds
Started Apr 16 02:21:07 PM PDT 24
Finished Apr 16 02:21:11 PM PDT 24
Peak memory 202060 kb
Host smart-5530509f-a917-401e-9eb4-a5657dcd959b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788612465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3788612465
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.372325872
Short name T572
Test name
Test status
Simulation time 72535899971 ps
CPU time 442.44 seconds
Started Apr 16 02:21:15 PM PDT 24
Finished Apr 16 02:28:38 PM PDT 24
Peak memory 202560 kb
Host smart-2fb80667-efae-4f27-bf96-20eab78b1818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372325872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.372325872
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2715583444
Short name T15
Test name
Test status
Simulation time 47526104116 ps
CPU time 106.21 seconds
Started Apr 16 02:21:13 PM PDT 24
Finished Apr 16 02:23:00 PM PDT 24
Peak memory 210996 kb
Host smart-e00a7dc2-2c92-42f9-b71c-17f7d39ee179
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715583444 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2715583444
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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