Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7394	1			T1	5		T2	20		T3	7
testmodes[AdcCtrlTestmodeNormal]	5621	1			T1	5		T3	9		T4	1
testmodes[AdcCtrlTestmodeLowpower]	5880	1			T5	2		T7	2		T8	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4047	1			T1	1		T2	19		T3	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1843	1			T1	3		T3	3		T5	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1401	1			T14	16		T16	14		T40	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1799	1			T1	3		T3	3		T52	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2033	1			T1	2		T3	6		T6	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1452	1			T5	1		T14	23		T16	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1428	1			T5	1		T14	23		T16	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1413	1			T5	1		T7	1		T14	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2784	1			T7	1		T11	1		T14	13