Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23381

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3380

1

T5

3

T7

26

T10

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21047

1

T1

10

T2

20

T3

16

auto[1]

5714

1

T4

1

T6

3

T8

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	69	1			T22	4		T248	26		T183	21
values[1]	647	1			T10	1		T137	1		T138	11
values[2]	761	1			T32	23		T153	13		T49	12
values[3]	706	1			T4	1		T5	3		T138	3
values[4]	454	1			T146	1		T147	8		T151	14
values[5]	619	1			T138	11		T29	26		T31	12
values[6]	620	1			T7	9		T50	2		T139	15
values[7]	617	1			T10	5		T137	1		T30	1
values[8]	671	1			T139	16		T221	16		T160	23
values[9]	3608	1			T6	3		T7	35		T8	17
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	895	1			T10	1		T137	1		T138	11
values[1]	706	1			T4	1		T138	3		T49	12
values[2]	717	1			T40	3		T155	14		T146	1
values[3]	504	1			T5	3		T138	11		T139	32
values[4]	583	1			T31	12		T145	14		T49	8
values[5]	628	1			T7	9		T137	1		T50	1
values[6]	2776	1			T6	3		T8	17		T9	1
values[7]	654	1			T45	28		T33	1		T139	16
values[8]	1068	1			T7	35		T10	12		T137	9
values[9]	241	1			T167	20		T154	20		T212	21
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T138	1		T32	12		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	1		T137	1		T32	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T4	1		T138	1		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T150	38		T143	11		T175	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T40	3		T146	1		T147	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T155	1		T51	1		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T138	1		T139	15		T41	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	3		T158	1		T250	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T201	14		T251	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T31	1		T145	14		T49	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T137	1		T253	14		T175	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	6		T50	1		T29	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T6	3		T8	17		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T10	1		T145	11		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T33	1		T139	14		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T45	10		T142	1		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T7	9		T168	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T7	8		T10	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T154	9		T212	13		T51	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T167	11		T254	1		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T138	10		T32	11		T42	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T32	7		T153	5		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T138	2		T49	11		T208	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T143	10		T175	5		T255	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T256	11		T257	2		T258	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T155	13		T249	7		T259	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T138	10		T139	17		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T158	5		T250	13		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T260	2		T261	1		T262	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T31	11		T49	5		T159	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T253	8		T175	10		T190	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	3		T29	13		T139	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T110	22		T111	24		T263	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	4		T160	1		T213	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T139	2		T221	15		T160	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T45	18		T142	2		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	9		T168	9		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T7	9		T10	11		T137	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T154	11		T212	8		T51	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T167	9		T249	16		T189	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T22	3		T183	10		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T248	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T138	1		T33	1		T145	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	1		T137	1		T32	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T32	12		T49	1		T150	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T153	8		T150	21		T175	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T4	1		T138	1		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	3		T155	1		T150	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T146	1		T147	8		T151	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T158	1		T51	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T138	1		T139	15		T201	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	13		T31	1		T145	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T50	1		T253	14		T175	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	6		T50	1		T139	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T137	1		T30	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	1		T145	11		T265	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T139	14		T221	1		T160	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T160	1		T213	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1689	1			T6	3		T7	9		T8	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	466	1			T7	8		T10	1		T45	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T22	1		T183	11		T266	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T248	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T138	10		T177	11		T267	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T32	7		T17	1		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T32	11		T49	11		T208	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T153	5		T175	5		T268	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T138	2		T256	11		T269	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T155	13		T143	10		T249	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T270	11		T260	1		T86	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T158	5		T250	13		T106	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T138	10		T139	17		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	13		T31	11		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T253	8		T175	10		T190	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	3		T139	4		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T172	11		T153	8		T36	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	4		T161	8		T38	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T139	2		T221	15		T160	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T160	1		T213	6		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1114	1			T7	9		T110	22		T111	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T7	9		T10	11		T45	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T138	11		T32	12		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T10	1		T137	1		T32	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T4	1		T138	3		T49	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T150	2		T143	11		T175	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	3		T146	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T155	14		T51	1		T249	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T138	11		T139	18		T41	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	3		T158	6		T250	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T201	1		T251	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T31	12		T145	1		T49	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T137	1		T253	9		T175	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	4		T50	1		T29	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T6	3		T8	1		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	5		T145	1		T160	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T33	1		T139	3		T221	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T45	19		T142	3		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T7	10		T168	10		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T7	10		T10	12		T137	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T154	12		T212	9		T51	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T167	10		T254	1		T249	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T32	11		T145	12		T147	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T32	6		T153	7		T156	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T150	18		T208	14		T253	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T150	36		T143	10		T175	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T147	7		T265	3		T256	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T271	1		T272	13		T214	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T139	14		T41	1		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T250	14		T162	16		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T201	13		T260	7		T262	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T145	13		T49	2		T159	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T253	13		T175	12		T265	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	5		T29	12		T139	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T8	16		T11	19		T46	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T145	10		T265	13		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T139	13		T160	14		T143	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T45	9		T151	12		T159	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	8		T158	17		T273	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T7	7		T16	3		T34	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T154	8		T212	12		T51	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T167	10		T214	3		T274	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T22	2		T183	12		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T248	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T138	11		T33	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	1		T137	1		T32	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T32	12		T49	12		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T153	6		T150	1		T175	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	1		T138	3		T40	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	3		T155	14		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T146	1		T147	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T158	6		T51	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T138	11		T139	18		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	14		T31	12		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T50	1		T253	9		T175	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	4		T50	1		T139	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T137	1		T30	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	5		T145	1		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T139	3		T221	16		T160	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T160	2		T213	7		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T6	3		T7	10		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	421	1			T7	10		T10	12		T45	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T22	2		T183	9		T266	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T248	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T145	12		T147	11		T177	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T32	6		T156	5		T158	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T32	11		T150	18		T208	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T153	7		T150	20		T175	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T256	13		T163	17		T192	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T150	16		T143	10		T271	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T147	7		T151	13		T265	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T250	14		T106	11		T275	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T139	14		T201	13		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	12		T145	13		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T253	13		T175	12		T21	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	5		T139	10		T49	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T172	18		T153	2		T36	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T145	10		T265	13		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T139	13		T160	14		T272	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T151	12		T159	7		T276	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T7	8		T8	16		T11	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T7	7		T45	9		T16	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23428

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3333

1

T7

44

T137

11

T138

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21096

1

T1

10

T2

20

T3

16

auto[1]

5665

1

T4

1

T6

3

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	62	1			T40	3		T41	1		T81	11
values[1]	763	1			T30	1		T32	14		T139	32
values[2]	688	1			T10	1		T140	1		T49	12
values[3]	754	1			T5	3		T7	17		T50	1
values[4]	867	1			T7	9		T10	5		T45	28
values[5]	706	1			T137	1		T34	26		T139	15
values[6]	486	1			T138	11		T16	8		T213	7
values[7]	674	1			T10	12		T30	1		T33	1
values[8]	2632	1			T4	1		T6	3		T7	18
values[9]	1140	1			T137	9		T138	14		T50	1
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1041	1			T10	1		T30	1		T139	32
values[1]	675	1			T7	17		T31	12		T32	14
values[2]	702	1			T5	3		T50	1		T17	3
values[3]	858	1			T7	9		T10	5		T45	28
values[4]	675	1			T137	1		T138	11		T16	8
values[5]	593	1			T141	1		T142	3		T146	1
values[6]	2674	1			T4	1		T6	3		T8	17
values[7]	574	1			T7	18		T145	11		T153	3
values[8]	825	1			T137	9		T138	14		T50	1
values[9]	148	1			T153	13		T268	7		T277	2
minimum	17996	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T10	1		T30	1		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T139	15		T142	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T32	7		T160	15		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	8		T31	1		T139	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	3		T50	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T151	13		T158	18		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T10	1		T45	10		T29	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	6		T137	1		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T16	6		T213	1		T208	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T137	1		T138	1		T145	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T142	1		T146	1		T175	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T141	1		T253	16		T151	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T4	1		T6	3		T8	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T33	1		T167	11		T172	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T145	11		T153	1		T150	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	9		T154	9		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T138	1		T50	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T137	1		T138	1		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T153	8		T277	1		T278	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T268	1		T275	11		T279	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17855	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T140	1		T280	1		T185	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T41	1		T249	7		T267	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T139	17		T142	13		T155	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T32	7		T160	6		T49	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	9		T31	11		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T17	1		T143	10		T212	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T151	12		T158	12		T249	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T10	4		T45	18		T29	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	3		T153	8		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	2		T213	6		T208	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T138	10		T156	5		T273	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T142	2		T175	5		T256	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T253	15		T38	7		T20	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	871	1			T10	11		T110	22		T111	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T167	9		T172	11		T158	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T153	2		T51	10		T267	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	9		T154	11		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T138	2		T221	15		T160	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T137	8		T138	10		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T153	5		T277	1		T281	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T268	6		T275	12		T35	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T40	3		T41	1		T81	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T282	1		T283	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T30	1		T32	7		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T139	15		T140	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	1		T49	1		T143	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T140	1		T142	1		T175	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	3		T50	1		T29	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	8		T31	1		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	1		T45	10		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	6		T137	1		T36	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T34	15		T139	11		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T137	1		T145	14		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T16	6		T213	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T138	1		T151	14		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	1		T30	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T33	1		T172	19		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T4	1		T6	3		T8	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T7	9		T167	11		T154	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T138	1		T50	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T137	1		T138	1		T32	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T284	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T282	8		T283	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T32	7		T41	1		T161	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T139	17		T155	13		T285	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T49	11		T143	10		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T142	13		T175	10		T286	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	13		T160	6		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	9		T31	11		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T10	4		T45	18		T212	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	3		T36	2		T156	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T34	11		T139	4		T221	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T143	10		T273	1		T248	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T16	2		T213	6		T256	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T138	10		T38	7		T287	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T10	11		T142	2		T175	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T172	11		T253	15		T158	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T110	22		T111	24		T263	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T7	9		T167	9		T154	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T138	2		T221	15		T160	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T137	8		T138	10		T32	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2