Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23027

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3734

1

T4

1

T7

35

T45

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20622

1

T1

10

T2

20

T3

16

auto[1]

6139

1

T4

1

T6

3

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	229	1			T50	1		T142	17		T36	1
values[0]	66	1			T222	9		T299	12		T346	12
values[1]	640	1			T32	14		T139	16		T145	11
values[2]	860	1			T5	3		T138	11		T33	1
values[3]	622	1			T7	18		T10	1		T16	8
values[4]	530	1			T4	1		T137	1		T30	1
values[5]	2838	1			T6	3		T8	17		T9	1
values[6]	849	1			T7	9		T138	3		T31	12
values[7]	590	1			T137	9		T221	12		T145	13
values[8]	587	1			T7	17		T30	1		T139	32
values[9]	961	1			T10	5		T45	28		T137	1
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	686	1			T32	14		T153	3		T142	15
values[1]	695	1			T5	3		T7	18		T10	1
values[2]	636	1			T16	8		T29	26		T32	23
values[3]	2762	1			T4	1		T6	3		T8	17
values[4]	678	1			T10	12		T50	1		T139	15
values[5]	755	1			T7	9		T138	3		T31	12
values[6]	696	1			T7	17		T137	9		T139	32
values[7]	657	1			T10	5		T137	1		T30	1
values[8]	771	1			T45	28		T221	1		T160	21
values[9]	144	1			T138	11		T50	1		T142	14
minimum	18281	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T32	7		T153	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T156	6		T158	9		T159	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	3		T10	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	9		T138	1		T139	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T16	6		T221	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T29	13		T32	12		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1477	1			T6	3		T8	17		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	1		T30	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T10	1		T139	11		T150	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T50	1		T212	1		T265	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	6		T138	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T31	1		T256	14		T250	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T145	13		T49	3		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	8		T137	1		T139	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T10	1		T137	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T153	8		T143	4		T163	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T160	15		T213	1		T17	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T45	10		T221	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T138	1		T142	1		T296	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T50	1		T42	5		T254	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17922	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T145	11		T41	4		T143	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T32	7		T153	2		T142	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T156	5		T158	2		T159	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T168	9		T160	1		T259	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	9		T138	10		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T16	2		T221	15		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T29	13		T32	11		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T110	22		T111	24		T263	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T34	11		T49	11		T285	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	11		T139	4		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T212	4		T256	12		T260	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	3		T138	2		T273	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T31	11		T256	11		T250	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T49	5		T253	15		T249	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	9		T137	8		T139	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	4		T167	9		T172	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T153	5		T143	4		T181	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T160	6		T213	6		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T45	18		T36	2		T267	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T138	10		T142	13		T296	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T42	4		T189	8		T347	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T16	1		T69	1		T36	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T41	1		T143	10		T208	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T142	2		T195	1		T286	21
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T50	1		T36	1		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T222	3		T299	12		T346	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T32	7		T255	1		T302	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T139	14		T145	11		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	3		T33	1		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T138	1		T40	3		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	1		T16	6		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	9		T29	13		T150	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T137	1		T146	1		T175	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	1		T30	1		T32	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T6	3		T8	17		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T50	1		T34	15		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	6		T138	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T31	1		T254	1		T256	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T145	13		T49	3		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T137	1		T221	1		T151	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T30	1		T167	11		T253	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	8		T139	15		T153	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T10	1		T137	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T45	10		T221	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T142	15		T286	15		T78	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T269	10		T295	6		T332	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T222	6		T301	10		T348	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T32	7		T255	9		T302	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T139	2		T41	1		T143	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T168	9		T160	1		T153	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T138	10		T153	8		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T16	2		T221	15		T155	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	9		T29	13		T212	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T175	5		T256	10		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T32	11		T49	11		T285	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T10	11		T110	22		T111	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	11		T212	4		T256	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	3		T138	2		T151	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T31	11		T256	11		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T49	5		T253	15		T249	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T137	8		T221	11		T159	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T167	9		T253	8		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	9		T139	17		T153	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	4		T138	10		T172	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T45	18		T36	2		T42	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T32	8		T153	3		T142	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T156	6		T158	3		T159	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T5	3		T10	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	10		T138	11		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T16	5		T221	16		T155	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T29	14		T32	12		T153	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T6	3		T8	1		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	1		T30	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	12		T139	5		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T50	1		T212	5		T265	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	4		T138	3		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T31	12		T256	12		T250	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T145	1		T49	6		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	10		T137	9		T139	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	5		T137	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T153	6		T143	5		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T160	7		T213	7		T17	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T45	19		T221	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T138	11		T142	14		T296	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T50	1		T42	6		T254	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18038	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T145	1		T41	4		T143	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T32	6		T292	7		T161	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T156	5		T158	8		T159	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T145	13		T201	13		T265	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	8		T139	13		T154	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	3		T150	20		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T29	12		T32	11		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T8	16		T11	19		T46	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T34	14		T157	9		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T139	10		T150	18		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T265	9		T256	13		T192	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T7	5		T273	9		T292	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T256	13		T250	14		T180	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T145	12		T49	2		T253	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	7		T139	14		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T167	10		T172	18		T253	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T153	7		T143	3		T163	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T160	14		T215	14		T286	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T45	9		T36	9		T267	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T274	10		T284	18		T297	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T42	3		T189	3		T347	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T222	2		T295	8		T299	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T145	10		T41	1		T143	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T142	17		T195	1		T286	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T50	1		T36	1		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T222	7		T299	1		T346	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T32	8		T255	10		T302	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T139	3		T145	1		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	3		T33	1		T168	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T138	11		T40	3		T153	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	1		T16	5		T221	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	10		T29	14		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T137	1		T146	1		T175	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	1		T30	1		T32	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T6	3		T8	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T50	1		T34	12		T212	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	4		T138	3		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T31	12		T254	1		T256	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T145	1		T49	6		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T137	9		T221	12		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	1		T167	10		T253	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	10		T139	18		T153	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T10	5		T137	1		T138	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T45	19		T221	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T286	19		T274	10		T24	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T269	12		T295	6		T332	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T222	2		T299	11		T346	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T32	6		T302	10		T295	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T139	13		T145	10		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T201	13		T265	13		T292	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T153	2		T154	8		T51	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T16	3		T145	13		T150	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	8		T29	12		T150	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T175	6		T256	10		T161	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T32	11		T157	9		T163	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T8	16		T11	19		T46	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T34	14		T265	9		T256	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	5		T151	12		T273	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T256	13		T250	14		T180	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T145	12		T49	2		T253	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T151	13		T159	6		T81	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T167	10		T253	13		T151	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T7	7		T139	14		T153	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T172	18		T160	14		T265	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T45	9		T36	9		T42	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19