Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23403

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3358

1

T4

1

T10

13

T45

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21090

1

T1

10

T2

20

T3

16

auto[1]

5671

1

T4

1

T5

3

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T146	1		T42	9		-	-
values[0]	100	1			T81	13		T349	25		T309	6
values[1]	888	1			T4	1		T7	17		T138	3
values[2]	802	1			T138	11		T139	16		T153	13
values[3]	581	1			T137	9		T139	15		T153	11
values[4]	534	1			T137	1		T29	26		T33	1
values[5]	2686	1			T6	3		T8	17		T9	1
values[6]	749	1			T50	1		T32	14		T172	30
values[7]	763	1			T7	9		T10	13		T138	11
values[8]	574	1			T45	28		T16	8		T30	1
values[9]	1085	1			T5	3		T7	18		T31	12
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1040	1			T4	1		T7	17		T138	3
values[1]	739	1			T138	11		T153	24		T141	1
values[2]	659	1			T137	9		T33	1		T139	31
values[3]	2699	1			T6	3		T8	17		T9	1
values[4]	677	1			T10	5		T137	1		T50	1
values[5]	610	1			T138	11		T50	1		T145	13
values[6]	815	1			T7	9		T10	13		T45	28
values[7]	586	1			T30	1		T33	1		T139	32
values[8]	759	1			T5	3		T7	18		T31	12
values[9]	151	1			T42	9		T267	19		T322	1
minimum	18026	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T7	8		T138	1		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T4	1		T30	1		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T153	3		T250	15		T286	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T138	1		T153	8		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T137	1		T139	11		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T33	1		T139	14		T201	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T6	3		T8	17		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T145	11		T140	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	1		T137	1		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T32	7		T172	19		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T145	13		T143	11		T175	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	1		T50	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	6		T16	6		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T10	2		T45	10		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T30	1		T153	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T33	1		T139	15		T145	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	3		T7	9		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T168	1		T154	9		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T267	10		T322	1		T278	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T42	5		T181	1		T329	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17862	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T292	8		T255	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	9		T138	2		T221	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T221	15		T213	6		T212	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T153	8		T250	13		T286	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T138	10		T153	5		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T137	8		T139	4		T43	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T139	2		T158	12		T277	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T110	22		T111	24		T263	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T253	8		T161	8		T306	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	4		T34	11		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T32	7		T172	11		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T143	10		T175	10		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	10		T160	1		T49	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	3		T16	2		T142	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	11		T45	18		T32	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T153	2		T159	8		T337	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T139	17		T51	10		T215	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	9		T31	11		T155	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T168	9		T154	11		T142	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T267	9		T321	4		T166	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T42	4		T181	11		T335	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	1		T69	1		T36	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T255	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T146	1		T42	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T349	16		T204	19		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T81	13		T309	1		T334	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T7	8		T138	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	1		T30	1		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T150	17		T222	3		T286	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T138	1		T139	14		T153	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T137	1		T139	11		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T201	14		T146	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T137	1		T29	13		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T33	1		T36	1		T253	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T6	3		T8	17		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T145	11		T140	1		T161	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T145	13		T143	11		T175	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	1		T32	7		T172	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	6		T142	2		T292	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	2		T138	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	6		T30	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	10		T32	12		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T5	3		T7	9		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T139	15		T168	1		T154	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T42	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T349	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T309	5		T334	4		T350	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	9		T138	2		T221	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T221	15		T213	6		T156	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T222	6		T286	8		T82	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T138	10		T139	2		T153	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T137	8		T139	4		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T44	4		T277	6		T290	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T29	13		T189	1		T164	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T253	8		T306	13		T278	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T10	4		T110	22		T111	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T161	8		T189	1		T259	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T143	10		T175	10		T177	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T32	7		T172	11		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	3		T142	15		T255	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	11		T138	10		T160	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T16	2		T159	8		T189	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T45	18		T32	11		T159	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	9		T31	11		T153	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T139	17		T168	9		T154	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	10		T138	3		T221	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T4	1		T30	1		T40	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T153	9		T250	14		T286	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T138	11		T153	6		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T137	9		T139	5		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T33	1		T139	3		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T6	3		T8	1		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T145	1		T140	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T10	5		T137	1		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T32	8		T172	12		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T145	1		T143	11		T175	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T138	11		T50	1		T160	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	4		T16	5		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T10	13		T45	19		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T30	1		T153	3		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T33	1		T139	18		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	3		T7	10		T31	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T168	10		T154	12		T142	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T267	10		T322	1		T278	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T42	6		T181	12		T329	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17999	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T292	1		T255	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T7	7		T160	14		T150	36
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T212	12		T156	5		T151	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T153	2		T250	14		T286	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T153	7		T147	7		T157	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T139	10		T43	4		T267	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T139	13		T201	13		T158	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T8	16		T11	19		T46	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T145	10		T253	13		T265	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T34	14		T167	10		T151	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T32	6		T172	18		T180	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T145	12		T143	10		T175	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T41	1		T175	6		T165	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	5		T16	3		T265	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T45	9		T32	11		T36	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T159	6		T272	2		T337	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T139	14		T145	13		T51	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	8		T150	18		T143	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T154	8		T159	7		T162	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T267	9		T278	2		T166	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T42	3		T329	11		T339	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T281	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T292	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T146	1		T42	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T349	10		T204	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T81	1		T309	6		T334	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T7	10		T138	3		T221	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T4	1		T30	1		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T150	1		T222	7		T286	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T138	11		T139	3		T153	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T137	9		T139	5		T153	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T201	1		T146	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T137	1		T29	14		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T33	1		T36	1		T253	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T6	3		T8	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T145	1		T140	1		T161	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T145	1		T143	11		T175	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T50	1		T32	8		T172	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	4		T142	17		T292	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	13		T138	11		T160	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T16	5		T30	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T45	19		T32	12		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T5	3		T7	10		T31	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T139	18		T168	10		T154	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T42	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T349	15		T204	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T81	12		T334	2		T350	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	7		T160	14		T150	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T156	5		T151	12		T256	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T150	16		T222	2		T286	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T139	13		T153	7		T147	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T139	10		T153	2		T43	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T201	13		T44	4		T277	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T29	12		T147	11		T271	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T253	13		T265	9		T272	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1140	1			T8	16		T11	19		T46	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T145	10		T161	11		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T145	12		T143	10		T175	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T32	6		T172	18		T36	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	5		T292	10		T192	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T208	14		T265	3		T19	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	3		T265	13		T159	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	9		T32	11		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	8		T150	18		T143	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T139	14		T154	8		T162	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19