Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21348

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

5413

1

T6

3

T7

17

T8

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20936

1

T1

10

T2

20

T3

16

auto[1]

5825

1

T6

3

T7

26

T8

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	191	1			T10	5		T33	1		T145	11
values[0]	23	1			T18	1		T197	1		T304	14
values[1]	507	1			T7	18		T137	10		T31	12
values[2]	654	1			T5	3		T50	1		T33	1
values[3]	612	1			T16	8		T30	1		T34	26
values[4]	906	1			T10	12		T138	11		T139	32
values[5]	581	1			T32	14		T221	12		T153	3
values[6]	747	1			T4	1		T138	3		T30	1
values[7]	637	1			T7	9		T10	1		T45	28
values[8]	741	1			T7	17		T29	26		T49	20
values[9]	3173	1			T6	3		T8	17		T9	1
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	520	1			T7	18		T137	10		T50	1
values[1]	2875	1			T5	3		T6	3		T8	17
values[2]	637	1			T16	8		T34	26		T153	11
values[3]	876	1			T10	12		T138	11		T139	32
values[4]	498	1			T4	1		T32	37		T167	20
values[5]	851	1			T45	28		T138	3		T30	1
values[6]	595	1			T7	9		T10	1		T138	11
values[7]	768	1			T7	17		T139	15		T153	13
values[8]	879	1			T137	1		T50	1		T33	1
values[9]	132	1			T10	5		T33	1		T140	1
minimum	18130	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	9		T145	13		T160	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T137	2		T50	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	3		T30	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1491	1			T6	3		T8	17		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T16	6		T34	15		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T212	13		T182	1		T351	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T138	1		T139	15		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T10	1		T253	16		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	1		T32	7		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T32	12		T167	11		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T30	1		T172	19		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T45	10		T138	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	6		T138	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	1		T29	13		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T139	11		T153	8		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	8		T49	1		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T33	1		T213	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T137	1		T50	1		T139	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T10	1		T33	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T140	1		T150	17		T159	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17873	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T322	1		T328	17		T197	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T7	9		T160	6		T143	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T137	8		T142	13		T181	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T221	15		T41	1		T249	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	955	1			T110	22		T111	24		T263	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	2		T34	11		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T212	8		T306	13		T214	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T138	10		T139	17		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	11		T253	15		T158	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T32	7		T143	10		T255	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T32	11		T167	9		T221	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T172	11		T208	2		T285	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T45	18		T138	2		T168	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T7	3		T138	10		T142	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	13		T51	10		T256	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T139	4		T153	5		T49	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T7	9		T49	11		T256	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T213	6		T155	13		T36	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T139	2		T142	14		T159	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T10	4		T260	2		T86	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T159	7		T20	1		T183	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	1		T31	11		T69	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T328	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T10	1		T33	1		T147	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T145	11		T141	1		T150	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T18	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T197	1		T304	14		T305	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	9		T31	1		T145	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T137	2		T142	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	3		T33	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T50	1		T160	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T16	6		T30	1		T34	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T182	1		T276	12		T308	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T138	1		T139	15		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T10	1		T212	13		T253	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T32	7		T153	1		T143	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T221	1		T44	8		T268	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T30	1		T172	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T138	1		T32	12		T167	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	6		T138	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	1		T45	10		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T49	3		T36	1		T150	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	8		T29	13		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T33	1		T139	11		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1628	1			T6	3		T8	17		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T10	4		T260	2		T296	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T159	7		T257	2		T352	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T7	9		T31	11		T160	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T137	8		T142	13		T286	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T221	15		T41	1		T143	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T160	1		T43	8		T38	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T16	2		T34	11		T253	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T269	10		T307	2		T275	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T138	10		T139	17		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T10	11		T212	8		T253	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T32	7		T153	2		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T221	11		T44	4		T268	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T172	11		T208	2		T255	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T138	2		T32	11		T167	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T138	10		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T45	18		T17	1		T51	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	5		T175	5		T164	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	9		T29	13		T49	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T139	4		T213	6		T153	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1040	1			T110	22		T111	24		T263	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T7	10		T145	1		T160	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T137	10		T50	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T5	3		T30	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1282	1			T6	3		T8	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	5		T34	12		T153	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T212	9		T182	1		T351	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T138	11		T139	18		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T10	12		T253	16		T158	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T4	1		T32	8		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T32	12		T167	10		T221	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T30	1		T172	12		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T45	19		T138	3		T168	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	4		T138	11		T142	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	1		T29	14		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T139	5		T153	6		T49	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	10		T49	12		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T33	1		T213	7		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T137	1		T50	1		T139	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T10	5		T33	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T140	1		T150	1		T159	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18023	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T322	1		T328	10		T197	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	8		T145	12		T160	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T162	16		T21	3		T307	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T41	1		T161	11		T215	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1164	1			T8	16		T11	19		T46	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T16	3		T34	14		T153	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T212	12		T308	2		T214	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T139	14		T154	8		T150	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T253	15		T177	21		T44	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T32	6		T143	10		T292	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T32	11		T167	10		T268	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T172	18		T208	14		T277	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T45	9		T143	10		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	5		T175	6		T158	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T29	12		T51	10		T256	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T139	10		T153	7		T49	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T7	7		T256	13		T19	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T36	9		T147	7		T156	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T139	13		T145	23		T159	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T260	7		T272	13		T353	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T150	16		T159	7		T20	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T277	5		T354	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T328	16		T304	13		T346	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T10	5		T33	1		T147	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T145	1		T141	1		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T18	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T197	1		T304	1		T305	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	10		T31	12		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T137	10		T142	14		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	3		T33	1		T221	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T50	1		T160	2		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T16	5		T30	1		T34	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T182	1		T276	1		T308	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T138	11		T139	18		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T10	12		T212	9		T253	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T32	8		T153	3		T143	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T221	12		T44	8		T268	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	1		T30	1		T172	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T138	3		T32	12		T167	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	4		T138	11		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	1		T45	19		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T49	6		T36	1		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	10		T29	14		T49	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T33	1		T139	5		T213	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1395	1			T6	3		T8	1		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T147	7		T260	7		T353	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T145	10		T150	16		T159	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T304	13		T305	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	8		T145	12		T160	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T162	16		T307	10		T286	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T41	1		T143	3		T215	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T43	4		T38	7		T21	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T16	3		T34	14		T253	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T276	11		T308	2		T269	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T139	14		T153	2		T154	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T212	12		T253	15		T177	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T32	6		T143	10		T292	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T44	4		T106	16		T295	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T172	18		T208	14		T277	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T32	11		T167	10		T143	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	5		T158	25		T267	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T45	9		T51	10		T256	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	2		T150	18		T175	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	7		T29	12		T256	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T139	10		T153	7		T36	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1273	1			T8	16		T11	19		T46	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19