Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23219

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3542

1

T4

1

T10

17

T137

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21295

1

T1

10

T2

20

T3

16

auto[1]

5466

1

T5

3

T6

3

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	40	1			T146	1		T355	11		T356	11
values[0]	44	1			T161	22		T335	7		T357	15
values[1]	742	1			T10	5		T138	11		T145	14
values[2]	2882	1			T6	3		T7	18		T8	17
values[3]	847	1			T10	12		T137	9		T138	3
values[4]	454	1			T4	1		T33	1		T221	1
values[5]	585	1			T33	2		T168	10		T153	11
values[6]	559	1			T7	17		T50	1		T30	1
values[7]	725	1			T137	1		T29	26		T30	1
values[8]	641	1			T10	1		T142	3		T36	12
values[9]	1253	1			T5	3		T7	9		T45	28
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	962	1			T7	18		T10	5		T138	22
values[1]	2951	1			T6	3		T8	17		T9	1
values[2]	641	1			T137	9		T138	3		T49	8
values[3]	484	1			T4	1		T33	2		T168	10
values[4]	653	1			T30	1		T31	12		T33	1
values[5]	570	1			T7	17		T137	1		T50	1
values[6]	721	1			T40	3		T167	20		T142	3
values[7]	576	1			T10	1		T29	26		T154	20
values[8]	920	1			T5	3		T7	9		T45	28
values[9]	282	1			T50	1		T32	14		T213	7
minimum	18001	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T7	9		T221	1		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T10	1		T138	2		T145	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T6	3		T8	17		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	1		T32	12		T139	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T137	1		T138	1		T49	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T36	1		T253	14		T151	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T33	1		T221	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	1		T33	1		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T30	1		T31	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T33	1		T153	3		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	8		T137	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T50	1		T221	1		T160	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T36	10		T156	6		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T40	3		T167	11		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	1		T147	8		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T29	13		T154	9		T175	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	3		T7	6		T45	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T137	1		T16	6		T34	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T32	7		T213	1		T150	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T50	1		T146	2		T302	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17854	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T358	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	9		T221	11		T153	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	4		T138	20		T142	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T110	22		T111	24		T263	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	11		T32	11		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T137	8		T138	2		T49	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T253	8		T273	1		T267	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T153	2		T41	1		T44	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T168	9		T19	4		T268	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T31	11		T143	4		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T153	8		T17	1		T158	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	9		T139	17		T222	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T221	15		T160	6		T175	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T36	2		T156	5		T249	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T167	9		T142	2		T212	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T249	2		T270	11		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	13		T154	11		T175	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	3		T45	18		T273	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T16	2		T34	11		T158	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T32	7		T213	6		T255	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T302	11		T215	14		T323	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	1		T69	1		T36	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T355	1		T344	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T146	1		T356	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T161	12		T357	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T335	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T153	8		T201	14		T42	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T10	1		T138	1		T145	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T6	3		T7	9		T8	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T138	1		T172	19		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T137	1		T138	1		T49	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T10	1		T32	12		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T33	1		T221	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	1		T253	14		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T150	19		T143	4		T158	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T33	2		T168	1		T153	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T7	8		T30	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T50	1		T167	11		T160	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T137	1		T30	1		T139	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T29	13		T40	3		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	1		T36	10		T147	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T142	1		T285	1		T151	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	3		T7	6		T45	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	417	1			T137	1		T50	1		T16	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T355	10		T344	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T356	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T161	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T335	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T153	5		T42	4		T51	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	4		T138	10		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T7	9		T110	22		T111	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T138	10		T172	11		T160	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T137	8		T138	2		T49	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	11		T32	11		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T153	2		T142	13		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T253	8		T158	5		T19	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T143	4		T158	12		T44	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T168	9		T153	8		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T7	9		T31	11		T248	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T167	9		T160	6		T43	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T139	17		T156	5		T222	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	13		T221	15		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T36	2		T249	16		T267	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T142	2		T285	12		T151	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	3		T45	18		T32	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T16	2		T34	11		T175	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	10		T221	12		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T10	5		T138	22		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T6	3		T8	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	12		T32	12		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	9		T138	3		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T36	1		T253	9		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T33	1		T221	1		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T4	1		T33	1		T168	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	1		T31	12		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T33	1		T153	9		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	10		T137	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T50	1		T221	16		T160	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T36	3		T156	6		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	3		T167	10		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	1		T147	1		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T29	14		T154	12		T175	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	3		T7	4		T45	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T137	1		T16	5		T34	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T32	8		T213	7		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T50	1		T146	2		T302	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17996	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T358	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	8		T153	7		T201	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T145	13		T253	15		T151	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T8	16		T11	19		T46	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T32	11		T139	13		T172	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T49	2		T147	11		T159	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T253	13		T151	13		T267	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T41	1		T44	4		T286	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T265	9		T19	4		T277	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T150	18		T143	3		T158	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T153	2		T43	4		T250	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T7	7		T139	14		T222	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T160	14		T150	20		T175	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T36	9		T156	5		T267	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T167	10		T212	12		T256	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T147	7		T161	11		T21	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T29	12		T154	8		T175	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	5		T45	9		T145	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T16	3		T34	14		T145	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T32	6		T150	16		T79	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T302	10		T215	16		T299	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T358	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T355	11		T344	8		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T146	1		T356	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T161	11		T357	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T335	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T153	6		T201	1		T42	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	5		T138	11		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T6	3		T7	10		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	11		T172	12		T160	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T137	9		T138	3		T49	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	12		T32	12		T139	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T33	1		T221	1		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	1		T253	9		T158	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T150	1		T143	5		T158	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T33	2		T168	10		T153	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T7	10		T30	1		T31	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T50	1		T167	10		T160	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T137	1		T30	1		T139	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T29	14		T40	3		T221	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	1		T36	3		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T142	3		T285	13		T151	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T5	3		T7	4		T45	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	402	1			T137	1		T50	1		T16	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T344	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T356	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T161	11		T357	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T153	7		T201	13		T42	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T145	13		T253	15		T151	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T7	8		T8	16		T11	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T172	18		T157	9		T265	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T49	2		T143	10		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T32	11		T139	13		T208	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T41	1		T286	11		T24	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T253	13		T19	4		T259	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T150	18		T143	3		T158	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T153	2		T265	9		T165	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T7	7		T248	12		T315	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T167	10		T160	14		T43	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T139	14		T156	5		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	12		T154	8		T150	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T36	9		T147	7		T267	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T151	12		T159	6		T180	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	5		T45	9		T32	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T16	3		T34	14		T145	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19