Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23276

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3485

1

T5

3

T7

9

T10

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21339

1

T1

10

T2

20

T3

16

auto[1]

5422

1

T6

3

T7

17

T8

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	165	1			T40	3		T154	20		T142	14
values[0]	49	1			T248	19		T321	5		T326	21
values[1]	693	1			T10	12		T45	28		T138	11
values[2]	493	1			T4	1		T5	3		T10	6
values[3]	687	1			T29	26		T139	15		T172	30
values[4]	2881	1			T6	3		T7	9		T8	17
values[5]	813	1			T16	8		T167	20		T221	1
values[6]	711	1			T7	18		T137	1		T138	11
values[7]	808	1			T7	17		T137	1		T32	23
values[8]	560	1			T138	3		T50	1		T32	14
values[9]	912	1			T137	9		T33	1		T145	14
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	574	1			T45	28		T138	11		T31	12
values[1]	601	1			T4	1		T5	3		T10	6
values[2]	727	1			T29	26		T172	30		T150	19
values[3]	2737	1			T6	3		T7	9		T8	17
values[4]	866	1			T7	18		T16	8		T167	20
values[5]	772	1			T7	17		T137	2		T138	11
values[6]	617	1			T32	23		T33	1		T34	26
values[7]	684	1			T138	3		T50	1		T32	14
values[8]	830	1			T137	9		T33	1		T145	14
values[9]	89	1			T40	3		T270	12		T322	1
minimum	18264	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T31	1		T33	1		T145	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T45	10		T138	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	1		T10	2		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	3		T139	11		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T29	13		T150	19		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T172	19		T143	11		T285	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T6	3		T8	17		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	6		T145	11		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T7	9		T16	6		T151	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T167	11		T140	1		T153	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	8		T137	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T50	1		T30	1		T139	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T17	2		T141	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T32	12		T33	1		T34	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T138	1		T32	7		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T50	1		T153	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T145	14		T160	15		T150	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T137	1		T33	1		T154	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T270	1		T289	12		T269	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T40	3		T322	1		T296	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17961	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T10	1		T215	10		T359	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T31	11		T253	23		T164	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T45	18		T138	10		T155	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T10	4		T168	9		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T139	4		T160	1		T256	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T29	13		T249	16		T250	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T172	11		T143	10		T285	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T110	22		T111	24		T263	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	3		T143	10		T212	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	9		T16	2		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T167	9		T153	8		T267	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	9		T138	10		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T139	17		T49	5		T249	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T17	1		T151	12		T42	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T32	11		T34	11		T221	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T138	2		T32	7		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T153	2		T49	11		T51	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T160	6		T159	8		T255	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T137	8		T154	11		T142	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T270	11		T289	12		T269	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T16	1		T213	6		T142	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T10	11		T215	7		T198	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T159	7		T255	1		T252	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T40	3		T154	9		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T248	12		T321	1		T326	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T264	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T31	1		T33	1		T145	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	1		T45	10		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	1		T10	2		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	3		T160	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T29	13		T146	1		T175	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T139	11		T172	19		T285	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T6	3		T8	17		T9	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	6		T145	11		T143	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T16	6		T221	1		T151	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T167	11		T140	1		T153	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	9		T137	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T50	1		T30	1		T139	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	8		T137	1		T17	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T32	12		T33	1		T34	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T138	1		T32	7		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	1		T49	1		T150	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T145	14		T160	15		T150	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T137	1		T33	1		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T159	8		T255	6		T316	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T154	11		T142	13		T315	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T248	7		T321	4		T326	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T31	11		T213	6		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	11		T45	18		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T10	4		T168	9		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T160	1		T155	13		T255	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T29	13		T175	5		T249	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T139	4		T172	11		T285	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T110	22		T111	24		T263	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	3		T143	20		T212	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T16	2		T151	9		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T167	9		T153	8		T267	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	9		T138	10		T139	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T139	17		T49	5		T249	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	9		T17	1		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T32	11		T34	11		T221	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T138	2		T32	7		T221	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T49	11		T189	9		T262	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T160	6		T270	11		T19	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T137	8		T153	2		T208	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T31	12		T33	1		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T45	19		T138	11		T155	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T4	1		T10	6		T168	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	3		T139	5		T160	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T29	14		T150	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T172	12		T143	11		T285	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T6	3		T8	1		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	4		T145	1		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	10		T16	5		T151	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T167	10		T140	1		T153	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	10		T137	2		T138	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T50	1		T30	1		T139	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T17	3		T141	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T32	12		T33	1		T34	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T138	3		T32	8		T221	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T50	1		T153	3		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T145	1		T160	7		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T137	9		T33	1		T154	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T270	12		T289	13		T269	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T40	3		T322	1		T296	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18076	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T10	12		T215	8		T359	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T145	12		T253	28		T162	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T45	9		T151	13		T265	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T41	1		T175	6		T267	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T139	10		T147	7		T256	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T29	12		T150	18		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T172	18		T143	10		T161	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T8	16		T11	19		T46	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	5		T145	10		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	8		T16	3		T151	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T167	10		T153	2		T267	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	7		T139	13		T267	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T139	14		T49	2		T262	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T151	12		T42	3		T44	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T32	11		T34	14		T159	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T32	6		T153	7		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T150	20		T51	10		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T145	13		T160	14		T150	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T154	8		T201	13		T208	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T289	11		T269	12		T304	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T329	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T163	14		T248	23		T284	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T215	9		T198	10		T360	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T159	9		T255	7		T252	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T40	3		T154	12		T142	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T248	8		T321	5		T326	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T264	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T31	12		T33	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	12		T45	19		T138	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	1		T10	6		T168	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	3		T160	2		T155	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T29	14		T146	1		T175	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T139	5		T172	12		T285	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T6	3		T8	1		T9	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	4		T145	1		T143	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T16	5		T221	1		T151	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T167	10		T140	1		T153	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	10		T137	1		T138	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T50	1		T30	1		T139	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	10		T137	1		T17	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T32	12		T33	1		T34	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T138	3		T32	8		T221	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T50	1		T49	12		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T145	1		T160	7		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T137	9		T33	1		T153	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T159	6		T304	3		T358	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T154	8		T315	4		T361	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T248	11		T326	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T145	12		T253	28		T162	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T45	9		T265	3		T276	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T41	1		T267	8		T318	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T147	7		T151	13		T292	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T29	12		T175	6		T308	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T139	10		T172	18		T256	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T8	16		T11	19		T46	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	5		T145	10		T143	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T16	3		T151	10		T177	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T167	10		T153	2		T267	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	8		T139	13		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T139	14		T49	2		T268	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	7		T151	12		T42	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T32	11		T34	14		T159	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T32	6		T153	7		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T150	20		T189	3		T22	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T145	13		T160	14		T150	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T201	13		T208	14		T265	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19