Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23245

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3516

1

T4

1

T10

17

T137

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21344

1

T1

10

T2

20

T3

16

auto[1]

5417

1

T5

3

T6

3

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	318	1			T34	26		T213	7		T146	1
values[0]	24	1			T161	22		T35	1		T199	1
values[1]	725	1			T10	5		T138	11		T145	14
values[2]	2964	1			T6	3		T7	18		T8	17
values[3]	736	1			T10	12		T137	9		T138	3
values[4]	514	1			T4	1		T33	1		T221	1
values[5]	601	1			T33	2		T168	10		T153	11
values[6]	541	1			T7	17		T137	1		T50	1
values[7]	725	1			T30	1		T139	32		T40	3
values[8]	634	1			T10	1		T29	26		T154	20
values[9]	990	1			T5	3		T7	9		T45	28
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	785	1			T7	18		T10	5		T138	22
values[1]	2865	1			T6	3		T8	17		T9	1
values[2]	618	1			T137	9		T138	3		T49	8
values[3]	529	1			T4	1		T33	1		T168	10
values[4]	712	1			T7	17		T31	12		T33	2
values[5]	519	1			T137	1		T50	1		T30	2
values[6]	772	1			T29	26		T139	32		T40	3
values[7]	498	1			T10	1		T154	20		T147	8
values[8]	1063	1			T5	3		T7	9		T45	28
values[9]	150	1			T50	1		T213	7		T146	2
minimum	18250	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	9		T221	1		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	1		T138	2		T145	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T6	3		T8	17		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	1		T32	12		T139	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T137	1		T138	1		T49	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T36	1		T253	14		T151	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T33	1		T221	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	1		T168	1		T265	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	8		T31	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T33	2		T153	3		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T137	1		T30	2		T222	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T50	1		T167	11		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T139	15		T36	10		T156	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T29	13		T40	3		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	1		T147	8		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T154	9		T175	7		T285	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	3		T7	6		T45	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T137	1		T16	6		T34	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T213	1		T362	1		T363	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T50	1		T146	2		T308	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17959	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T253	16		T151	11		T277	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	9		T221	11		T153	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	4		T138	20		T142	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T110	22		T111	24		T263	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T10	11		T32	11		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T137	8		T138	2		T49	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T253	8		T273	1		T267	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T153	2		T41	1		T143	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T168	9		T19	4		T268	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	9		T31	11		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T153	8		T17	1		T158	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T222	6		T306	13		T60	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T167	9		T221	15		T160	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T139	17		T36	2		T156	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T29	13		T142	2		T212	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T249	2		T189	1		T190	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T154	11		T175	5		T285	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	3		T45	18		T32	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T16	2		T34	11		T158	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T213	6		T363	9		T364	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T302	11		T323	1		T365	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	1		T69	1		T36	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T253	15		T151	9		T277	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T213	1		T43	1		T362	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T34	15		T146	1		T158	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T161	12		T199	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T35	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T153	8		T201	14		T42	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T10	1		T138	1		T145	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T6	3		T7	9		T8	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T138	1		T172	19		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T137	1		T138	1		T49	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	1		T32	12		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T33	1		T221	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	1		T253	14		T351	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T141	1		T150	19		T143	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T33	2		T168	1		T153	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	8		T137	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T50	1		T167	11		T160	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T30	1		T139	15		T156	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T40	3		T221	1		T150	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	1		T36	10		T147	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T29	13		T154	9		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	3		T7	6		T45	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T137	1		T50	1		T16	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T213	6		T295	8		T352	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T34	11		T158	2		T189	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T161	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T153	5		T42	4		T51	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	4		T138	10		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T7	9		T110	22		T111	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T138	10		T172	11		T160	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T137	8		T138	2		T49	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	11		T32	11		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T153	2		T142	13		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T253	8		T19	4		T268	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T143	4		T158	12		T44	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T168	9		T153	8		T17	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T7	9		T31	11		T306	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T167	9		T160	6		T43	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T139	17		T156	5		T222	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T221	15		T212	8		T175	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T36	2		T249	16		T267	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T29	13		T154	11		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	3		T45	18		T32	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T16	2		T302	11		T215	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	10		T221	12		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T10	5		T138	22		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T6	3		T8	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	12		T32	12		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T137	9		T138	3		T49	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T36	1		T253	9		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T33	1		T221	1		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	1		T168	10		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	10		T31	12		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T33	2		T153	9		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T137	1		T30	2		T222	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T50	1		T167	10		T221	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T139	18		T36	3		T156	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T29	14		T40	3		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	1		T147	1		T51	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T154	12		T175	6		T285	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T5	3		T7	4		T45	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T137	1		T16	5		T34	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T213	7		T362	1		T363	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T50	1		T146	2		T308	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18056	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T253	16		T151	10		T277	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	8		T153	7		T143	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T145	13		T157	9		T38	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T8	16		T11	19		T46	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T32	11		T139	13		T172	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	2		T147	11		T159	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T253	13		T151	13		T267	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T41	1		T143	3		T286	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T265	9		T19	4		T259	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	7		T150	18		T158	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T153	2		T43	4		T250	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T222	2		T265	13		T60	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T167	10		T160	14		T150	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T139	14		T36	9		T156	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	12		T212	12		T256	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T147	7		T21	3		T262	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T154	8		T175	6		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	5		T45	9		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T16	3		T34	14		T145	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T364	5		T344	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T308	2		T302	10		T81	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T201	13		T51	10		T161	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T253	15		T151	10		T278	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T213	7		T43	1		T362	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T34	12		T146	1		T158	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T161	11		T199	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T35	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T153	6		T201	1		T42	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	5		T138	11		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T6	3		T7	10		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T138	11		T172	12		T160	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T137	9		T138	3		T49	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	12		T32	12		T139	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T33	1		T221	1		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T4	1		T253	9		T351	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T141	1		T150	1		T143	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T33	2		T168	10		T153	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	10		T137	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T50	1		T167	10		T160	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T30	1		T139	18		T156	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	3		T221	16		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	1		T36	3		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T29	14		T154	12		T142	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T5	3		T7	4		T45	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T137	1		T50	1		T16	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T295	8		T352	12		T364	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T34	14		T158	8		T308	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T161	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T153	7		T201	13		T42	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T145	13		T253	15		T151	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T7	8		T8	16		T11	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T172	18		T157	9		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T49	2		T147	11		T159	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T32	11		T139	13		T208	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T41	1		T286	11		T24	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T253	13		T19	4		T259	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T150	18		T143	3		T158	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T153	2		T265	9		T165	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T7	7		T262	8		T248	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T167	10		T160	14		T43	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T139	14		T156	5		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T150	20		T212	12		T175	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T36	9		T147	7		T267	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	12		T154	8		T175	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	5		T45	9		T32	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T16	3		T145	12		T302	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19