Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23463

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3298

1

T5

3

T7

17

T10

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20620

1

T1

10

T2

20

T3

16

auto[1]

6141

1

T5

3

T6

3

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	618	1			T7	17		T14	5		T16	1
values[0]	65	1			T180	12		T352	22		T279	15
values[1]	713	1			T45	28		T33	1		T140	1
values[2]	2894	1			T6	3		T8	17		T9	1
values[3]	673	1			T7	18		T137	1		T31	12
values[4]	536	1			T137	9		T34	26		T139	15
values[5]	627	1			T138	11		T33	1		T140	1
values[6]	867	1			T4	1		T5	3		T7	9
values[7]	545	1			T50	1		T16	8		T32	23
values[8]	596	1			T172	30		T49	12		T142	14
values[9]	1059	1			T10	1		T138	3		T30	1
minimum	17568	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	618	1			T45	28		T33	1		T145	13
values[1]	3031	1			T6	3		T7	18		T8	17
values[2]	584	1			T139	15		T221	12		T143	21
values[3]	543	1			T137	9		T33	1		T34	26
values[4]	661	1			T4	1		T138	11		T139	32
values[5]	808	1			T5	3		T7	9		T10	12
values[6]	645	1			T10	5		T50	1		T16	8
values[7]	562	1			T142	14		T146	1		T147	8
values[8]	886	1			T7	17		T10	1		T138	3
values[9]	120	1			T154	20		T151	25		T307	11
minimum	18303	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	10		T140	1		T249	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T33	1		T145	13		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1565	1			T6	3		T7	9		T8	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T29	13		T31	1		T167	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T158	18		T273	10		T322	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T139	11		T221	1		T143	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T33	1		T34	15		T160	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T137	1		T221	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	1		T140	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T138	1		T139	15		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	6		T30	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T5	3		T10	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T10	1		T50	1		T16	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T49	1		T201	14		T253	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T146	1		T147	8		T253	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T142	1		T175	13		T285	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T30	1		T221	1		T153	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	8		T10	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T151	13		T366	18		T309	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T154	9		T307	11		T78	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17986	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T153	3		T43	8		T248	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T45	18		T249	16		T19	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T249	2		T267	9		T189	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T7	9		T110	22		T111	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T29	13		T31	11		T167	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T158	12		T273	11		T289	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T139	4		T221	11		T143	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T34	11		T160	7		T255	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T137	8		T142	14		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T262	13		T257	2		T278	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T138	10		T139	17		T168	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	3		T142	2		T267	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	11		T138	10		T32	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	4		T16	2		T172	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T49	11		T253	8		T190	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T253	15		T250	13		T290	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T142	13		T175	10		T285	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T221	15		T153	5		T159	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	9		T138	2		T41	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T151	12		T309	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T154	11		T78	8		T367	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T16	1		T69	1		T36	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T153	8		T43	8		T248	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	466	1			T14	5		T16	1		T40	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	8		T145	11		T143	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T352	13		T368	1		T369	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T180	12		T279	15		T370	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T45	10		T140	1		T36	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T33	1		T153	3		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1528	1			T6	3		T8	17		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T29	13		T167	11		T145	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	9		T137	1		T158	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T31	1		T221	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	15		T160	16		T265	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T137	1		T139	11		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T33	1		T140	1		T151	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T138	1		T141	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	1		T7	6		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T5	3		T10	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T50	1		T16	6		T145	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T32	12		T139	14		T201	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T172	19		T146	1		T147	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T49	1		T142	1		T253	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T30	1		T221	1		T153	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T10	1		T138	1		T154	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17431	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T80	8		T183	4		T371	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T7	9		T143	4		T259	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T352	9		T368	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T370	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	18		T36	2		T208	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T153	8		T43	8		T249	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T110	22		T111	24		T263	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	13		T167	9		T49	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	9		T158	12		T273	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T31	11		T221	11		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T34	11		T160	7		T306	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T137	8		T139	4		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T255	6		T214	8		T278	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T138	10		T142	14		T212	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	3		T10	4		T142	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T10	11		T138	10		T139	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T16	2		T175	5		T158	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T32	11		T139	2		T256	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T172	11		T159	8		T250	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T49	11		T142	13		T253	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T221	15		T153	5		T253	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T138	2		T154	11		T41	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T45	19		T140	1		T249	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T33	1		T145	1		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T6	3		T7	10		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T29	14		T31	12		T167	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T158	13		T273	12		T322	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T139	5		T221	12		T143	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T33	1		T34	12		T160	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T137	9		T221	1		T142	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T4	1		T140	1		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T138	11		T139	18		T168	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	4		T30	1		T142	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	3		T10	12		T138	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	5		T50	1		T16	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T49	12		T201	1		T253	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T146	1		T147	1		T253	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T142	14		T175	11		T285	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T30	1		T221	16		T153	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	10		T10	1		T138	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T151	13		T366	1		T309	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T154	12		T307	1		T78	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18110	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T153	9		T43	12		T248	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T45	9		T19	4		T79	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T145	12		T267	9		T180	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T7	8		T8	16		T11	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T29	12		T167	10		T49	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T158	17		T273	9		T289	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T139	10		T143	10		T151	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	14		T160	14		T265	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T143	10		T212	12		T157	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T151	13		T262	11		T257	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T139	14		T150	18		T222	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	5		T267	8		T215	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T32	11		T139	13		T150	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T16	3		T172	18		T145	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T201	13		T253	13		T265	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T147	7		T253	15		T250	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T175	12		T163	14		T277	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T153	7		T159	7		T267	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	7		T145	10		T41	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T151	12		T366	17		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T154	8		T307	10		T207	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T36	9		T208	14		T274	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T153	2		T43	4		T248	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	445	1			T14	5		T16	1		T40	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T7	10		T145	1		T143	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T352	10		T368	3		T369	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T180	1		T279	1		T370	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T45	19		T140	1		T36	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T33	1		T153	9		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T6	3		T8	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	14		T167	10		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	10		T137	1		T158	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T31	12		T221	12		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T34	12		T160	9		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T137	9		T139	5		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T33	1		T140	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T138	11		T141	1		T142	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	1		T7	4		T10	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T5	3		T10	12		T138	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T50	1		T16	5		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T32	12		T139	3		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T172	12		T146	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T49	12		T142	14		T253	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T30	1		T221	16		T153	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T10	1		T138	3		T154	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17568	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T80	11		T183	12		T366	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T7	7		T145	10		T143	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T352	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T180	11		T279	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T45	9		T36	9		T208	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T153	2		T43	4		T267	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T8	16		T11	19		T46	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	12		T167	10		T145	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	8		T158	17		T273	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T143	10		T151	10		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T34	14		T160	14		T265	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T139	10		T143	10		T212	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T151	13		T214	17		T278	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T150	18		T222	2		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	5		T267	8		T262	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T139	14		T150	20		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	3		T145	13		T175	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T32	11		T139	13		T201	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T172	18		T147	7		T265	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T253	13		T265	13		T163	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T153	7		T253	15		T151	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T154	8		T41	1		T150	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19