Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T10	1		T30	1		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T139	18		T142	14		T155	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T32	8		T160	7		T49	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	10		T31	12		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	3		T50	1		T17	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T151	13		T158	13		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T10	5		T45	19		T29	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	4		T137	1		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	5		T213	7		T208	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T137	1		T138	11		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T142	3		T146	1		T175	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T141	1		T253	16		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T4	1		T6	3		T8	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T33	1		T167	10		T172	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T145	1		T153	3		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	10		T154	12		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T138	3		T50	1		T221	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T137	9		T138	11		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T153	6		T277	2		T278	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T268	7		T275	13		T279	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17992	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T140	1		T280	2		T185	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T201	13		T41	1		T265	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T139	14		T150	18		T175	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T32	6		T160	14		T157	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	7		T139	13		T49	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T143	10		T147	7		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T151	12		T158	17		T267	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T45	9		T29	12		T34	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	5		T153	2		T36	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T16	3		T208	14		T256	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T145	13		T156	5		T288	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T175	6		T256	13		T21	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T253	15		T151	13		T265	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1128	1			T8	16		T11	19		T46	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T167	10		T172	18		T150	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T145	10		T150	20		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T7	8		T154	8		T289	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T290	16		T272	2		T82	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T32	11		T145	12		T143	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T153	7		T278	2		T291	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T275	10		T279	6		T35	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T40	3		T41	1		T81	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T282	9		T283	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T30	1		T32	8		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T139	18		T140	1		T155	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	1		T49	12		T143	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T140	1		T142	14		T175	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	3		T50	1		T29	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	10		T31	12		T139	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T10	5		T45	19		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	4		T137	1		T36	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T34	12		T139	5		T221	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	1		T145	1		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T16	5		T213	7		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T138	11		T151	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T10	12		T30	1		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T33	1		T172	12		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T4	1		T6	3		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	10		T167	10		T154	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T138	3		T50	1		T221	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T137	9		T138	11		T32	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T81	10		T284	18		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T32	6		T201	13		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T139	14		T150	18		T292	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T143	10		T157	9		T42	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T175	12		T180	11		T163	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T29	12		T160	14		T147	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	7		T139	13		T153	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T45	9		T212	12		T158	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	5		T36	9		T156	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T34	14		T139	10		T208	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T145	13		T143	10		T162	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T16	3		T256	13		T163	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T151	13		T288	13		T38	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T175	6		T265	3		T21	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T172	18		T150	16		T253	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T8	16		T11	19		T46	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	8		T167	10		T154	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T145	10		T153	7		T150	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T32	11		T145	12		T253	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19