Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23020

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3741

1

T4

1

T7

35

T45

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20623

1

T1

10

T2

20

T3

16

auto[1]

6138

1

T4

1

T6

3

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T24	5		T293	1		T294	1
values[0]	107	1			T222	9		T20	4		T295	17
values[1]	594	1			T32	14		T139	16		T145	11
values[2]	844	1			T5	3		T138	11		T33	1
values[3]	635	1			T7	18		T10	1		T16	8
values[4]	537	1			T137	1		T30	1		T32	23
values[5]	2783	1			T4	1		T6	3		T8	17
values[6]	870	1			T7	9		T138	3		T33	1
values[7]	643	1			T137	9		T31	12		T221	12
values[8]	551	1			T7	17		T30	1		T139	32
values[9]	1200	1			T10	5		T45	28		T137	1
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	971	1			T32	14		T139	16		T145	11
values[1]	662	1			T5	3		T10	1		T138	11
values[2]	679	1			T7	18		T16	8		T29	26
values[3]	2769	1			T4	1		T6	3		T8	17
values[4]	615	1			T10	12		T50	1		T139	15
values[5]	762	1			T7	9		T138	3		T31	12
values[6]	751	1			T7	17		T137	9		T30	1
values[7]	595	1			T10	5		T137	1		T172	30
values[8]	823	1			T45	28		T221	1		T160	21
values[9]	129	1			T138	11		T50	1		T42	9
minimum	18005	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T32	7		T153	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T139	14		T145	11		T41	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	3		T10	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T138	1		T40	3		T154	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T16	6		T221	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	9		T29	13		T32	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T6	3		T8	17		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	1		T30	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	1		T139	11		T150	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T50	1		T212	1		T265	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	6		T138	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T31	1		T256	14		T250	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	1		T167	11		T145	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	8		T137	1		T139	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	1		T137	1		T172	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T153	8		T143	4		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T221	1		T160	15		T213	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T45	10		T140	1		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T138	1		T296	1		T274	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T50	1		T42	5		T189	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17858	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T32	7		T153	2		T142	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T139	2		T41	1		T143	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T168	9		T160	1		T259	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T138	10		T154	11		T159	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	2		T221	15		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	9		T29	13		T32	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T110	22		T111	24		T263	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	11		T49	11		T285	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T10	11		T139	4		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T212	4		T256	12		T260	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	3		T138	2		T273	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T31	11		T256	11		T250	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T167	9		T49	5		T253	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	9		T137	8		T139	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T10	4		T172	11		T151	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T153	5		T143	4		T181	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T160	6		T213	6		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T45	18		T267	12		T255	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T138	10		T296	11		T297	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T42	4		T189	8		T298	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	1		T69	1		T36	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T24	5		T293	1		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T222	3		T295	9		T299	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T20	3		T216	1		T300	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T32	7		T292	8		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T139	14		T145	11		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	3		T33	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T138	1		T40	3		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	1		T16	6		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	9		T29	13		T147	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T137	1		T175	7		T256	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T30	1		T32	12		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T6	3		T8	17		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T4	1		T50	1		T34	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	6		T138	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T151	14		T254	1		T256	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T145	13		T49	3		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T137	1		T31	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T30	1		T167	11		T253	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T7	8		T139	15		T153	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T10	1		T137	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T45	10		T50	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T222	6		T295	8		T301	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T20	1		T216	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T32	7		T255	9		T302	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T139	2		T41	1		T143	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T153	2		T142	14		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T138	10		T153	8		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T16	2		T168	9		T221	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	9		T29	13		T212	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T175	5		T256	10		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T32	11		T49	11		T285	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T10	11		T110	22		T111	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T34	11		T212	4		T256	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	3		T138	2		T151	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T256	11		T250	13		T260	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T49	5		T253	15		T249	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T137	8		T31	11		T221	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T167	9		T253	8		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	9		T139	17		T153	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T10	4		T138	10		T172	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T45	18		T42	4		T267	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T32	8		T153	3		T142	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T139	3		T145	1		T41	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T5	3		T10	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T138	11		T40	3		T154	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	5		T221	16		T155	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	10		T29	14		T32	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T6	3		T8	1		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T30	1		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T10	12		T139	5		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T50	1		T212	5		T265	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	4		T138	3		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T31	12		T256	12		T250	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T30	1		T167	10		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	10		T137	9		T139	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	5		T137	1		T172	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T153	6		T143	5		T181	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T221	1		T160	7		T213	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T45	19		T140	1		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T138	11		T296	12		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T50	1		T42	6		T189	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18004	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T32	6		T222	2		T292	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T139	13		T145	10		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T145	13		T201	13		T265	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T154	8		T150	16		T147	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T16	3		T150	20		T147	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	8		T29	12		T32	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T8	16		T11	19		T46	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	14		T157	9		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T139	10		T150	18		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T265	9		T256	13		T192	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	5		T273	9		T292	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T256	13		T250	14		T180	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T167	10		T145	12		T49	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	7		T139	14		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T172	18		T151	10		T265	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T153	7		T143	3		T81	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T160	14		T36	9		T253	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T45	9		T267	4		T163	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T274	10		T297	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T42	3		T189	3		T299	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T86	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T24	2		T293	1		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T222	7		T295	9		T299	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T20	3		T216	12		T300	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T32	8		T292	1		T255	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T139	3		T145	1		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	3		T33	1		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T138	11		T40	3		T153	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	1		T16	5		T168	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	10		T29	14		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T137	1		T175	6		T256	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	1		T32	12		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T6	3		T8	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	1		T50	1		T34	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	4		T138	3		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T151	1		T254	1		T256	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T145	1		T49	6		T41	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T137	9		T31	12		T221	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T30	1		T167	10		T253	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	10		T139	18		T153	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T10	5		T137	1		T138	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T45	19		T50	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T24	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T222	2		T295	8		T299	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T20	1		T300	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T32	6		T292	7		T302	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T139	13		T145	10		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T201	13		T265	13		T161	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T153	2		T154	8		T150	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	3		T145	13		T150	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	8		T29	12		T147	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T175	6		T256	10		T161	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T32	11		T157	9		T163	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1117	1			T8	16		T11	19		T46	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T34	14		T265	9		T256	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	5		T151	12		T273	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T151	13		T256	13		T250	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T145	12		T49	2		T253	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T159	6		T81	10		T275	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T167	10		T253	13		T151	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T7	7		T139	14		T153	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T172	18		T160	14		T36	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T45	9		T42	3		T267	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19