Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21310

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

5451

1

T6

3

T7

17

T8

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20928

1

T1

10

T2

20

T3

16

auto[1]

5833

1

T6

3

T7

26

T8

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T50	1		T303	1		T266	17
values[0]	15	1			T252	1		T304	14		-	-
values[1]	520	1			T7	18		T137	10		T31	12
values[2]	621	1			T5	3		T50	1		T33	1
values[3]	676	1			T16	8		T30	1		T34	26
values[4]	864	1			T10	12		T138	11		T139	32
values[5]	602	1			T32	14		T167	20		T221	12
values[6]	735	1			T4	1		T138	3		T30	1
values[7]	650	1			T7	17		T10	1		T45	28
values[8]	770	1			T7	9		T29	26		T221	1
values[9]	3300	1			T6	3		T8	17		T9	1
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	635	1			T7	18		T137	10		T50	1
values[1]	2841	1			T5	3		T6	3		T8	17
values[2]	701	1			T16	8		T34	26		T153	11
values[3]	840	1			T10	12		T138	11		T139	32
values[4]	540	1			T4	1		T32	37		T167	20
values[5]	787	1			T45	28		T138	3		T30	1
values[6]	693	1			T7	9		T10	1		T138	11
values[7]	736	1			T7	17		T139	15		T213	7
values[8]	781	1			T137	1		T50	1		T33	2
values[9]	211	1			T10	5		T140	1		T36	12
minimum	17996	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	9		T137	1		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T137	1		T50	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	3		T30	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1481	1			T6	3		T8	17		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T16	6		T34	15		T153	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T212	13		T158	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T138	1		T139	15		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T10	1		T253	16		T177	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	1		T32	7		T167	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T32	12		T221	1		T268	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T30	1		T172	19		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T45	10		T138	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	6		T138	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T10	1		T29	13		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T139	11		T153	8		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	8		T213	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	1		T33	2		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T137	1		T139	14		T145	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T10	1		T36	10		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T140	1		T150	17		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T305	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T7	9		T31	11		T160	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T137	8		T142	13		T181	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T221	15		T41	1		T249	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	955	1			T110	22		T111	24		T263	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	2		T34	11		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T212	8		T158	5		T306	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T138	10		T139	17		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	11		T253	15		T177	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T32	7		T167	9		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T32	11		T221	11		T268	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T172	11		T181	11		T277	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T45	18		T138	2		T168	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	3		T138	10		T142	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T29	13		T51	10		T256	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T139	4		T153	5		T49	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T7	9		T213	6		T49	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T155	13		T156	5		T42	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T139	2		T142	14		T159	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T10	4		T36	2		T161	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T20	1		T257	2		T183	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T50	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T303	1		T266	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T252	1		T304	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	9		T137	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T137	1		T142	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	3		T33	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T50	1		T160	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T16	6		T30	1		T34	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T253	16		T182	1		T276	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T138	1		T139	15		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T10	1		T212	13		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T32	7		T167	11		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T221	1		T143	11		T44	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	1		T30	1		T172	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T138	1		T32	12		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T138	1		T142	1		T285	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	8		T10	1		T45	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	6		T49	3		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T29	13		T221	1		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T10	1		T33	2		T139	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1681	1			T6	3		T8	17		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T266	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T7	9		T31	11		T160	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T137	8		T142	13		T38	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T221	15		T143	4		T249	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T160	1		T43	8		T181	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T16	2		T34	11		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T253	15		T269	10		T307	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T138	10		T139	17		T153	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	11		T212	8		T158	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T32	7		T167	9		T153	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T221	11		T143	10		T44	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T172	11		T208	2		T255	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T138	2		T32	11		T168	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T138	10		T142	2		T285	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	9		T45	18		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	3		T49	5		T175	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T29	13		T213	6		T49	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	4		T139	4		T153	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1042	1			T110	22		T111	24		T263	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	10		T137	1		T31	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T137	9		T50	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T5	3		T30	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1283	1			T6	3		T8	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T16	5		T34	12		T153	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T212	9		T158	6		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T138	11		T139	18		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T10	12		T253	16		T177	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	1		T32	8		T167	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T32	12		T221	12		T268	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T30	1		T172	12		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T45	19		T138	3		T168	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	4		T138	11		T142	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T29	14		T40	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T139	5		T153	6		T49	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	10		T213	7		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T50	1		T33	2		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T137	1		T139	3		T145	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T10	5		T36	3		T251	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T140	1		T150	1		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T305	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	8		T145	12		T160	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T162	16		T21	3		T307	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T41	1		T161	11		T215	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1153	1			T8	16		T11	19		T46	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	3		T34	14		T153	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T212	12		T308	2		T214	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T139	14		T154	8		T150	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T253	15		T177	21		T44	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T32	6		T167	10		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T32	11		T268	7		T24	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T172	18		T277	11		T271	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T45	9		T143	10		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	5		T158	25		T267	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T29	12		T51	10		T256	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T139	10		T153	7		T49	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T7	7		T256	13		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T147	7		T156	5		T265	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T139	13		T145	23		T159	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T36	9		T161	11		T260	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T150	16		T20	1		T257	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T305	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T50	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T303	1		T266	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T252	1		T304	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	10		T137	1		T31	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	9		T142	14		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	3		T33	1		T221	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T50	1		T160	2		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T16	5		T30	1		T34	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T253	16		T182	1		T276	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T138	11		T139	18		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	12		T212	9		T158	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T32	8		T167	10		T153	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T221	12		T143	11		T44	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	1		T30	1		T172	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T138	3		T32	12		T168	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T138	11		T142	3		T285	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	10		T10	1		T45	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	4		T49	6		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T29	14		T221	1		T213	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T10	5		T33	2		T139	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1398	1			T6	3		T8	1		T9	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T266	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T304	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T7	8		T145	12		T160	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T162	16		T38	7		T307	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T143	3		T215	16		T79	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T43	4		T21	3		T82	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T16	3		T34	14		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T253	15		T276	11		T308	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T139	14		T153	2		T154	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T212	12		T177	21		T288	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T32	6		T167	10		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T143	10		T44	4		T267	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T172	18		T208	14		T277	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T32	11		T157	9		T151	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T158	25		T267	9		T271	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	7		T45	9		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	5		T49	2		T150	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T29	12		T256	13		T19	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T139	10		T153	7		T36	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1325	1			T8	16		T11	19		T46	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19