Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23253

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3508

1

T7

26

T10

13

T137

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20786

1

T1

10

T2

20

T3

16

auto[1]

5975

1

T5

3

T6

3

T7

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	421	1			T14	5		T16	1		T40	3
values[0]	163	1			T33	1		T255	10		T180	12
values[1]	677	1			T45	28		T140	1		T153	11
values[2]	2870	1			T6	3		T8	17		T9	1
values[3]	648	1			T7	18		T137	10		T31	12
values[4]	516	1			T34	26		T139	15		T221	1
values[5]	711	1			T138	11		T33	1		T168	10
values[6]	808	1			T4	1		T7	9		T10	17
values[7]	606	1			T5	3		T50	1		T16	8
values[8]	512	1			T49	12		T142	14		T146	1
values[9]	1261	1			T7	17		T10	1		T138	3
minimum	17568	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	901	1			T45	28		T33	1		T145	13
values[1]	3025	1			T6	3		T7	18		T8	17
values[2]	594	1			T139	15		T221	12		T143	21
values[3]	581	1			T137	9		T33	1		T34	26
values[4]	664	1			T4	1		T138	11		T139	32
values[5]	764	1			T5	3		T7	9		T10	12
values[6]	645	1			T10	5		T50	1		T16	8
values[7]	492	1			T30	1		T146	1		T147	8
values[8]	855	1			T7	17		T10	1		T138	3
values[9]	236	1			T154	20		T307	11		T78	9
minimum	18004	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T45	10		T36	10		T208	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T33	1		T145	13		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1513	1			T6	3		T7	9		T8	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T137	1		T29	13		T32	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T139	11		T158	18		T273	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T221	1		T143	11		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T33	1		T160	15		T265	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T137	1		T34	15		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	1		T138	1		T139	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T168	1		T160	1		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	3		T138	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T7	6		T10	1		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T10	1		T50	1		T172	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	6		T253	14		T265	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T30	1		T146	1		T147	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T175	13		T285	1		T163	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T153	8		T142	1		T143	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	8		T10	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T154	9		T309	1		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T307	11		T78	1		T82	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T279	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T45	18		T36	2		T208	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T153	8		T43	8		T249	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T7	9		T110	22		T111	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T29	13		T32	7		T167	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T139	4		T158	12		T273	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T221	11		T143	10		T151	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T160	6		T269	10		T214	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T137	8		T34	11		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T138	10		T139	17		T212	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T168	9		T160	1		T213	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T138	10		T17	1		T142	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	3		T10	11		T32	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	4		T172	11		T49	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T16	2		T253	8		T190	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T250	13		T277	6		T310	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T175	10		T285	12		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T153	5		T142	13		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	9		T138	2		T221	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T154	11		T309	10		T109	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T78	8		T82	8		T311	36
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	421	1			T14	5		T16	1		T40	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T255	1		T312	1		T313	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T33	1		T180	12		T279	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T45	10		T155	1		T36	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T140	1		T153	3		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T6	3		T8	17		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T29	13		T32	7		T167	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	9		T31	1		T158	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T137	2		T221	1		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T139	11		T160	15		T265	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T34	15		T221	1		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T138	1		T33	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T168	1		T141	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	1		T10	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T7	6		T10	1		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	3		T50	1		T172	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T16	6		T32	12		T139	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T49	1		T142	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T265	24		T252	1		T290	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T30	1		T153	8		T154	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	439	1			T7	8		T10	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17431	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T255	9		T312	8		T313	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T314	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T45	18		T155	13		T36	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T153	8		T43	8		T249	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T110	22		T111	24		T263	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T29	13		T32	7		T167	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	9		T31	11		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T137	8		T221	11		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T139	4		T160	6		T306	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T34	11		T160	1		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T138	10		T212	4		T267	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T168	9		T142	14		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	4		T138	10		T139	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	3		T10	11		T213	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T172	11		T175	5		T158	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T16	2		T32	11		T139	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T49	11		T142	13		T159	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T290	16		T215	7		T22	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T153	5		T154	11		T143	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T7	9		T138	2		T221	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T45	19		T36	3		T208	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T33	1		T145	1		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T6	3		T7	10		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T137	1		T29	14		T32	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T139	5		T158	13		T273	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T221	12		T143	11		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T33	1		T160	7		T265	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T137	9		T34	12		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	1		T138	11		T139	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T168	10		T160	2		T213	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T5	3		T138	11		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	4		T10	12		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	5		T50	1		T172	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T16	5		T253	9		T265	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T30	1		T146	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T175	11		T285	13		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T153	6		T142	14		T143	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	10		T10	1		T138	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T154	12		T309	11		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T307	1		T78	9		T82	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T279	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T45	9		T36	9		T208	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T145	12		T153	2		T43	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T7	8		T8	16		T11	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T29	12		T32	6		T167	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T139	10		T158	17		T273	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T143	10		T151	10		T302	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T160	14		T265	3		T276	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T34	14		T143	10		T212	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T139	14		T151	13		T267	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T150	18		T222	2		T42	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T147	11		T286	8		T315	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T7	5		T32	11		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T172	18		T145	13		T201	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T16	3		T253	13		T265	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T147	7		T250	14		T192	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T175	12		T163	14		T290	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T153	7		T143	3		T253	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	7		T145	10		T41	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T154	8		T109	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T307	10		T82	10		T274	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T279	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	421	1			T14	5		T16	1		T40	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T255	10		T312	9		T313	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T33	1		T180	1		T279	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T45	19		T155	14		T36	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T140	1		T153	9		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T6	3		T8	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T29	14		T32	8		T167	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	10		T31	12		T158	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T137	10		T221	12		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T139	5		T160	7		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T34	12		T221	1		T160	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T138	11		T33	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T168	10		T141	1		T142	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	1		T10	5		T138	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T7	4		T10	12		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	3		T50	1		T172	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T16	5		T32	12		T139	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	12		T142	14		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T265	2		T252	1		T290	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T30	1		T153	6		T154	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	412	1			T7	10		T10	1		T138	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17568	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T313	12		T316	1		T317	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T180	11		T279	14		T314	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T45	9		T36	9		T208	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T153	2		T43	4		T267	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1135	1			T8	16		T11	19		T46	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	12		T32	6		T167	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	8		T158	17		T273	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T143	10		T151	10		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T139	10		T160	14		T265	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T34	14		T143	10		T212	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T151	13		T267	8		T292	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T150	18		T157	9		T261	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T139	14		T147	11		T318	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	5		T150	20		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T172	18		T145	13		T201	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T16	3		T32	11		T139	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T147	7		T159	6		T192	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T265	22		T290	16		T215	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T153	7		T154	8		T143	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T7	7		T145	10		T41	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19