Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23272

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3489

1

T5

3

T7

9

T10

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21337

1

T1

10

T2

20

T3

16

auto[1]

5424

1

T6

3

T7

17

T8

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	58	1			T154	20		T251	1		T319	1
values[0]	44	1			T78	13		T320	1		T321	5
values[1]	671	1			T10	12		T45	28		T138	11
values[2]	562	1			T5	3		T10	6		T168	10
values[3]	669	1			T4	1		T29	26		T139	15
values[4]	2859	1			T6	3		T7	9		T8	17
values[5]	814	1			T16	8		T167	20		T140	1
values[6]	700	1			T7	18		T137	1		T138	11
values[7]	864	1			T7	17		T137	1		T32	23
values[8]	467	1			T138	3		T50	1		T32	14
values[9]	1064	1			T137	9		T33	1		T40	3
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	828	1			T10	12		T45	28		T138	11
values[1]	615	1			T4	1		T5	3		T10	6
values[2]	680	1			T29	26		T172	30		T150	19
values[3]	2873	1			T6	3		T7	9		T8	17
values[4]	740	1			T7	18		T16	8		T139	16
values[5]	858	1			T7	17		T137	2		T138	11
values[6]	567	1			T32	23		T33	1		T221	16
values[7]	663	1			T138	3		T50	1		T32	14
values[8]	849	1			T137	9		T33	1		T145	14
values[9]	87	1			T40	3		T158	11		T322	1
minimum	18001	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T33	1		T145	13		T213	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T10	1		T45	10		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	1		T10	2		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	3		T139	11		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T29	13		T150	19		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T172	19		T143	11		T285	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T6	3		T8	17		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	6		T145	11		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T7	9		T16	6		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T167	11		T140	1		T153	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	8		T137	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T50	1		T30	1		T34	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	2		T141	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T32	12		T33	1		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T138	1		T32	7		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T50	1		T153	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T145	14		T160	15		T150	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T137	1		T33	1		T154	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T269	13		T320	1		T323	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T40	3		T158	9		T322	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17853	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T213	6		T142	2		T253	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	11		T45	18		T138	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T10	4		T168	9		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	4		T160	1		T256	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	13		T249	16		T250	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T172	11		T143	10		T285	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	927	1			T110	22		T111	24		T263	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	3		T143	10		T212	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	9		T16	2		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T167	9		T153	8		T267	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	9		T138	10		T44	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T34	11		T139	17		T49	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T17	1		T42	4		T306	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T32	11		T221	15		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T138	2		T32	7		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T153	2		T49	11		T51	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T160	6		T159	8		T270	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T137	8		T154	11		T142	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T269	10		T323	1		T324	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T158	2		T280	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T16	1		T31	11		T69	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T269	13		T325	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T154	9		T251	1		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T321	1		T326	11		T327	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T78	1		T320	1		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T31	1		T33	1		T145	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	1		T45	10		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	2		T168	1		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	3		T172	19		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	1		T29	13		T175	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T139	11		T285	1		T273	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T6	3		T8	17		T9	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	6		T145	11		T143	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T16	6		T177	22		T251	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T167	11		T140	1		T153	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	9		T137	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T50	1		T30	1		T139	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	8		T137	1		T17	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T32	12		T33	1		T34	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T138	1		T32	7		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T50	1		T49	1		T150	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T145	14		T160	15		T153	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T137	1		T33	1		T40	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T269	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T154	11		T315	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T321	4		T326	10		T327	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T78	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T31	11		T213	6		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	11		T45	18		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	4		T168	9		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T172	11		T160	1		T155	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T29	13		T175	5		T249	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T139	4		T285	12		T273	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T110	22		T111	24		T263	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	3		T143	20		T212	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	2		T177	11		T181	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T167	9		T153	8		T267	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	9		T138	10		T139	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T139	17		T49	5		T249	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	9		T17	1		T151	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T32	11		T34	11		T221	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T138	2		T32	7		T221	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T49	11		T189	9		T262	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T160	6		T153	5		T159	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T137	8		T153	2		T142	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T33	1		T145	1		T213	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	12		T45	19		T138	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	1		T10	6		T168	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	3		T139	5		T160	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T29	14		T150	1		T249	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T172	12		T143	11		T285	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T6	3		T8	1		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	4		T145	1		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	10		T16	5		T139	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T167	10		T140	1		T153	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	10		T137	2		T138	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T50	1		T30	1		T34	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T17	3		T141	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T32	12		T33	1		T221	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T138	3		T32	8		T221	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T50	1		T153	3		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T145	1		T160	7		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T137	9		T33	1		T154	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T269	11		T320	1		T323	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T40	3		T158	3		T322	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18001	1			T1	10		T2	20		T3	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T145	12		T253	28		T162	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T45	9		T147	7		T151	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T41	1		T175	6		T267	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T139	10		T256	13		T161	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	12		T150	18		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T172	18		T143	10		T161	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T8	16		T11	19		T46	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	5		T145	10		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	8		T16	3		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T167	10		T153	2		T267	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	7		T44	4		T267	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T34	14		T139	14		T49	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T42	3		T272	2		T328	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T32	11		T159	7		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T32	6		T153	7		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T150	20		T51	10		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T145	13		T160	14		T150	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T154	8		T201	13		T208	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T269	12		T323	1		T304	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T158	8		T329	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T269	11		T325	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T154	12		T251	1		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T321	5		T326	11		T327	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T78	13		T320	1		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T31	12		T33	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	12		T45	19		T138	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	6		T168	10		T41	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	3		T172	12		T160	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	1		T29	14		T175	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T139	5		T285	13		T273	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T6	3		T8	1		T9	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	4		T145	1		T143	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T16	5		T177	12		T251	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T167	10		T140	1		T153	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	10		T137	1		T138	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T50	1		T30	1		T139	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	10		T137	1		T17	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T32	12		T33	1		T34	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T138	3		T32	8		T221	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T50	1		T49	12		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T145	1		T160	7		T153	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T137	9		T33	1		T40	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T269	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T154	8		T315	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T326	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T145	12		T253	15		T162	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T45	9		T265	3		T276	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T41	1		T253	13		T267	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T172	18		T147	7		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T29	12		T175	6		T308	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T139	10		T256	13		T161	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T8	16		T11	19		T46	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	5		T145	10		T143	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	3		T177	21		T272	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T167	10		T153	2		T267	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	8		T139	13		T151	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T139	14		T49	2		T268	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	7		T151	12		T42	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T32	11		T34	14		T159	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T32	6		T222	2		T175	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T150	20		T189	3		T22	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T145	13		T160	14		T153	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T201	13		T208	14		T265	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19