Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23519

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3242

1

T7

44

T137

11

T138

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

10

T2

20

T3

16

auto[1]

5571

1

T4

1

T6

3

T8

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	131	1			T138	11		T168	10		T160	2
values[0]	11	1			T283	11		-	-		-	-
values[1]	831	1			T30	1		T139	32		T40	3
values[2]	714	1			T10	1		T32	14		T160	21
values[3]	688	1			T5	3		T7	17		T50	1
values[4]	864	1			T7	9		T10	5		T45	28
values[5]	729	1			T137	1		T34	26		T139	15
values[6]	547	1			T138	11		T16	8		T213	7
values[7]	626	1			T30	1		T33	2		T167	20
values[8]	2651	1			T4	1		T6	3		T7	18
values[9]	980	1			T137	9		T138	3		T50	1
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	765	1			T10	1		T30	1		T142	14
values[1]	646	1			T7	17		T31	12		T32	14
values[2]	823	1			T5	3		T10	5		T45	28
values[3]	812	1			T7	9		T137	1		T29	26
values[4]	634	1			T137	1		T138	11		T16	8
values[5]	609	1			T141	1		T142	3		T146	1
values[6]	2646	1			T4	1		T6	3		T8	17
values[7]	606	1			T7	18		T153	3		T154	20
values[8]	875	1			T137	9		T138	14		T50	1
values[9]	82	1			T153	13		T35	16		T281	6
minimum	18263	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T10	1		T30	1		T201	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T142	1		T155	1		T150	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T32	7		T160	15		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	8		T31	1		T139	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T5	3		T10	1		T45	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T151	13		T158	18		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T29	13		T33	1		T34	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	6		T137	1		T153	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	6		T213	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T137	1		T138	1		T145	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T142	1		T175	7		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T141	1		T146	1		T253	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1463	1			T4	1		T6	3		T8	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T33	1		T167	11		T172	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T153	1		T150	21		T147	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	9		T154	9		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T138	1		T50	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T137	1		T138	1		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T153	8		T281	1		T291	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T35	11		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17909	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T139	15		T140	1		T292	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T285	12		T249	7		T161	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T142	13		T155	13		T175	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T32	7		T160	6		T49	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	9		T31	11		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	4		T45	18		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T151	12		T158	12		T249	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T29	13		T34	11		T139	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	3		T153	8		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T16	2		T213	6		T256	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T138	10		T156	5		T273	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T142	2		T175	5		T256	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T253	15		T177	11		T38	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T10	11		T110	22		T111	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T167	9		T172	11		T158	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	2		T51	10		T267	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T7	9		T154	11		T273	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T138	2		T221	15		T160	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T137	8		T138	10		T32	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T153	5		T281	5		T291	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T35	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	1		T69	1		T36	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T139	17		T250	13		T214	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T160	1		T153	8		T189	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T138	1		T168	1		T312	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T30	1		T40	3		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T139	15		T140	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T10	1		T32	7		T160	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T140	1		T330	1		T251	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	3		T50	1		T29	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	8		T31	1		T139	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T10	1		T45	10		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	6		T137	1		T153	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T34	15		T139	11		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T137	1		T145	14		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	6		T213	1		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T138	1		T151	14		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T30	1		T33	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T33	1		T167	11		T172	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T4	1		T6	3		T8	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	9		T154	9		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T138	1		T50	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T137	1		T32	12		T145	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T160	1		T153	5		T189	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T138	10		T168	9		T312	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T283	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T41	1		T285	12		T249	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	17		T142	13		T155	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T32	7		T160	6		T49	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T286	8		T82	8		T258	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	13		T17	1		T212	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	9		T31	11		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T10	4		T45	18		T212	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	3		T153	8		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T34	11		T139	4		T221	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T143	10		T156	5		T273	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T16	2		T213	6		T256	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T138	10		T177	11		T38	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T142	2		T175	5		T44	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T167	9		T172	11		T253	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T10	11		T110	22		T111	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	9		T154	11		T289	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T138	2		T221	15		T189	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T137	8		T32	11		T142	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T10	1		T30	1		T201	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T142	14		T155	14		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T32	8		T160	7		T49	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	10		T31	12		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T5	3		T10	5		T45	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T151	13		T158	13		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T29	14		T33	1		T34	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	4		T137	1		T153	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	5		T213	7		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T137	1		T138	11		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T142	3		T175	6		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T141	1		T146	1		T253	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T4	1		T6	3		T8	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T33	1		T167	10		T172	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T153	3		T150	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	10		T154	12		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T138	3		T50	1		T221	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T137	9		T138	11		T32	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T153	6		T281	6		T291	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T35	11		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18043	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T139	18		T140	1		T292	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T201	13		T292	10		T180	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T150	18		T175	12		T302	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T32	6		T160	14		T143	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	7		T139	13		T49	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T45	9		T147	7		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T151	12		T158	17		T267	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	12		T34	14		T139	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	5		T153	2		T36	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T16	3		T256	13		T259	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T145	13		T156	5		T288	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T175	6		T256	13		T163	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T253	15		T151	13		T265	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T8	16		T11	19		T46	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T167	10		T172	18		T150	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T150	20		T147	11		T51	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	8		T154	8		T273	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T145	10		T272	2		T82	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T32	11		T145	12		T143	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T153	7		T291	13		T331	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T35	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T41	1		T265	9		T277	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T139	14		T292	7		T250	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T160	2		T153	6		T189	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T138	11		T168	10		T312	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T30	1		T40	3		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T139	18		T140	1		T142	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T10	1		T32	8		T160	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T140	1		T330	1		T251	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	3		T50	1		T29	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	10		T31	12		T139	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T10	5		T45	19		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	4		T137	1		T153	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T34	12		T139	5		T221	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T137	1		T145	1		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T16	5		T213	7		T51	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T138	11		T151	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T30	1		T33	1		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T33	1		T167	10		T172	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T4	1		T6	3		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	10		T154	12		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T138	3		T50	1		T221	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T137	9		T32	12		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T153	7		T332	9		T291	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T333	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T201	13		T41	1		T265	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T139	14		T150	18		T175	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T32	6		T160	14		T143	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T163	11		T286	8		T82	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	12		T147	7		T43	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	7		T139	13		T49	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T45	9		T212	12		T158	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	5		T153	2		T36	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T34	14		T139	10		T208	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T145	13		T143	10		T156	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T16	3		T256	13		T163	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T151	13		T177	21		T162	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T175	6		T265	3		T44	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T167	10		T172	18		T150	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T8	16		T11	19		T46	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	8		T154	8		T289	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T145	10		T147	11		T290	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T32	11		T145	12		T143	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19