Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23388

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3373

1

T7

17

T10

18

T45

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21019

1

T1

10

T2

20

T3

16

auto[1]

5742

1

T5

3

T6

3

T7

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	205	1			T31	12		T142	15		T182	1
values[0]	20	1			T81	13		T334	7		-	-
values[1]	945	1			T4	1		T7	17		T138	3
values[2]	796	1			T138	11		T139	16		T153	13
values[3]	608	1			T137	9		T139	15		T153	11
values[4]	525	1			T137	1		T29	26		T33	2
values[5]	2710	1			T6	3		T8	17		T9	1
values[6]	715	1			T50	1		T32	14		T172	30
values[7]	805	1			T7	9		T10	13		T138	11
values[8]	603	1			T45	28		T16	8		T30	1
values[9]	840	1			T5	3		T7	18		T139	32
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	815	1			T4	1		T138	3		T30	1
values[1]	725	1			T138	11		T153	24		T141	1
values[2]	650	1			T137	9		T33	1		T139	31
values[3]	2680	1			T6	3		T8	17		T9	1
values[4]	654	1			T10	5		T137	1		T50	1
values[5]	558	1			T138	11		T50	1		T32	14
values[6]	894	1			T7	9		T10	13		T45	28
values[7]	595	1			T30	1		T32	23		T33	1
values[8]	803	1			T5	3		T7	18		T31	12
values[9]	108	1			T267	19		T181	12		T278	3
minimum	18279	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	1		T138	1		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T30	1		T40	3		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T153	3		T147	8		T250	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T138	1		T153	8		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T137	1		T139	11		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T33	1		T139	14		T201	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T6	3		T8	17		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T33	1		T145	11		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T137	1		T50	1		T34	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	1		T172	19		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T145	13		T143	11		T175	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T138	1		T50	1		T32	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	6		T16	6		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T10	2		T45	10		T145	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T30	1		T33	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T32	12		T139	15		T265	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T5	3		T7	9		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T168	1		T154	9		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T267	10		T278	3		T205	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T181	1		T335	1		T336	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17972	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T7	8		T213	1		T255	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T138	2		T221	11		T143	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T221	15		T212	8		T156	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T153	8		T250	13		T286	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T138	10		T153	5		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T137	8		T139	4		T43	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T139	2		T158	12		T277	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T110	22		T111	24		T263	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T253	8		T161	8		T306	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T34	11		T167	9		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	4		T172	11		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T143	10		T175	10		T249	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T138	10		T32	7		T160	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	3		T16	2		T142	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	11		T45	18		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T153	2		T159	8		T337	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T32	11		T139	17		T51	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	9		T31	11		T155	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T168	9		T154	11		T142	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T267	9		T205	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T181	11		T335	11		T338	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T16	1		T160	6		T69	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T7	9		T213	6		T255	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T31	1		T273	1		T267	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T142	1		T182	1		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T81	13		T334	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T4	1		T138	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	8		T30	1		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T147	8		T250	15		T286	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T138	1		T139	14		T153	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T137	1		T139	11		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T201	14		T146	1		T158	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T137	1		T29	13		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T33	2		T140	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T6	3		T8	17		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T10	1		T145	11		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T145	13		T41	4		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T50	1		T32	7		T172	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T7	6		T140	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	2		T138	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T16	6		T30	1		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T45	10		T32	12		T145	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T5	3		T7	9		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T139	15		T168	1		T154	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T31	11		T273	1		T267	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T142	14		T328	9		T335	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T334	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T138	2		T221	11		T160	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	9		T221	15		T213	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T250	13		T286	8		T82	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T138	10		T139	2		T153	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T137	8		T139	4		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T158	12		T44	4		T277	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T29	13		T49	5		T189	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T253	8		T306	13		T248	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T110	22		T111	24		T263	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	4		T158	5		T267	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T41	1		T143	10		T175	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T32	7		T172	11		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	3		T142	13		T249	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	11		T138	10		T160	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T16	2		T159	8		T189	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T45	18		T32	11		T51	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	9		T153	2		T155	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T139	17		T168	9		T154	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	1		T138	3		T221	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T30	1		T40	3		T221	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T153	9		T147	1		T250	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T138	11		T153	6		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T137	9		T139	5		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T33	1		T139	3		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T6	3		T8	1		T9	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T33	1		T145	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T137	1		T50	1		T34	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	5		T172	12		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T145	1		T143	11		T175	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T138	11		T50	1		T32	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	4		T16	5		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	13		T45	19		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T30	1		T33	1		T153	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T32	12		T139	18		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	3		T7	10		T31	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T168	10		T154	12		T142	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T267	10		T278	1		T205	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T181	12		T335	12		T336	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18055	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T7	10		T213	7		T255	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T143	10		T253	15		T222	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T150	36		T212	12		T156	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T153	2		T147	7		T250	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T153	7		T157	9		T44	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T139	10		T43	4		T267	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T139	13		T201	13		T158	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T8	16		T11	19		T46	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T145	10		T253	13		T265	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T34	14		T167	10		T151	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T172	18		T267	4		T180	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T145	12		T143	10		T175	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T32	6		T36	9		T175	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	5		T16	3		T41	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T45	9		T145	13		T208	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T159	6		T272	2		T337	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T32	11		T139	14		T265	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	8		T150	18		T143	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T154	8		T162	16		T328	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T267	9		T278	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T339	14		T340	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T160	14		T158	8		T161	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T7	7		T81	12		T295	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T31	12		T273	2		T267	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T142	15		T182	1		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T81	1		T334	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	1		T138	3		T221	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T7	10		T30	1		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T147	1		T250	14		T286	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T138	11		T139	3		T153	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T137	9		T139	5		T153	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T201	1		T146	1		T158	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T137	1		T29	14		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T33	2		T140	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T6	3		T8	1		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	5		T145	1		T158	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T145	1		T41	4		T143	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T50	1		T32	8		T172	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	4		T140	1		T142	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	13		T138	11		T160	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T16	5		T30	1		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T45	19		T32	12		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T5	3		T7	10		T153	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T139	18		T168	10		T154	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T267	9		T22	2		T329	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T328	16		T339	14		T341	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T81	12		T334	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T160	14		T143	10		T253	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	7		T150	20		T156	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T147	7		T250	14		T286	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T139	13		T153	7		T150	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T139	10		T153	2		T43	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T201	13		T158	17		T44	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	12		T49	2		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T253	13		T265	9		T272	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1163	1			T8	16		T11	19		T46	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T145	10		T267	4		T161	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T145	12		T41	1		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T32	6		T172	18		T36	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	5		T292	10		T192	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T208	14		T265	3		T308	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T16	3		T159	6		T189	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T45	9		T32	11		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	8		T150	18		T143	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	14		T154	8		T162	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19