Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26761

1

T1

10

T2

20

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23338

1

T1

10

T2

20

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3423

1

T5

3

T7

26

T10

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21041

1

T1

10

T2

20

T3

16

auto[1]

5720

1

T4

1

T6

3

T8

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23006

1

T1

10

T2

20

T3

16

auto[1]

3755

1

T7

21

T10

15

T45

18

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	323	1			T7	17		T137	9		T167	20
values[0]	29	1			T138	11		T264	1		T266	17
values[1]	736	1			T10	1		T137	1		T32	37
values[2]	739	1			T153	13		T49	12		T150	40
values[3]	659	1			T4	1		T138	3		T40	3
values[4]	479	1			T5	3		T146	2		T147	8
values[5]	644	1			T138	11		T29	26		T31	12
values[6]	585	1			T7	9		T50	1		T139	15
values[7]	668	1			T10	5		T137	1		T50	1
values[8]	620	1			T139	16		T221	16		T160	23
values[9]	3290	1			T6	3		T7	18		T8	17
minimum	17989	1			T1	10		T2	20		T3	16

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	780	1			T10	1		T137	1		T32	23
values[1]	726	1			T4	1		T153	13		T49	12
values[2]	655	1			T138	3		T40	3		T155	14
values[3]	509	1			T5	3		T138	11		T139	32
values[4]	636	1			T29	26		T31	12		T145	14
values[5]	566	1			T7	9		T137	1		T50	1
values[6]	2811	1			T6	3		T8	17		T9	1
values[7]	651	1			T45	28		T16	8		T139	16
values[8]	1149	1			T7	35		T10	12		T137	9
values[9]	147	1			T167	20		T212	21		T254	1
minimum	18131	1			T1	10		T2	20		T3	16

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

4111

1

T7

20

T8

16

T11

19

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T32	12		T145	13		T147	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	1		T137	1		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T4	1		T49	1		T150	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T153	8		T150	38		T143	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T138	1		T147	8		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	3		T155	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T138	1		T139	15		T41	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	3		T158	1		T250	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T201	14		T251	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T29	13		T31	1		T145	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T137	1		T253	14		T222	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	6		T50	1		T139	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T6	3		T8	17		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T10	1		T145	11		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T139	14		T221	1		T160	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T45	10		T16	6		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T7	9		T33	1		T168	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T7	8		T10	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T212	13		T183	13		T230	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T167	11		T254	1		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17899	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T32	7		T78	1		T299	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T32	11		T253	15		T177	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T17	1		T142	13		T156	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	11		T208	2		T151	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T153	5		T143	10		T175	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T138	2		T256	11		T259	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T155	13		T249	7		T255	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T138	10		T139	17		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T158	5		T250	13		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T260	2		T261	1		T262	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	13		T31	11		T49	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T253	8		T222	6		T175	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	3		T139	4		T221	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T110	22		T111	24		T263	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	4		T160	1		T213	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T139	2		T221	15		T160	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T45	18		T16	2		T142	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	9		T168	9		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T7	9		T10	11		T137	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T212	8		T183	4		T24	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T167	9		T249	16		T342	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	10		T16	1		T69	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T32	7		T78	8		T343	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T221	1		T142	1		T212	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T7	8		T137	1		T167	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T138	1		T264	1		T266	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T32	12		T33	1		T145	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	1		T137	1		T32	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T49	1		T150	19		T208	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T153	8		T150	21		T175	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	1		T138	1		T256	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	3		T155	1		T150	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T146	1		T147	8		T151	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	3		T146	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T138	1		T139	15		T201	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T29	13		T31	1		T145	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T253	14		T222	3		T175	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	6		T50	1		T139	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T137	1		T50	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	1		T145	11		T265	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T139	14		T221	1		T160	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T160	1		T213	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T6	3		T7	9		T8	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T10	1		T45	10		T16	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17852	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T142	14		T212	8		T189	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T7	9		T137	8		T167	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T138	10		T266	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T32	11		T177	11		T267	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T32	7		T17	1		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T49	11		T208	2		T253	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T153	5		T175	5		T164	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T138	2		T256	11		T259	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T155	13		T143	10		T249	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T270	11		T277	1		T260	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T158	5		T250	13		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T138	10		T139	17		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	13		T31	11		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T253	8		T222	6		T175	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T7	3		T139	4		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T172	11		T153	8		T36	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	4		T161	8		T38	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T139	2		T221	15		T160	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T160	1		T213	6		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T7	9		T110	22		T111	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T10	11		T45	18		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T16	1		T69	1		T36	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T32	12		T145	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	1		T137	1		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T49	12		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T153	6		T150	2		T143	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T138	3		T147	1		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	3		T155	14		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T138	11		T139	18		T41	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	3		T158	6		T250	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T201	1		T251	1		T252	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T29	14		T31	12		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T137	1		T253	9		T222	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	4		T50	1		T139	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T6	3		T8	1		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	5		T145	1		T160	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T139	3		T221	16		T160	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T45	19		T16	5		T142	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T7	10		T33	1		T168	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T7	10		T10	12		T137	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T212	9		T183	5		T230	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T167	10		T254	1		T249	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18032	1			T1	10		T2	20		T3	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T32	8		T78	9		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T32	11		T145	12		T147	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T156	5		T158	8		T292	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T150	18		T208	14		T151	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T153	7		T150	36		T143	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T147	7		T256	13		T163	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T265	3		T271	1		T272	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T139	14		T41	1		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T250	14		T162	16		T20	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T201	13		T260	7		T262	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T29	12		T145	13		T49	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T253	13		T222	2		T175	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T7	5		T139	10		T288	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1118	1			T8	16		T11	19		T46	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T145	10		T265	13		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T139	13		T160	14		T143	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T45	9		T16	3		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	8		T154	8		T158	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T7	7		T34	14		T157	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T212	12		T183	12		T24	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T167	10		T342	6		T344	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T277	5		T345	9		T339	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T32	6		T299	4		T343	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T221	1		T142	15		T212	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T7	10		T137	9		T167	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T138	11		T264	1		T266	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T32	12		T33	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	1		T137	1		T32	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T49	12		T150	1		T208	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T153	6		T150	1		T175	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	1		T138	3		T256	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T40	3		T155	14		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T146	1		T147	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	3		T146	1		T158	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T138	11		T139	18		T201	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	14		T31	12		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T253	9		T222	7		T175	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	4		T50	1		T139	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T137	1		T50	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	5		T145	1		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T139	3		T221	16		T160	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T160	2		T213	7		T142	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T6	3		T7	10		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T10	12		T45	19		T16	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	10		T2	20		T3	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T212	12		T162	10		T274	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T7	7		T167	10		T273	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T266	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T32	11		T145	12		T147	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T32	6		T156	5		T158	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T150	18		T208	14		T253	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T153	7		T150	20		T175	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T256	13		T163	17		T192	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T150	16		T143	10		T265	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T147	7		T151	13		T86	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T250	14		T20	1		T106	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T139	14		T201	13		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T29	12		T145	13		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T253	13		T222	2		T175	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	5		T139	10		T49	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T172	18		T153	2		T36	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T145	10		T265	13		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T139	13		T160	14		T143	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T151	12		T159	7		T276	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T7	8		T8	16		T11	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T45	9		T16	3		T34	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22650

1

T1

10

T2

20

T3

16

auto[1]

auto[0]

4111

1

T7

20

T8

16

T11

19