Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.67 99.07 96.67 100.00 100.00 98.83 98.33 90.77


Total test records in report: 916
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T185 /workspace/coverage/default/41.adc_ctrl_filters_both.855919112 Apr 18 12:51:10 PM PDT 24 Apr 18 12:55:17 PM PDT 24 518010999162 ps
T794 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1461288379 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:43 PM PDT 24 423485582 ps
T61 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4012026549 Apr 18 12:43:39 PM PDT 24 Apr 18 12:43:41 PM PDT 24 662494019 ps
T795 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4054759387 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:49 PM PDT 24 371020576 ps
T796 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1720771984 Apr 18 12:43:51 PM PDT 24 Apr 18 12:43:52 PM PDT 24 525511968 ps
T62 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4145000043 Apr 18 12:43:33 PM PDT 24 Apr 18 12:43:37 PM PDT 24 909053703 ps
T87 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.604008302 Apr 18 12:43:29 PM PDT 24 Apr 18 12:43:33 PM PDT 24 510427637 ps
T132 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3444645555 Apr 18 12:43:29 PM PDT 24 Apr 18 12:43:33 PM PDT 24 1010920560 ps
T66 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2593009439 Apr 18 12:43:30 PM PDT 24 Apr 18 12:43:33 PM PDT 24 678916198 ps
T127 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3951392130 Apr 18 12:43:34 PM PDT 24 Apr 18 12:43:43 PM PDT 24 2160182188 ps
T133 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4226163986 Apr 18 12:43:26 PM PDT 24 Apr 18 12:43:30 PM PDT 24 763184149 ps
T797 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4169809342 Apr 18 12:43:46 PM PDT 24 Apr 18 12:43:48 PM PDT 24 441277594 ps
T67 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3649368679 Apr 18 12:43:42 PM PDT 24 Apr 18 12:43:47 PM PDT 24 839261728 ps
T68 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.484137830 Apr 18 12:44:01 PM PDT 24 Apr 18 12:44:04 PM PDT 24 545207759 ps
T128 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.126012148 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:42 PM PDT 24 469244079 ps
T798 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1013118235 Apr 18 12:43:36 PM PDT 24 Apr 18 12:43:38 PM PDT 24 379374225 ps
T799 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2288939755 Apr 18 12:43:49 PM PDT 24 Apr 18 12:43:51 PM PDT 24 372518946 ps
T72 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3345733206 Apr 18 12:43:52 PM PDT 24 Apr 18 12:43:55 PM PDT 24 1730426602 ps
T800 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2835806095 Apr 18 12:43:51 PM PDT 24 Apr 18 12:43:54 PM PDT 24 487222951 ps
T112 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2328928090 Apr 18 12:43:35 PM PDT 24 Apr 18 12:43:36 PM PDT 24 425786828 ps
T801 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4126733053 Apr 18 12:43:48 PM PDT 24 Apr 18 12:43:50 PM PDT 24 353781326 ps
T129 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.108971049 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:49 PM PDT 24 378608270 ps
T113 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1319794946 Apr 18 12:43:31 PM PDT 24 Apr 18 12:43:33 PM PDT 24 410108588 ps
T802 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1890570087 Apr 18 12:43:55 PM PDT 24 Apr 18 12:43:58 PM PDT 24 498950474 ps
T57 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2608567921 Apr 18 12:43:25 PM PDT 24 Apr 18 12:43:33 PM PDT 24 4429666758 ps
T803 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.942944972 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:43 PM PDT 24 433619620 ps
T54 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.796554355 Apr 18 12:43:44 PM PDT 24 Apr 18 12:43:52 PM PDT 24 2165237510 ps
T55 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3042568534 Apr 18 12:43:37 PM PDT 24 Apr 18 12:43:40 PM PDT 24 2196497066 ps
T114 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3439428443 Apr 18 12:43:28 PM PDT 24 Apr 18 12:43:32 PM PDT 24 779280895 ps
T56 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2109331695 Apr 18 12:43:43 PM PDT 24 Apr 18 12:43:56 PM PDT 24 4817763797 ps
T804 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4291311177 Apr 18 12:43:55 PM PDT 24 Apr 18 12:43:58 PM PDT 24 523107214 ps
T58 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2300988089 Apr 18 12:43:36 PM PDT 24 Apr 18 12:43:42 PM PDT 24 4369532791 ps
T805 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.155198909 Apr 18 12:43:29 PM PDT 24 Apr 18 12:43:32 PM PDT 24 371709621 ps
T130 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.968976726 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:49 PM PDT 24 524868733 ps
T88 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1203603305 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:44 PM PDT 24 493060554 ps
T59 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.146360988 Apr 18 12:43:30 PM PDT 24 Apr 18 12:43:39 PM PDT 24 9111706494 ps
T373 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.332435983 Apr 18 12:43:38 PM PDT 24 Apr 18 12:43:44 PM PDT 24 4527761660 ps
T107 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3099945620 Apr 18 12:43:27 PM PDT 24 Apr 18 12:43:50 PM PDT 24 8305966464 ps
T115 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.107548876 Apr 18 12:43:25 PM PDT 24 Apr 18 12:44:45 PM PDT 24 43855732713 ps
T108 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2369743030 Apr 18 12:43:48 PM PDT 24 Apr 18 12:43:51 PM PDT 24 362368745 ps
T806 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1378694525 Apr 18 12:43:52 PM PDT 24 Apr 18 12:44:05 PM PDT 24 4283511872 ps
T807 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1285044258 Apr 18 12:43:37 PM PDT 24 Apr 18 12:43:39 PM PDT 24 430459813 ps
T131 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3389310770 Apr 18 12:43:36 PM PDT 24 Apr 18 12:43:48 PM PDT 24 4560782688 ps
T808 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.295126322 Apr 18 12:43:48 PM PDT 24 Apr 18 12:43:57 PM PDT 24 7962235326 ps
T809 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2441725811 Apr 18 12:43:48 PM PDT 24 Apr 18 12:43:50 PM PDT 24 541482761 ps
T372 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4222476450 Apr 18 12:43:41 PM PDT 24 Apr 18 12:43:50 PM PDT 24 8196187525 ps
T810 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.665579099 Apr 18 12:43:24 PM PDT 24 Apr 18 12:43:26 PM PDT 24 389595724 ps
T811 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2741156223 Apr 18 12:43:36 PM PDT 24 Apr 18 12:43:39 PM PDT 24 340361126 ps
T812 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3155469501 Apr 18 12:43:29 PM PDT 24 Apr 18 12:43:33 PM PDT 24 459370282 ps
T813 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1957427025 Apr 18 12:43:53 PM PDT 24 Apr 18 12:43:55 PM PDT 24 432190449 ps
T814 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3933904469 Apr 18 12:43:54 PM PDT 24 Apr 18 12:43:55 PM PDT 24 357386169 ps
T815 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.329278632 Apr 18 12:43:53 PM PDT 24 Apr 18 12:43:56 PM PDT 24 445844414 ps
T816 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.507117721 Apr 18 12:43:36 PM PDT 24 Apr 18 12:43:37 PM PDT 24 427216341 ps
T817 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1739932004 Apr 18 12:43:37 PM PDT 24 Apr 18 12:43:42 PM PDT 24 4683716680 ps
T818 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4098486939 Apr 18 12:43:28 PM PDT 24 Apr 18 12:43:44 PM PDT 24 4389038311 ps
T819 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.931126883 Apr 18 12:43:48 PM PDT 24 Apr 18 12:43:54 PM PDT 24 2834130648 ps
T820 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.788367212 Apr 18 12:43:41 PM PDT 24 Apr 18 12:43:44 PM PDT 24 423035576 ps
T116 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1166461915 Apr 18 12:43:26 PM PDT 24 Apr 18 12:43:29 PM PDT 24 1231333747 ps
T821 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2493020493 Apr 18 12:43:29 PM PDT 24 Apr 18 12:43:37 PM PDT 24 4158999050 ps
T374 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.807387857 Apr 18 12:43:41 PM PDT 24 Apr 18 12:43:47 PM PDT 24 9193338598 ps
T822 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2188615482 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:48 PM PDT 24 502347661 ps
T823 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1130690583 Apr 18 12:43:48 PM PDT 24 Apr 18 12:43:56 PM PDT 24 4538209318 ps
T824 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.70387830 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:49 PM PDT 24 499683595 ps
T117 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3117792655 Apr 18 12:43:41 PM PDT 24 Apr 18 12:43:43 PM PDT 24 484896938 ps
T825 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4169684518 Apr 18 12:43:26 PM PDT 24 Apr 18 12:43:28 PM PDT 24 434185283 ps
T826 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.842824468 Apr 18 12:43:33 PM PDT 24 Apr 18 12:43:36 PM PDT 24 769077794 ps
T118 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1595648235 Apr 18 12:43:30 PM PDT 24 Apr 18 12:43:57 PM PDT 24 18203206040 ps
T827 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3132904529 Apr 18 12:43:48 PM PDT 24 Apr 18 12:43:52 PM PDT 24 648900113 ps
T828 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3958728791 Apr 18 12:43:42 PM PDT 24 Apr 18 12:43:46 PM PDT 24 692914113 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2420254696 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:50 PM PDT 24 300779818 ps
T830 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1846821322 Apr 18 12:43:38 PM PDT 24 Apr 18 12:43:40 PM PDT 24 423501048 ps
T831 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1876381726 Apr 18 12:43:33 PM PDT 24 Apr 18 12:43:36 PM PDT 24 819601801 ps
T832 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1226266511 Apr 18 12:43:33 PM PDT 24 Apr 18 12:43:36 PM PDT 24 2398782459 ps
T833 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2854645003 Apr 18 12:43:46 PM PDT 24 Apr 18 12:43:48 PM PDT 24 412577245 ps
T834 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3802370060 Apr 18 12:43:45 PM PDT 24 Apr 18 12:43:49 PM PDT 24 4893600552 ps
T835 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.439574013 Apr 18 12:43:30 PM PDT 24 Apr 18 12:43:33 PM PDT 24 2003539754 ps
T836 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3570942620 Apr 18 12:43:23 PM PDT 24 Apr 18 12:43:26 PM PDT 24 436391419 ps
T837 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.833908904 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:43 PM PDT 24 440705910 ps
T838 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1539449117 Apr 18 12:43:27 PM PDT 24 Apr 18 12:43:34 PM PDT 24 5072389096 ps
T839 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.578431169 Apr 18 12:43:38 PM PDT 24 Apr 18 12:43:41 PM PDT 24 672381381 ps
T840 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1628638769 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:48 PM PDT 24 415737429 ps
T841 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2249098297 Apr 18 12:43:28 PM PDT 24 Apr 18 12:43:30 PM PDT 24 436145688 ps
T119 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2054790496 Apr 18 12:43:36 PM PDT 24 Apr 18 12:43:38 PM PDT 24 409126761 ps
T842 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1260093646 Apr 18 12:43:36 PM PDT 24 Apr 18 12:43:46 PM PDT 24 3760178537 ps
T843 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.323731710 Apr 18 12:43:49 PM PDT 24 Apr 18 12:43:50 PM PDT 24 408984433 ps
T844 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3808533776 Apr 18 12:43:39 PM PDT 24 Apr 18 12:43:44 PM PDT 24 582321624 ps
T120 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.910254055 Apr 18 12:43:27 PM PDT 24 Apr 18 12:43:30 PM PDT 24 577609074 ps
T845 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3353293459 Apr 18 12:43:32 PM PDT 24 Apr 18 12:43:34 PM PDT 24 313933665 ps
T846 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2659197789 Apr 18 12:43:23 PM PDT 24 Apr 18 12:43:37 PM PDT 24 4810933048 ps
T847 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4269175932 Apr 18 12:43:54 PM PDT 24 Apr 18 12:43:55 PM PDT 24 478805029 ps
T848 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2140413818 Apr 18 12:43:25 PM PDT 24 Apr 18 12:43:28 PM PDT 24 878815539 ps
T849 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1647753678 Apr 18 12:43:52 PM PDT 24 Apr 18 12:44:03 PM PDT 24 4151520890 ps
T850 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.602277988 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:50 PM PDT 24 557561260 ps
T121 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.756540853 Apr 18 12:43:53 PM PDT 24 Apr 18 12:43:55 PM PDT 24 371092136 ps
T851 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3892058581 Apr 18 12:43:37 PM PDT 24 Apr 18 12:43:46 PM PDT 24 8533401604 ps
T852 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1379742965 Apr 18 12:43:54 PM PDT 24 Apr 18 12:43:56 PM PDT 24 453466272 ps
T853 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.642543459 Apr 18 12:43:52 PM PDT 24 Apr 18 12:43:54 PM PDT 24 304431831 ps
T854 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.499209397 Apr 18 12:43:28 PM PDT 24 Apr 18 12:43:32 PM PDT 24 2857884853 ps
T855 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1622363035 Apr 18 12:43:30 PM PDT 24 Apr 18 12:43:33 PM PDT 24 527106399 ps
T122 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1151054690 Apr 18 12:43:37 PM PDT 24 Apr 18 12:43:40 PM PDT 24 379273815 ps
T856 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3379497316 Apr 18 12:43:37 PM PDT 24 Apr 18 12:43:40 PM PDT 24 367432938 ps
T857 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1891651400 Apr 18 12:43:38 PM PDT 24 Apr 18 12:43:46 PM PDT 24 4166947245 ps
T858 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2817926443 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:46 PM PDT 24 1869333554 ps
T859 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2088769630 Apr 18 12:43:24 PM PDT 24 Apr 18 12:43:27 PM PDT 24 469027927 ps
T860 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2378971243 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:52 PM PDT 24 3902526759 ps
T861 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.851195678 Apr 18 12:43:46 PM PDT 24 Apr 18 12:43:48 PM PDT 24 333700771 ps
T862 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1797748357 Apr 18 12:43:28 PM PDT 24 Apr 18 12:43:31 PM PDT 24 514541958 ps
T863 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.974839953 Apr 18 12:43:51 PM PDT 24 Apr 18 12:43:53 PM PDT 24 333059623 ps
T864 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1049744261 Apr 18 12:43:53 PM PDT 24 Apr 18 12:43:55 PM PDT 24 436383838 ps
T865 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2418442420 Apr 18 12:43:45 PM PDT 24 Apr 18 12:43:49 PM PDT 24 392978809 ps
T866 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2256182269 Apr 18 12:43:38 PM PDT 24 Apr 18 12:43:42 PM PDT 24 804042464 ps
T867 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1772240173 Apr 18 12:43:39 PM PDT 24 Apr 18 12:43:53 PM PDT 24 7930782459 ps
T868 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1144350219 Apr 18 12:43:55 PM PDT 24 Apr 18 12:43:57 PM PDT 24 471764102 ps
T123 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1471607380 Apr 18 12:43:27 PM PDT 24 Apr 18 12:43:32 PM PDT 24 1008917794 ps
T869 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2779671076 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:49 PM PDT 24 431080626 ps
T870 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3282994878 Apr 18 12:43:37 PM PDT 24 Apr 18 12:43:39 PM PDT 24 580037017 ps
T871 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1537665095 Apr 18 12:43:26 PM PDT 24 Apr 18 12:43:30 PM PDT 24 881982910 ps
T872 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1334095637 Apr 18 12:43:27 PM PDT 24 Apr 18 12:43:33 PM PDT 24 523563374 ps
T873 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1863181796 Apr 18 12:43:35 PM PDT 24 Apr 18 12:43:47 PM PDT 24 4174712987 ps
T874 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3670003254 Apr 18 12:43:44 PM PDT 24 Apr 18 12:43:46 PM PDT 24 426450673 ps
T875 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2431893253 Apr 18 12:43:35 PM PDT 24 Apr 18 12:43:37 PM PDT 24 490033293 ps
T126 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1442988273 Apr 18 12:43:30 PM PDT 24 Apr 18 12:43:33 PM PDT 24 489390051 ps
T876 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2447560544 Apr 18 12:43:36 PM PDT 24 Apr 18 12:43:38 PM PDT 24 521475469 ps
T877 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2817291386 Apr 18 12:43:55 PM PDT 24 Apr 18 12:43:59 PM PDT 24 534398193 ps
T878 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1626165357 Apr 18 12:44:11 PM PDT 24 Apr 18 12:44:14 PM PDT 24 592279979 ps
T879 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.274172697 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:49 PM PDT 24 544867080 ps
T880 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.823864711 Apr 18 12:43:27 PM PDT 24 Apr 18 12:43:31 PM PDT 24 666869670 ps
T881 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1825188501 Apr 18 12:43:25 PM PDT 24 Apr 18 12:43:27 PM PDT 24 379977651 ps
T882 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3641454667 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:49 PM PDT 24 421576416 ps
T883 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.391442881 Apr 18 12:43:53 PM PDT 24 Apr 18 12:43:54 PM PDT 24 445629779 ps
T884 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.845734505 Apr 18 12:44:06 PM PDT 24 Apr 18 12:44:25 PM PDT 24 26879122650 ps
T885 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.724616051 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:48 PM PDT 24 543017903 ps
T124 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3049918453 Apr 18 12:43:29 PM PDT 24 Apr 18 12:44:55 PM PDT 24 39920815524 ps
T886 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1231912885 Apr 18 12:43:35 PM PDT 24 Apr 18 12:43:49 PM PDT 24 8270878875 ps
T887 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.865409119 Apr 18 12:43:26 PM PDT 24 Apr 18 12:43:28 PM PDT 24 354941109 ps
T888 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1884335979 Apr 18 12:43:41 PM PDT 24 Apr 18 12:43:43 PM PDT 24 376018110 ps
T889 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3389336899 Apr 18 12:43:35 PM PDT 24 Apr 18 12:43:44 PM PDT 24 4467570943 ps
T890 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4007923524 Apr 18 12:43:36 PM PDT 24 Apr 18 12:43:41 PM PDT 24 590173193 ps
T891 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1755564850 Apr 18 12:43:53 PM PDT 24 Apr 18 12:43:55 PM PDT 24 619241974 ps
T892 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1277281529 Apr 18 12:43:50 PM PDT 24 Apr 18 12:43:52 PM PDT 24 421141108 ps
T893 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1172831902 Apr 18 12:43:28 PM PDT 24 Apr 18 12:45:20 PM PDT 24 53469394024 ps
T894 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.36343802 Apr 18 12:43:42 PM PDT 24 Apr 18 12:43:45 PM PDT 24 602784312 ps
T125 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2821630853 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:43 PM PDT 24 480674111 ps
T895 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3699987863 Apr 18 12:43:42 PM PDT 24 Apr 18 12:43:44 PM PDT 24 368323951 ps
T896 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.788019262 Apr 18 12:43:38 PM PDT 24 Apr 18 12:43:43 PM PDT 24 469939050 ps
T897 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.329784286 Apr 18 12:43:43 PM PDT 24 Apr 18 12:43:46 PM PDT 24 480145889 ps
T898 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.4120728996 Apr 18 12:43:42 PM PDT 24 Apr 18 12:43:44 PM PDT 24 367165833 ps
T899 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.847292182 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:44 PM PDT 24 365148924 ps
T900 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2087083232 Apr 18 12:43:43 PM PDT 24 Apr 18 12:43:45 PM PDT 24 462600735 ps
T901 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2611638347 Apr 18 12:43:30 PM PDT 24 Apr 18 12:43:33 PM PDT 24 418661546 ps
T902 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4199002233 Apr 18 12:43:28 PM PDT 24 Apr 18 12:43:31 PM PDT 24 417713761 ps
T903 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2532196694 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:51 PM PDT 24 4141565789 ps
T904 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.760661446 Apr 18 12:43:51 PM PDT 24 Apr 18 12:43:52 PM PDT 24 553184951 ps
T905 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.644889477 Apr 18 12:43:41 PM PDT 24 Apr 18 12:43:52 PM PDT 24 2661036287 ps
T906 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3415642023 Apr 18 12:43:36 PM PDT 24 Apr 18 12:43:41 PM PDT 24 483046008 ps
T907 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.600636489 Apr 18 12:43:49 PM PDT 24 Apr 18 12:43:54 PM PDT 24 631479001 ps
T908 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2355472080 Apr 18 12:43:51 PM PDT 24 Apr 18 12:43:53 PM PDT 24 490228487 ps
T909 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3515266648 Apr 18 12:43:28 PM PDT 24 Apr 18 12:43:32 PM PDT 24 609284008 ps
T910 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4234039441 Apr 18 12:43:47 PM PDT 24 Apr 18 12:43:51 PM PDT 24 2099904237 ps
T911 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4021608480 Apr 18 12:43:54 PM PDT 24 Apr 18 12:43:57 PM PDT 24 421129956 ps
T73 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4275136277 Apr 18 12:43:53 PM PDT 24 Apr 18 12:44:14 PM PDT 24 7937195288 ps
T912 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.45340414 Apr 18 12:44:00 PM PDT 24 Apr 18 12:44:03 PM PDT 24 470795831 ps
T913 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2966496162 Apr 18 12:43:37 PM PDT 24 Apr 18 12:43:42 PM PDT 24 3996426469 ps
T914 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1063963828 Apr 18 12:43:45 PM PDT 24 Apr 18 12:43:47 PM PDT 24 518375011 ps
T915 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2702938931 Apr 18 12:43:40 PM PDT 24 Apr 18 12:43:42 PM PDT 24 574675118 ps
T916 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1947870605 Apr 18 12:43:55 PM PDT 24 Apr 18 12:43:56 PM PDT 24 540040447 ps

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1709264183
Short name T7
Test name
Test status
Simulation time 527331785631 ps
CPU time 286.62 seconds
Started Apr 18 12:47:29 PM PDT 24
Finished Apr 18 12:52:17 PM PDT 24
Peak memory 202252 kb
Host smart-1dc0a614-bcbf-48dd-8c4d-0772c193a100
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709264183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1709264183
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.717558575
Short name T16
Test name
Test status
Simulation time 355255080904 ps
CPU time 299.91 seconds
Started Apr 18 12:52:08 PM PDT 24
Finished Apr 18 12:57:08 PM PDT 24
Peak memory 210872 kb
Host smart-49a9e791-111a-4ff0-ad15-323a5c35718f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717558575 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.717558575
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1246588499
Short name T49
Test name
Test status
Simulation time 453872555614 ps
CPU time 510.64 seconds
Started Apr 18 12:48:04 PM PDT 24
Finished Apr 18 12:56:35 PM PDT 24
Peak memory 202548 kb
Host smart-141e8530-2a6f-4cba-84d9-ca2f8fb5b4f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246588499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1246588499
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2139880019
Short name T139
Test name
Test status
Simulation time 491897101417 ps
CPU time 290.69 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:52:11 PM PDT 24
Peak memory 202256 kb
Host smart-49cc9564-be1c-4a51-b38f-43fa20d8f37b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139880019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2139880019
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1980035844
Short name T10
Test name
Test status
Simulation time 495424125423 ps
CPU time 553.99 seconds
Started Apr 18 12:46:54 PM PDT 24
Finished Apr 18 12:56:09 PM PDT 24
Peak memory 202232 kb
Host smart-82f48b58-6576-448d-ac25-46e0ba9211eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980035844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1980035844
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.4114765756
Short name T153
Test name
Test status
Simulation time 488339998701 ps
CPU time 1079.58 seconds
Started Apr 18 12:48:16 PM PDT 24
Finished Apr 18 01:06:16 PM PDT 24
Peak memory 202312 kb
Host smart-b146f42b-4492-4ef5-adce-45e8b22f3ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114765756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.4114765756
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.571969077
Short name T143
Test name
Test status
Simulation time 527525719074 ps
CPU time 354.94 seconds
Started Apr 18 12:50:48 PM PDT 24
Finished Apr 18 12:56:43 PM PDT 24
Peak memory 202240 kb
Host smart-6620cf4e-9bcf-45d6-9bb7-a0cbdc611868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571969077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.571969077
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3275964150
Short name T142
Test name
Test status
Simulation time 503022235621 ps
CPU time 562.06 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:56:38 PM PDT 24
Peak memory 202216 kb
Host smart-01af286f-b530-48d9-b9bf-ab0d1e030e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275964150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3275964150
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3412823572
Short name T265
Test name
Test status
Simulation time 669370580160 ps
CPU time 355.38 seconds
Started Apr 18 12:51:51 PM PDT 24
Finished Apr 18 12:57:47 PM PDT 24
Peak memory 202332 kb
Host smart-c8db9050-235c-4fa5-8fbb-4367e7f7ad9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412823572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3412823572
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4145000043
Short name T62
Test name
Test status
Simulation time 909053703 ps
CPU time 2.8 seconds
Started Apr 18 12:43:33 PM PDT 24
Finished Apr 18 12:43:37 PM PDT 24
Peak memory 217680 kb
Host smart-47690c16-33aa-4ef9-894e-8b75c48a8dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145000043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.4145000043
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.4108392067
Short name T151
Test name
Test status
Simulation time 497980264776 ps
CPU time 571.44 seconds
Started Apr 18 12:49:47 PM PDT 24
Finished Apr 18 12:59:19 PM PDT 24
Peak memory 202252 kb
Host smart-a775230c-3d27-4ad4-ab5d-ab93e3991c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108392067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.4108392067
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3917382924
Short name T189
Test name
Test status
Simulation time 494555166623 ps
CPU time 494.01 seconds
Started Apr 18 12:48:06 PM PDT 24
Finished Apr 18 12:56:21 PM PDT 24
Peak memory 202264 kb
Host smart-36bbbd34-c48e-4c27-99a4-0c26bc0c2838
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917382924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3917382924
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3114466464
Short name T275
Test name
Test status
Simulation time 529348124627 ps
CPU time 321.49 seconds
Started Apr 18 12:47:16 PM PDT 24
Finished Apr 18 12:52:39 PM PDT 24
Peak memory 202304 kb
Host smart-2b86252b-7635-403e-b002-0289598cbe57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114466464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3114466464
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2278549501
Short name T11
Test name
Test status
Simulation time 412585635984 ps
CPU time 942.29 seconds
Started Apr 18 12:48:31 PM PDT 24
Finished Apr 18 01:04:14 PM PDT 24
Peak memory 202192 kb
Host smart-368bb1f1-254e-4b53-b34a-095acf630637
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278549501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2278549501
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3474382522
Short name T149
Test name
Test status
Simulation time 528984309 ps
CPU time 1.68 seconds
Started Apr 18 12:47:05 PM PDT 24
Finished Apr 18 12:47:08 PM PDT 24
Peak memory 201848 kb
Host smart-b32cd14e-a314-405f-a9d7-1c7299c9e3e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474382522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3474382522
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2259293662
Short name T82
Test name
Test status
Simulation time 543542659642 ps
CPU time 172.52 seconds
Started Apr 18 12:47:07 PM PDT 24
Finished Apr 18 12:50:00 PM PDT 24
Peak memory 202284 kb
Host smart-29259655-c684-4b4d-97bd-cef108b14e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259293662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2259293662
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1595648235
Short name T118
Test name
Test status
Simulation time 18203206040 ps
CPU time 26 seconds
Started Apr 18 12:43:30 PM PDT 24
Finished Apr 18 12:43:57 PM PDT 24
Peak memory 201664 kb
Host smart-a6972171-9a39-4c18-aeee-919ef603d80f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595648235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1595648235
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3014857781
Short name T75
Test name
Test status
Simulation time 7526433577 ps
CPU time 9.11 seconds
Started Apr 18 12:46:55 PM PDT 24
Finished Apr 18 12:47:05 PM PDT 24
Peak memory 218760 kb
Host smart-902bf8ce-ced3-491f-bcd2-fda5bd3d0fb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014857781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3014857781
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2929006762
Short name T150
Test name
Test status
Simulation time 565319603379 ps
CPU time 618.45 seconds
Started Apr 18 12:47:46 PM PDT 24
Finished Apr 18 12:58:05 PM PDT 24
Peak memory 202228 kb
Host smart-65b353f6-4133-472e-8586-896f1d71d681
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929006762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2929006762
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1229957550
Short name T277
Test name
Test status
Simulation time 594829005336 ps
CPU time 888.98 seconds
Started Apr 18 12:47:08 PM PDT 24
Finished Apr 18 01:01:58 PM PDT 24
Peak memory 202224 kb
Host smart-ce09b328-25b7-4801-a069-96db610740d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229957550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1229957550
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.545794009
Short name T81
Test name
Test status
Simulation time 536803064228 ps
CPU time 1239.45 seconds
Started Apr 18 12:47:07 PM PDT 24
Finished Apr 18 01:07:48 PM PDT 24
Peak memory 202232 kb
Host smart-ae5996df-aea3-48ba-807f-cb01becfabd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545794009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.545794009
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3546145877
Short name T24
Test name
Test status
Simulation time 171748413047 ps
CPU time 166.48 seconds
Started Apr 18 12:52:32 PM PDT 24
Finished Apr 18 12:55:19 PM PDT 24
Peak memory 210856 kb
Host smart-24fc5113-fcc5-43fe-9dea-ea6c234df9ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546145877 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3546145877
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4273220595
Short name T20
Test name
Test status
Simulation time 33352360925 ps
CPU time 83.41 seconds
Started Apr 18 12:49:51 PM PDT 24
Finished Apr 18 12:51:15 PM PDT 24
Peak memory 210780 kb
Host smart-af8b7477-0b80-46e3-ae21-021ff7887e6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273220595 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4273220595
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.133923271
Short name T50
Test name
Test status
Simulation time 360775546977 ps
CPU time 235.4 seconds
Started Apr 18 12:48:23 PM PDT 24
Finished Apr 18 12:52:19 PM PDT 24
Peak memory 202344 kb
Host smart-b1805e52-8913-4438-9877-aa4a749b7014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133923271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
133923271
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3918034996
Short name T161
Test name
Test status
Simulation time 364950588820 ps
CPU time 80.55 seconds
Started Apr 18 12:52:03 PM PDT 24
Finished Apr 18 12:53:24 PM PDT 24
Peak memory 202168 kb
Host smart-8642049d-55e9-4f6c-af73-e06f681721e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918034996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3918034996
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1728715657
Short name T304
Test name
Test status
Simulation time 660915588457 ps
CPU time 732.31 seconds
Started Apr 18 12:52:30 PM PDT 24
Finished Apr 18 01:04:43 PM PDT 24
Peak memory 202332 kb
Host smart-2fb900ec-973f-405f-bebd-0a6e5bb7716f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728715657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1728715657
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.177083708
Short name T278
Test name
Test status
Simulation time 506998477431 ps
CPU time 1177.05 seconds
Started Apr 18 12:47:34 PM PDT 24
Finished Apr 18 01:07:13 PM PDT 24
Peak memory 202244 kb
Host smart-05adc5b3-2410-41b1-b3f6-e2f93465e37f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177083708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.177083708
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3610356016
Short name T344
Test name
Test status
Simulation time 486295062625 ps
CPU time 381.15 seconds
Started Apr 18 12:52:42 PM PDT 24
Finished Apr 18 12:59:04 PM PDT 24
Peak memory 210716 kb
Host smart-3d34f235-566f-4dbb-9ae6-de0885941ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610356016 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3610356016
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3022837336
Short name T248
Test name
Test status
Simulation time 510940282264 ps
CPU time 1081.8 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 01:05:06 PM PDT 24
Peak memory 202156 kb
Host smart-f2d5a0ab-ba8c-4492-bd08-41812113c089
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022837336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3022837336
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3867736839
Short name T32
Test name
Test status
Simulation time 341078710712 ps
CPU time 486.15 seconds
Started Apr 18 12:51:38 PM PDT 24
Finished Apr 18 12:59:45 PM PDT 24
Peak memory 202220 kb
Host smart-a290c03a-0dd5-4ecd-88f0-cea2dbca222e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867736839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3867736839
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1644875259
Short name T25
Test name
Test status
Simulation time 598749905059 ps
CPU time 459.07 seconds
Started Apr 18 12:50:41 PM PDT 24
Finished Apr 18 12:58:21 PM PDT 24
Peak memory 219000 kb
Host smart-b7d29a69-18f6-4889-aa0e-e434ae9289d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644875259 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1644875259
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3744086087
Short name T255
Test name
Test status
Simulation time 335085212544 ps
CPU time 167.14 seconds
Started Apr 18 12:49:02 PM PDT 24
Finished Apr 18 12:51:49 PM PDT 24
Peak memory 202260 kb
Host smart-ec00d783-3207-4323-a2cd-07666f245e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744086087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3744086087
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4222476450
Short name T372
Test name
Test status
Simulation time 8196187525 ps
CPU time 7.61 seconds
Started Apr 18 12:43:41 PM PDT 24
Finished Apr 18 12:43:50 PM PDT 24
Peak memory 201460 kb
Host smart-be3597cf-cd20-4b70-98ff-986b851fc63a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222476450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.4222476450
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1091676990
Short name T154
Test name
Test status
Simulation time 183005303337 ps
CPU time 105.42 seconds
Started Apr 18 12:48:32 PM PDT 24
Finished Apr 18 12:50:19 PM PDT 24
Peak memory 202180 kb
Host smart-f2323696-6df6-4576-95db-6856cf4b3f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091676990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1091676990
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2356513244
Short name T264
Test name
Test status
Simulation time 330693723743 ps
CPU time 209.87 seconds
Started Apr 18 12:47:13 PM PDT 24
Finished Apr 18 12:50:44 PM PDT 24
Peak memory 202320 kb
Host smart-a67e2925-55db-44b6-b112-a4ae0536fd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356513244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2356513244
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.243380604
Short name T35
Test name
Test status
Simulation time 389261518768 ps
CPU time 253.32 seconds
Started Apr 18 12:48:03 PM PDT 24
Finished Apr 18 12:52:17 PM PDT 24
Peak memory 210520 kb
Host smart-1095757c-a5e7-491c-898d-7bb712444b72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243380604 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.243380604
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.108971049
Short name T129
Test name
Test status
Simulation time 378608270 ps
CPU time 1.55 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 201104 kb
Host smart-faeeea11-d48c-4234-b223-6d90ee58d074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108971049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.108971049
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2532255259
Short name T42
Test name
Test status
Simulation time 53891839681 ps
CPU time 120.27 seconds
Started Apr 18 12:47:44 PM PDT 24
Finished Apr 18 12:49:45 PM PDT 24
Peak memory 210444 kb
Host smart-efdbc3c8-1fe9-4391-93d1-fa8d4e6219ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532255259 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2532255259
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3235279262
Short name T299
Test name
Test status
Simulation time 591046578839 ps
CPU time 870.94 seconds
Started Apr 18 12:47:09 PM PDT 24
Finished Apr 18 01:01:40 PM PDT 24
Peak memory 202184 kb
Host smart-81f69ec1-5753-4c8c-906e-04553a8489d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235279262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3235279262
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3956048746
Short name T279
Test name
Test status
Simulation time 608401364868 ps
CPU time 368.96 seconds
Started Apr 18 12:47:56 PM PDT 24
Finished Apr 18 12:54:07 PM PDT 24
Peak memory 202224 kb
Host smart-b0e4d931-40ac-48ce-917a-7098c61e6a13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956048746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3956048746
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1542530158
Short name T183
Test name
Test status
Simulation time 540011613866 ps
CPU time 200.17 seconds
Started Apr 18 12:47:56 PM PDT 24
Finished Apr 18 12:51:19 PM PDT 24
Peak memory 202228 kb
Host smart-6715d66e-c8bf-4719-b91a-aa94f2b37e12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542530158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1542530158
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3794642298
Short name T290
Test name
Test status
Simulation time 164013452312 ps
CPU time 365.21 seconds
Started Apr 18 12:48:11 PM PDT 24
Finished Apr 18 12:54:17 PM PDT 24
Peak memory 202252 kb
Host smart-b155422e-d0c0-47d9-99fe-756d80530ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794642298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3794642298
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1909052352
Short name T283
Test name
Test status
Simulation time 492263400602 ps
CPU time 1008.67 seconds
Started Apr 18 12:50:37 PM PDT 24
Finished Apr 18 01:07:26 PM PDT 24
Peak memory 202248 kb
Host smart-abbc8c4f-892c-43ca-b8b8-9cfb8c1dd4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909052352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1909052352
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3346468317
Short name T269
Test name
Test status
Simulation time 225545680353 ps
CPU time 124.38 seconds
Started Apr 18 12:48:39 PM PDT 24
Finished Apr 18 12:50:44 PM PDT 24
Peak memory 202324 kb
Host smart-14fa7252-ff54-458a-a1cc-85bbcd823951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346468317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3346468317
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1461539192
Short name T380
Test name
Test status
Simulation time 101844110281 ps
CPU time 542.33 seconds
Started Apr 18 12:47:59 PM PDT 24
Finished Apr 18 12:57:02 PM PDT 24
Peak memory 202768 kb
Host smart-83273be8-8759-4187-9c24-3091b43e6757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461539192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1461539192
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2544155195
Short name T138
Test name
Test status
Simulation time 503746870818 ps
CPU time 1214.38 seconds
Started Apr 18 12:47:57 PM PDT 24
Finished Apr 18 01:08:13 PM PDT 24
Peak memory 202240 kb
Host smart-967ab12f-6d82-4373-bf80-c4821ad96894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544155195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2544155195
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2788611730
Short name T349
Test name
Test status
Simulation time 508712501335 ps
CPU time 322.73 seconds
Started Apr 18 12:51:40 PM PDT 24
Finished Apr 18 12:57:03 PM PDT 24
Peak memory 202132 kb
Host smart-b7526501-5c1a-493f-80bd-38ecc174a854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788611730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2788611730
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1203060331
Short name T267
Test name
Test status
Simulation time 485349232254 ps
CPU time 254.53 seconds
Started Apr 18 12:48:06 PM PDT 24
Finished Apr 18 12:52:21 PM PDT 24
Peak memory 202164 kb
Host smart-da997e76-c73a-45ba-b17d-d64d756c296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203060331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1203060331
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1223020033
Short name T280
Test name
Test status
Simulation time 558049912598 ps
CPU time 404 seconds
Started Apr 18 12:47:37 PM PDT 24
Finished Apr 18 12:54:22 PM PDT 24
Peak memory 202220 kb
Host smart-1c46cb79-b9b4-461c-8cf6-249a932cbe28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223020033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1223020033
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3480910893
Short name T335
Test name
Test status
Simulation time 324468592333 ps
CPU time 726.91 seconds
Started Apr 18 12:47:28 PM PDT 24
Finished Apr 18 12:59:35 PM PDT 24
Peak memory 202196 kb
Host smart-34442240-9bbd-4f00-bbc0-4287ddba94a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480910893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3480910893
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2113853975
Short name T173
Test name
Test status
Simulation time 495274243242 ps
CPU time 549.39 seconds
Started Apr 18 12:47:40 PM PDT 24
Finished Apr 18 12:56:50 PM PDT 24
Peak memory 202188 kb
Host smart-cc760207-664c-40ab-9b23-b762ac29f6c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113853975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2113853975
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1241246969
Short name T352
Test name
Test status
Simulation time 337791343504 ps
CPU time 790.08 seconds
Started Apr 18 12:47:36 PM PDT 24
Finished Apr 18 01:00:48 PM PDT 24
Peak memory 202304 kb
Host smart-e657eff6-7043-474a-8705-3537673314d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241246969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1241246969
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.36970833
Short name T356
Test name
Test status
Simulation time 249956114826 ps
CPU time 307.48 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 12:52:11 PM PDT 24
Peak memory 202160 kb
Host smart-cd4e254c-03d1-4dcf-b9c9-00f79cf4cdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36970833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.36970833
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1159998450
Short name T266
Test name
Test status
Simulation time 352387822823 ps
CPU time 708.93 seconds
Started Apr 18 12:48:27 PM PDT 24
Finished Apr 18 01:00:17 PM PDT 24
Peak memory 202216 kb
Host smart-ccbbe90c-a894-4fdc-9ffe-6b48c3af0420
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159998450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1159998450
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2927105702
Short name T245
Test name
Test status
Simulation time 120686104042 ps
CPU time 435.04 seconds
Started Apr 18 12:48:06 PM PDT 24
Finished Apr 18 12:55:22 PM PDT 24
Peak memory 202500 kb
Host smart-a05741b8-66d3-4bb8-98ae-20d7ef44b425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927105702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2927105702
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2270045391
Short name T326
Test name
Test status
Simulation time 162080901593 ps
CPU time 188.04 seconds
Started Apr 18 12:49:18 PM PDT 24
Finished Apr 18 12:52:27 PM PDT 24
Peak memory 202188 kb
Host smart-18fc3e07-c79a-437d-a563-722ec2de46f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270045391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2270045391
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2088769630
Short name T859
Test name
Test status
Simulation time 469027927 ps
CPU time 2 seconds
Started Apr 18 12:43:24 PM PDT 24
Finished Apr 18 12:43:27 PM PDT 24
Peak memory 201472 kb
Host smart-1ff8ec92-4336-4d07-a463-992f6ee7d9c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088769630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2088769630
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2268864668
Short name T86
Test name
Test status
Simulation time 45487669331 ps
CPU time 91.37 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:48:50 PM PDT 24
Peak memory 213992 kb
Host smart-329497d0-4fb6-41ab-b610-7ebf7b97fbe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268864668 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2268864668
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3707300260
Short name T358
Test name
Test status
Simulation time 362508200841 ps
CPU time 395.27 seconds
Started Apr 18 12:48:42 PM PDT 24
Finished Apr 18 12:55:19 PM PDT 24
Peak memory 202260 kb
Host smart-b5ec5f75-e42c-4166-8244-b927d705fae4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707300260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3707300260
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2473634725
Short name T305
Test name
Test status
Simulation time 365367581835 ps
CPU time 767.49 seconds
Started Apr 18 12:49:44 PM PDT 24
Finished Apr 18 01:02:32 PM PDT 24
Peak memory 202296 kb
Host smart-5f34592f-dc24-4da1-a938-a39fa394beac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473634725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2473634725
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1198246792
Short name T340
Test name
Test status
Simulation time 649797794204 ps
CPU time 1533.57 seconds
Started Apr 18 12:51:08 PM PDT 24
Finished Apr 18 01:16:42 PM PDT 24
Peak memory 202624 kb
Host smart-6816f945-73c3-4cb4-8316-9f76bffd43e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198246792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1198246792
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.807387857
Short name T374
Test name
Test status
Simulation time 9193338598 ps
CPU time 4.14 seconds
Started Apr 18 12:43:41 PM PDT 24
Finished Apr 18 12:43:47 PM PDT 24
Peak memory 201348 kb
Host smart-862ac6b9-ed64-4453-8ed1-05897a505ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807387857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.807387857
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3101688521
Short name T328
Test name
Test status
Simulation time 193502786087 ps
CPU time 436.43 seconds
Started Apr 18 12:46:54 PM PDT 24
Finished Apr 18 12:54:11 PM PDT 24
Peak memory 202304 kb
Host smart-3bbdd5cb-414c-4acb-b0d8-13c311abc8f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101688521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3101688521
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1218782336
Short name T284
Test name
Test status
Simulation time 168680309206 ps
CPU time 357.18 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 12:53:00 PM PDT 24
Peak memory 202168 kb
Host smart-dbe462e7-6adb-4ea7-8b22-67367a594420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218782336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1218782336
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2081306007
Short name T348
Test name
Test status
Simulation time 195477881275 ps
CPU time 429.96 seconds
Started Apr 18 12:47:30 PM PDT 24
Finished Apr 18 12:54:41 PM PDT 24
Peak memory 202192 kb
Host smart-215a7577-9a6a-435f-b5d4-8e097f729979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081306007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2081306007
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.4133223368
Short name T182
Test name
Test status
Simulation time 494341478460 ps
CPU time 126.48 seconds
Started Apr 18 12:47:28 PM PDT 24
Finished Apr 18 12:49:35 PM PDT 24
Peak memory 202232 kb
Host smart-c40a8d5c-9174-4bb1-838e-d824e514ae08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133223368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.4133223368
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.181472620
Short name T350
Test name
Test status
Simulation time 87172597008 ps
CPU time 122.63 seconds
Started Apr 18 12:47:43 PM PDT 24
Finished Apr 18 12:49:46 PM PDT 24
Peak memory 217024 kb
Host smart-b2429ae4-d85a-4514-80b3-a3b395a7ec05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181472620 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.181472620
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1788043737
Short name T147
Test name
Test status
Simulation time 384729307330 ps
CPU time 940.21 seconds
Started Apr 18 12:48:10 PM PDT 24
Finished Apr 18 01:03:51 PM PDT 24
Peak memory 202164 kb
Host smart-5f860eb1-914a-4842-ae04-b269a8cc58f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788043737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1788043737
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1054940935
Short name T18
Test name
Test status
Simulation time 27871285064 ps
CPU time 38.88 seconds
Started Apr 18 12:48:58 PM PDT 24
Finished Apr 18 12:49:38 PM PDT 24
Peak memory 202452 kb
Host smart-9c634448-b7d7-401e-a3d2-b74153b0706e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054940935 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1054940935
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3546655562
Short name T370
Test name
Test status
Simulation time 327464552811 ps
CPU time 793.03 seconds
Started Apr 18 12:51:37 PM PDT 24
Finished Apr 18 01:04:51 PM PDT 24
Peak memory 202180 kb
Host smart-2dc56fe7-f259-4fde-a8f3-22ff15b59ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546655562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3546655562
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3495753598
Short name T329
Test name
Test status
Simulation time 372062567261 ps
CPU time 776.77 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 01:00:13 PM PDT 24
Peak memory 202308 kb
Host smart-107f8e98-d2eb-44dd-8b36-a75634407d1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495753598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3495753598
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4275136277
Short name T73
Test name
Test status
Simulation time 7937195288 ps
CPU time 20.13 seconds
Started Apr 18 12:43:53 PM PDT 24
Finished Apr 18 12:44:14 PM PDT 24
Peak memory 201436 kb
Host smart-7b2ea719-1289-4e30-a413-0321698fa6ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275136277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.4275136277
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.937343164
Short name T409
Test name
Test status
Simulation time 449000360 ps
CPU time 1.79 seconds
Started Apr 18 12:48:13 PM PDT 24
Finished Apr 18 12:48:16 PM PDT 24
Peak memory 201856 kb
Host smart-4a27587f-5724-48da-a6b4-c883928ec927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937343164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.937343164
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3726573086
Short name T314
Test name
Test status
Simulation time 176559566093 ps
CPU time 108.78 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:49:05 PM PDT 24
Peak memory 202240 kb
Host smart-8e4f5e86-c729-4ebf-8876-6fe2aedba71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726573086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3726573086
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.495846346
Short name T90
Test name
Test status
Simulation time 96258866774 ps
CPU time 314.45 seconds
Started Apr 18 12:46:57 PM PDT 24
Finished Apr 18 12:52:13 PM PDT 24
Peak memory 202504 kb
Host smart-dd027073-bb05-4a80-aad5-0e03feaf1167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495846346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.495846346
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2580657902
Short name T317
Test name
Test status
Simulation time 182583960950 ps
CPU time 220.08 seconds
Started Apr 18 12:47:05 PM PDT 24
Finished Apr 18 12:50:46 PM PDT 24
Peak memory 202304 kb
Host smart-32c5a407-7034-4788-8fc1-4422b373336d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580657902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2580657902
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2419875195
Short name T631
Test name
Test status
Simulation time 74354860336 ps
CPU time 437.29 seconds
Started Apr 18 12:47:01 PM PDT 24
Finished Apr 18 12:54:19 PM PDT 24
Peak memory 202536 kb
Host smart-b42b005f-ccbe-4c84-98aa-b5aa9668ca79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419875195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2419875195
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3987058631
Short name T710
Test name
Test status
Simulation time 95906305341 ps
CPU time 487.66 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 202440 kb
Host smart-20d0e750-dc86-4dfb-9430-b47952ec0b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987058631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3987058631
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3029114463
Short name T212
Test name
Test status
Simulation time 367029258417 ps
CPU time 283.22 seconds
Started Apr 18 12:47:23 PM PDT 24
Finished Apr 18 12:52:07 PM PDT 24
Peak memory 202212 kb
Host smart-f2f966cb-4951-4865-85bb-60cd3524fac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029114463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3029114463
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1809600581
Short name T333
Test name
Test status
Simulation time 48009531451 ps
CPU time 101.53 seconds
Started Apr 18 12:47:35 PM PDT 24
Finished Apr 18 12:49:19 PM PDT 24
Peak memory 210624 kb
Host smart-9cda5fb9-ec7a-4295-adb6-d2656fabf018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809600581 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1809600581
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1877648241
Short name T360
Test name
Test status
Simulation time 188836148522 ps
CPU time 97.78 seconds
Started Apr 18 12:47:33 PM PDT 24
Finished Apr 18 12:49:13 PM PDT 24
Peak memory 202236 kb
Host smart-be804d10-dfa4-435a-b4ad-130a14c09cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877648241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1877648241
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2415764995
Short name T241
Test name
Test status
Simulation time 97725260897 ps
CPU time 427.16 seconds
Started Apr 18 12:47:36 PM PDT 24
Finished Apr 18 12:54:45 PM PDT 24
Peak memory 202516 kb
Host smart-a68e20b9-5940-4266-bbbc-76e425ace802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415764995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2415764995
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3743661608
Short name T242
Test name
Test status
Simulation time 136741453945 ps
CPU time 484.43 seconds
Started Apr 18 12:47:53 PM PDT 24
Finished Apr 18 12:56:00 PM PDT 24
Peak memory 202528 kb
Host smart-34b4e31f-1ca1-4763-b918-2f2f4db63e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743661608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3743661608
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3352606076
Short name T297
Test name
Test status
Simulation time 330597838096 ps
CPU time 211.17 seconds
Started Apr 18 12:49:07 PM PDT 24
Finished Apr 18 12:52:39 PM PDT 24
Peak memory 202144 kb
Host smart-cd8ac28d-0240-423f-9372-5864002c3320
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352606076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3352606076
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1218373998
Short name T224
Test name
Test status
Simulation time 64057086907 ps
CPU time 245.22 seconds
Started Apr 18 12:49:08 PM PDT 24
Finished Apr 18 12:53:14 PM PDT 24
Peak memory 202592 kb
Host smart-5aec519c-b044-493e-adc9-ea87ad3aafb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218373998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1218373998
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2763963821
Short name T292
Test name
Test status
Simulation time 365512784672 ps
CPU time 230.94 seconds
Started Apr 18 12:50:06 PM PDT 24
Finished Apr 18 12:53:58 PM PDT 24
Peak memory 202156 kb
Host smart-d2d2d656-a7d4-4c59-b5ae-9f6183250c0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763963821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2763963821
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2394214832
Short name T78
Test name
Test status
Simulation time 490182297116 ps
CPU time 1183.8 seconds
Started Apr 18 12:51:28 PM PDT 24
Finished Apr 18 01:11:13 PM PDT 24
Peak memory 202300 kb
Host smart-4790f77c-5452-4b51-800b-08307b47da69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394214832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2394214832
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2668373155
Short name T379
Test name
Test status
Simulation time 105429823585 ps
CPU time 382.48 seconds
Started Apr 18 12:51:34 PM PDT 24
Finished Apr 18 12:57:57 PM PDT 24
Peak memory 202444 kb
Host smart-8759c53c-df02-411b-a159-89951f383485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668373155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2668373155
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3945588927
Short name T334
Test name
Test status
Simulation time 478839583114 ps
CPU time 1081.97 seconds
Started Apr 18 12:47:08 PM PDT 24
Finished Apr 18 01:05:11 PM PDT 24
Peak memory 201424 kb
Host smart-ffffc659-89ab-4db8-ba02-c35bd3fc963c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945588927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3945588927
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.36389871
Short name T281
Test name
Test status
Simulation time 362936459439 ps
CPU time 803.11 seconds
Started Apr 18 12:47:08 PM PDT 24
Finished Apr 18 01:00:32 PM PDT 24
Peak memory 202328 kb
Host smart-441d2c10-fc0b-4420-a26f-1e4c5fb9cfea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36389871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.36389871
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2140413818
Short name T848
Test name
Test status
Simulation time 878815539 ps
CPU time 1.74 seconds
Started Apr 18 12:43:25 PM PDT 24
Finished Apr 18 12:43:28 PM PDT 24
Peak memory 201440 kb
Host smart-30b686e3-3bf0-4db3-9666-c5d445606702
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140413818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2140413818
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1166461915
Short name T116
Test name
Test status
Simulation time 1231333747 ps
CPU time 1.4 seconds
Started Apr 18 12:43:26 PM PDT 24
Finished Apr 18 12:43:29 PM PDT 24
Peak memory 201268 kb
Host smart-bc770b3e-8412-4a2f-89cf-d696b2d79adc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166461915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1166461915
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.865409119
Short name T887
Test name
Test status
Simulation time 354941109 ps
CPU time 1.6 seconds
Started Apr 18 12:43:26 PM PDT 24
Finished Apr 18 12:43:28 PM PDT 24
Peak memory 201280 kb
Host smart-ad0d4556-bb93-4387-98fe-40037e82bc88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865409119 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.865409119
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2249098297
Short name T841
Test name
Test status
Simulation time 436145688 ps
CPU time 0.94 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:43:30 PM PDT 24
Peak memory 201116 kb
Host smart-6921330b-4976-4776-92e8-930c189e4783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249098297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2249098297
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.499209397
Short name T854
Test name
Test status
Simulation time 2857884853 ps
CPU time 2.7 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 201256 kb
Host smart-5f35032a-cce1-407c-8724-4ced94638099
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499209397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.499209397
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2608567921
Short name T57
Test name
Test status
Simulation time 4429666758 ps
CPU time 6.79 seconds
Started Apr 18 12:43:25 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201428 kb
Host smart-315ce063-f0dc-4607-90f9-b7740af72e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608567921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2608567921
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1471607380
Short name T123
Test name
Test status
Simulation time 1008917794 ps
CPU time 2.8 seconds
Started Apr 18 12:43:27 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 201404 kb
Host smart-c172f04e-b991-4b0c-bdba-d2260c2db1e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471607380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1471607380
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.107548876
Short name T115
Test name
Test status
Simulation time 43855732713 ps
CPU time 78.77 seconds
Started Apr 18 12:43:25 PM PDT 24
Finished Apr 18 12:44:45 PM PDT 24
Peak memory 201364 kb
Host smart-00a7816c-4232-476e-a5fd-1e837167ba11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107548876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.107548876
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3439428443
Short name T114
Test name
Test status
Simulation time 779280895 ps
CPU time 2.7 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 201228 kb
Host smart-226bf5ba-40b5-422c-b74f-1d6052b2cdc9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439428443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3439428443
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3515266648
Short name T909
Test name
Test status
Simulation time 609284008 ps
CPU time 2.33 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 201264 kb
Host smart-65bf5334-6741-4bdc-bfa7-b72ab410d366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515266648 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3515266648
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1825188501
Short name T881
Test name
Test status
Simulation time 379977651 ps
CPU time 1.05 seconds
Started Apr 18 12:43:25 PM PDT 24
Finished Apr 18 12:43:27 PM PDT 24
Peak memory 201224 kb
Host smart-0651c473-76cf-4741-94b8-341c263d638e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825188501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1825188501
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4169684518
Short name T825
Test name
Test status
Simulation time 434185283 ps
CPU time 1.15 seconds
Started Apr 18 12:43:26 PM PDT 24
Finished Apr 18 12:43:28 PM PDT 24
Peak memory 201220 kb
Host smart-3c0340e7-3657-4376-b81f-6dce4116c3c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169684518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.4169684518
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1539449117
Short name T838
Test name
Test status
Simulation time 5072389096 ps
CPU time 6.02 seconds
Started Apr 18 12:43:27 PM PDT 24
Finished Apr 18 12:43:34 PM PDT 24
Peak memory 201464 kb
Host smart-f634868b-f5cd-4431-b847-206a68ed8480
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539449117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1539449117
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1334095637
Short name T872
Test name
Test status
Simulation time 523563374 ps
CPU time 4.22 seconds
Started Apr 18 12:43:27 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201508 kb
Host smart-814d6961-99f4-425b-8e04-b5b59c66efc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334095637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1334095637
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2659197789
Short name T846
Test name
Test status
Simulation time 4810933048 ps
CPU time 13.5 seconds
Started Apr 18 12:43:23 PM PDT 24
Finished Apr 18 12:43:37 PM PDT 24
Peak memory 201328 kb
Host smart-d82b89b2-2b97-4e70-b12f-81c264c3847f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659197789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2659197789
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.507117721
Short name T816
Test name
Test status
Simulation time 427216341 ps
CPU time 1.13 seconds
Started Apr 18 12:43:36 PM PDT 24
Finished Apr 18 12:43:37 PM PDT 24
Peak memory 201196 kb
Host smart-c02ae28f-c9f6-463c-b616-980acd4302c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507117721 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.507117721
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2328928090
Short name T112
Test name
Test status
Simulation time 425786828 ps
CPU time 1.07 seconds
Started Apr 18 12:43:35 PM PDT 24
Finished Apr 18 12:43:36 PM PDT 24
Peak memory 201140 kb
Host smart-9511f5a5-8db1-4000-838c-829399bf6c6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328928090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2328928090
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1461288379
Short name T794
Test name
Test status
Simulation time 423485582 ps
CPU time 1.65 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 201180 kb
Host smart-572160fd-4e01-436c-ba5c-a0d73da106e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461288379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1461288379
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3042568534
Short name T55
Test name
Test status
Simulation time 2196497066 ps
CPU time 2.07 seconds
Started Apr 18 12:43:37 PM PDT 24
Finished Apr 18 12:43:40 PM PDT 24
Peak memory 201272 kb
Host smart-d446c6eb-cb95-456c-802f-65af9d7302ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042568534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3042568534
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4007923524
Short name T890
Test name
Test status
Simulation time 590173193 ps
CPU time 3.74 seconds
Started Apr 18 12:43:36 PM PDT 24
Finished Apr 18 12:43:41 PM PDT 24
Peak memory 201364 kb
Host smart-505a41d6-c28f-425d-87d4-2d26be0d7eb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007923524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4007923524
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1891651400
Short name T857
Test name
Test status
Simulation time 4166947245 ps
CPU time 6.3 seconds
Started Apr 18 12:43:38 PM PDT 24
Finished Apr 18 12:43:46 PM PDT 24
Peak memory 201472 kb
Host smart-25e73215-d377-4f08-88e4-af55e4a022c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891651400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1891651400
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.36343802
Short name T894
Test name
Test status
Simulation time 602784312 ps
CPU time 2.2 seconds
Started Apr 18 12:43:42 PM PDT 24
Finished Apr 18 12:43:45 PM PDT 24
Peak memory 201196 kb
Host smart-382c893b-293a-421e-afdb-885b8efea29d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36343802 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.36343802
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2821630853
Short name T125
Test name
Test status
Simulation time 480674111 ps
CPU time 1.51 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 201260 kb
Host smart-0579ec05-57d8-4c8f-8121-c607e8210e41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821630853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2821630853
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2447560544
Short name T876
Test name
Test status
Simulation time 521475469 ps
CPU time 1.11 seconds
Started Apr 18 12:43:36 PM PDT 24
Finished Apr 18 12:43:38 PM PDT 24
Peak memory 201212 kb
Host smart-e74c32f7-b6e5-4c40-b01d-12d474b0861d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447560544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2447560544
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2532196694
Short name T903
Test name
Test status
Simulation time 4141565789 ps
CPU time 9.87 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:51 PM PDT 24
Peak memory 201532 kb
Host smart-d3423c96-36ed-43ca-997d-1e195418ca65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532196694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2532196694
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3415642023
Short name T906
Test name
Test status
Simulation time 483046008 ps
CPU time 3.41 seconds
Started Apr 18 12:43:36 PM PDT 24
Finished Apr 18 12:43:41 PM PDT 24
Peak memory 217296 kb
Host smart-3e2a1a77-67b0-4097-b8f9-12da429001f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415642023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3415642023
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.332435983
Short name T373
Test name
Test status
Simulation time 4527761660 ps
CPU time 4.34 seconds
Started Apr 18 12:43:38 PM PDT 24
Finished Apr 18 12:43:44 PM PDT 24
Peak memory 201468 kb
Host smart-6b9b07a9-6a24-43fb-83e1-519469364cbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332435983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.332435983
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.788367212
Short name T820
Test name
Test status
Simulation time 423035576 ps
CPU time 1.46 seconds
Started Apr 18 12:43:41 PM PDT 24
Finished Apr 18 12:43:44 PM PDT 24
Peak memory 201304 kb
Host smart-f7f440f9-d311-49c4-85d6-19cc3b71e4ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788367212 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.788367212
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.126012148
Short name T128
Test name
Test status
Simulation time 469244079 ps
CPU time 0.97 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:42 PM PDT 24
Peak memory 201128 kb
Host smart-49752103-247b-490e-aee3-901abd9bd75e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126012148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.126012148
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1884335979
Short name T888
Test name
Test status
Simulation time 376018110 ps
CPU time 0.77 seconds
Started Apr 18 12:43:41 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 201064 kb
Host smart-477eb710-6e30-4e7a-8daa-1e8fe9897548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884335979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1884335979
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.644889477
Short name T905
Test name
Test status
Simulation time 2661036287 ps
CPU time 9.04 seconds
Started Apr 18 12:43:41 PM PDT 24
Finished Apr 18 12:43:52 PM PDT 24
Peak memory 201184 kb
Host smart-36c3d232-edf2-4671-90d4-0226049115ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644889477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.644889477
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3958728791
Short name T828
Test name
Test status
Simulation time 692914113 ps
CPU time 2.41 seconds
Started Apr 18 12:43:42 PM PDT 24
Finished Apr 18 12:43:46 PM PDT 24
Peak memory 217132 kb
Host smart-65bf09b4-fcb1-4b96-a074-e82003382e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958728791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3958728791
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1626165357
Short name T878
Test name
Test status
Simulation time 592279979 ps
CPU time 2.23 seconds
Started Apr 18 12:44:11 PM PDT 24
Finished Apr 18 12:44:14 PM PDT 24
Peak memory 201248 kb
Host smart-b4f3e050-49fc-400d-893e-4d35d4007f0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626165357 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1626165357
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3117792655
Short name T117
Test name
Test status
Simulation time 484896938 ps
CPU time 0.81 seconds
Started Apr 18 12:43:41 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 201220 kb
Host smart-028999d8-b3b5-4bc4-bc52-ef9c1c091640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117792655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3117792655
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.942944972
Short name T803
Test name
Test status
Simulation time 433619620 ps
CPU time 1.18 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 201140 kb
Host smart-2b1da311-f2c0-4d92-905d-53bcf201fd6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942944972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.942944972
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2378971243
Short name T860
Test name
Test status
Simulation time 3902526759 ps
CPU time 9.79 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:52 PM PDT 24
Peak memory 201332 kb
Host smart-68c74f68-8c01-4b3c-9dbf-495da61c5c00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378971243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2378971243
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.847292182
Short name T899
Test name
Test status
Simulation time 365148924 ps
CPU time 2.66 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:44 PM PDT 24
Peak memory 201368 kb
Host smart-98733206-8123-4157-9866-cea982ec4703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847292182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.847292182
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1772240173
Short name T867
Test name
Test status
Simulation time 7930782459 ps
CPU time 12.74 seconds
Started Apr 18 12:43:39 PM PDT 24
Finished Apr 18 12:43:53 PM PDT 24
Peak memory 201368 kb
Host smart-8f7da0ad-734e-44fb-add9-e3d24bb7598d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772240173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1772240173
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4012026549
Short name T61
Test name
Test status
Simulation time 662494019 ps
CPU time 1 seconds
Started Apr 18 12:43:39 PM PDT 24
Finished Apr 18 12:43:41 PM PDT 24
Peak memory 201300 kb
Host smart-baf2aad0-65f2-4177-af53-b95ebc3d043f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012026549 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4012026549
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2702938931
Short name T915
Test name
Test status
Simulation time 574675118 ps
CPU time 1.06 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:42 PM PDT 24
Peak memory 201212 kb
Host smart-a23a6388-6e5a-4b2e-a1ce-bfbb88417a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702938931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2702938931
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.4120728996
Short name T898
Test name
Test status
Simulation time 367165833 ps
CPU time 1.08 seconds
Started Apr 18 12:43:42 PM PDT 24
Finished Apr 18 12:43:44 PM PDT 24
Peak memory 201112 kb
Host smart-e78b623a-a0ce-41e0-b900-1a7a9c9cdf77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120728996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.4120728996
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2817926443
Short name T858
Test name
Test status
Simulation time 1869333554 ps
CPU time 3.91 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:46 PM PDT 24
Peak memory 201104 kb
Host smart-302153f6-0378-46b2-a85c-d513ed795ec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817926443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2817926443
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3649368679
Short name T67
Test name
Test status
Simulation time 839261728 ps
CPU time 3.39 seconds
Started Apr 18 12:43:42 PM PDT 24
Finished Apr 18 12:43:47 PM PDT 24
Peak memory 201388 kb
Host smart-a540b7a1-86ac-4dd6-a57f-f34854e24ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649368679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3649368679
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1203603305
Short name T88
Test name
Test status
Simulation time 493060554 ps
CPU time 2.06 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:44 PM PDT 24
Peak memory 201248 kb
Host smart-55a7e7ff-4dc0-4093-b4a4-2c6ce96461d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203603305 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1203603305
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1755564850
Short name T891
Test name
Test status
Simulation time 619241974 ps
CPU time 0.97 seconds
Started Apr 18 12:43:53 PM PDT 24
Finished Apr 18 12:43:55 PM PDT 24
Peak memory 201176 kb
Host smart-2780ee1c-f767-4827-9aa1-45868dcc067f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755564850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1755564850
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3670003254
Short name T874
Test name
Test status
Simulation time 426450673 ps
CPU time 1.19 seconds
Started Apr 18 12:43:44 PM PDT 24
Finished Apr 18 12:43:46 PM PDT 24
Peak memory 201188 kb
Host smart-be6a8f8a-4715-412b-a598-d4257106eb5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670003254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3670003254
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2109331695
Short name T56
Test name
Test status
Simulation time 4817763797 ps
CPU time 12.24 seconds
Started Apr 18 12:43:43 PM PDT 24
Finished Apr 18 12:43:56 PM PDT 24
Peak memory 201344 kb
Host smart-f109b4fb-2b78-455f-9898-83710915843d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109331695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2109331695
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3345733206
Short name T72
Test name
Test status
Simulation time 1730426602 ps
CPU time 1.91 seconds
Started Apr 18 12:43:52 PM PDT 24
Finished Apr 18 12:43:55 PM PDT 24
Peak memory 201476 kb
Host smart-fb5923ef-106c-46c2-ae41-e3ec9f089047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345733206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3345733206
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3802370060
Short name T834
Test name
Test status
Simulation time 4893600552 ps
CPU time 3.19 seconds
Started Apr 18 12:43:45 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 201484 kb
Host smart-b1106401-5d62-4610-b16b-561d32c0b127
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802370060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3802370060
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.329784286
Short name T897
Test name
Test status
Simulation time 480145889 ps
CPU time 2 seconds
Started Apr 18 12:43:43 PM PDT 24
Finished Apr 18 12:43:46 PM PDT 24
Peak memory 201300 kb
Host smart-0a00ed75-87c8-4e04-bf00-ab55df55b528
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329784286 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.329784286
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.756540853
Short name T121
Test name
Test status
Simulation time 371092136 ps
CPU time 1.18 seconds
Started Apr 18 12:43:53 PM PDT 24
Finished Apr 18 12:43:55 PM PDT 24
Peak memory 201204 kb
Host smart-8ee312a4-f8c6-423a-b0e1-7c2f636c9a9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756540853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.756540853
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.329278632
Short name T815
Test name
Test status
Simulation time 445844414 ps
CPU time 0.86 seconds
Started Apr 18 12:43:53 PM PDT 24
Finished Apr 18 12:43:56 PM PDT 24
Peak memory 201204 kb
Host smart-43bf6144-b4e4-4f0c-b6b9-c9f8d5c25a0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329278632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.329278632
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1647753678
Short name T849
Test name
Test status
Simulation time 4151520890 ps
CPU time 9.91 seconds
Started Apr 18 12:43:52 PM PDT 24
Finished Apr 18 12:44:03 PM PDT 24
Peak memory 201472 kb
Host smart-d5f174cc-c130-46fe-b7b3-6cec65aff03c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647753678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1647753678
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.484137830
Short name T68
Test name
Test status
Simulation time 545207759 ps
CPU time 2.71 seconds
Started Apr 18 12:44:01 PM PDT 24
Finished Apr 18 12:44:04 PM PDT 24
Peak memory 217724 kb
Host smart-c98cfee8-bcd1-4e5d-9160-8cd2bbf5d6a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484137830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.484137830
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1378694525
Short name T806
Test name
Test status
Simulation time 4283511872 ps
CPU time 11.74 seconds
Started Apr 18 12:43:52 PM PDT 24
Finished Apr 18 12:44:05 PM PDT 24
Peak memory 201432 kb
Host smart-f09f31c1-9160-4aa4-a7df-f043183d3f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378694525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1378694525
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.274172697
Short name T879
Test name
Test status
Simulation time 544867080 ps
CPU time 0.96 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 201140 kb
Host smart-062f5435-ab56-43ff-9feb-11a4464f9f06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274172697 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.274172697
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3699987863
Short name T895
Test name
Test status
Simulation time 368323951 ps
CPU time 1.11 seconds
Started Apr 18 12:43:42 PM PDT 24
Finished Apr 18 12:43:44 PM PDT 24
Peak memory 201096 kb
Host smart-2aab131a-ae66-4335-8e33-672adc5ef480
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699987863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3699987863
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.391442881
Short name T883
Test name
Test status
Simulation time 445629779 ps
CPU time 0.96 seconds
Started Apr 18 12:43:53 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 201196 kb
Host smart-330a5cf2-ee1f-4706-b436-e4ab72e4f289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391442881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.391442881
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.796554355
Short name T54
Test name
Test status
Simulation time 2165237510 ps
CPU time 7.73 seconds
Started Apr 18 12:43:44 PM PDT 24
Finished Apr 18 12:43:52 PM PDT 24
Peak memory 201292 kb
Host smart-cf696fc5-be9b-41f6-8723-f700dfc71773
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796554355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.796554355
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2418442420
Short name T865
Test name
Test status
Simulation time 392978809 ps
CPU time 3.4 seconds
Started Apr 18 12:43:45 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 201480 kb
Host smart-7c1da3dc-6b3e-443b-80a5-0a655617918d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418442420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2418442420
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.602277988
Short name T850
Test name
Test status
Simulation time 557561260 ps
CPU time 1.12 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:50 PM PDT 24
Peak memory 201300 kb
Host smart-7383e93f-dffa-4a91-a18f-3bd0b92e04ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602277988 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.602277988
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.968976726
Short name T130
Test name
Test status
Simulation time 524868733 ps
CPU time 1.37 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 201236 kb
Host smart-43fa976c-0443-4909-823f-50a264f724a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968976726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.968976726
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3641454667
Short name T882
Test name
Test status
Simulation time 421576416 ps
CPU time 1.07 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 201064 kb
Host smart-ca760ad7-be23-4497-9757-c56d36638273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641454667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3641454667
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4234039441
Short name T910
Test name
Test status
Simulation time 2099904237 ps
CPU time 2.9 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:51 PM PDT 24
Peak memory 201236 kb
Host smart-56e86917-7252-402e-b1e2-c6881108272b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234039441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.4234039441
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.600636489
Short name T907
Test name
Test status
Simulation time 631479001 ps
CPU time 3.84 seconds
Started Apr 18 12:43:49 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 201536 kb
Host smart-bf91f853-e8e6-47f6-bd48-7f984ac98126
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600636489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.600636489
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1130690583
Short name T823
Test name
Test status
Simulation time 4538209318 ps
CPU time 6.31 seconds
Started Apr 18 12:43:48 PM PDT 24
Finished Apr 18 12:43:56 PM PDT 24
Peak memory 201384 kb
Host smart-03124cf1-c184-4465-b3f3-5575fdf370c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130690583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1130690583
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2369743030
Short name T108
Test name
Test status
Simulation time 362368745 ps
CPU time 1.51 seconds
Started Apr 18 12:43:48 PM PDT 24
Finished Apr 18 12:43:51 PM PDT 24
Peak memory 201196 kb
Host smart-c94506b7-1efd-4858-a8c1-a76546146607
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369743030 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2369743030
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2420254696
Short name T829
Test name
Test status
Simulation time 300779818 ps
CPU time 1.43 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:50 PM PDT 24
Peak memory 201136 kb
Host smart-3e542373-94eb-4909-abbb-18e79b1b798a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420254696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2420254696
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1628638769
Short name T840
Test name
Test status
Simulation time 415737429 ps
CPU time 0.87 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:48 PM PDT 24
Peak memory 201232 kb
Host smart-51f56b41-ff5f-4a8f-81b9-b2691929eca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628638769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1628638769
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.931126883
Short name T819
Test name
Test status
Simulation time 2834130648 ps
CPU time 4.84 seconds
Started Apr 18 12:43:48 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 201492 kb
Host smart-47426ff5-13a0-4b42-80a4-3c43b5002ec8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931126883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.931126883
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3132904529
Short name T827
Test name
Test status
Simulation time 648900113 ps
CPU time 2.65 seconds
Started Apr 18 12:43:48 PM PDT 24
Finished Apr 18 12:43:52 PM PDT 24
Peak memory 217596 kb
Host smart-04acb5d3-1a57-452a-bb85-301a5971eeab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132904529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3132904529
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.295126322
Short name T808
Test name
Test status
Simulation time 7962235326 ps
CPU time 7.26 seconds
Started Apr 18 12:43:48 PM PDT 24
Finished Apr 18 12:43:57 PM PDT 24
Peak memory 201368 kb
Host smart-7f28fb65-78b9-4bec-b699-88ccd9b0d09e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295126322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.295126322
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.910254055
Short name T120
Test name
Test status
Simulation time 577609074 ps
CPU time 1.83 seconds
Started Apr 18 12:43:27 PM PDT 24
Finished Apr 18 12:43:30 PM PDT 24
Peak memory 201428 kb
Host smart-00806035-8155-4a84-b40c-117d17b00a59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910254055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.910254055
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.845734505
Short name T884
Test name
Test status
Simulation time 26879122650 ps
CPU time 17.57 seconds
Started Apr 18 12:44:06 PM PDT 24
Finished Apr 18 12:44:25 PM PDT 24
Peak memory 201484 kb
Host smart-4755b08a-803c-4a97-abbd-7cc865c81a6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845734505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.845734505
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4226163986
Short name T133
Test name
Test status
Simulation time 763184149 ps
CPU time 2.36 seconds
Started Apr 18 12:43:26 PM PDT 24
Finished Apr 18 12:43:30 PM PDT 24
Peak memory 201228 kb
Host smart-6d643235-d462-4a16-a3c0-546c2aaac97e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226163986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.4226163986
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3155469501
Short name T812
Test name
Test status
Simulation time 459370282 ps
CPU time 1.91 seconds
Started Apr 18 12:43:29 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201196 kb
Host smart-e1bd936c-7496-43ee-b86b-fc1bd4252371
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155469501 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3155469501
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3570942620
Short name T836
Test name
Test status
Simulation time 436391419 ps
CPU time 1.77 seconds
Started Apr 18 12:43:23 PM PDT 24
Finished Apr 18 12:43:26 PM PDT 24
Peak memory 201200 kb
Host smart-34981cd3-a064-4cec-bdfd-802bf0a8f8f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570942620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3570942620
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.665579099
Short name T810
Test name
Test status
Simulation time 389595724 ps
CPU time 0.88 seconds
Started Apr 18 12:43:24 PM PDT 24
Finished Apr 18 12:43:26 PM PDT 24
Peak memory 201204 kb
Host smart-ac60cde8-ea97-4771-86c3-6d6e9d634833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665579099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.665579099
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.439574013
Short name T835
Test name
Test status
Simulation time 2003539754 ps
CPU time 2.07 seconds
Started Apr 18 12:43:30 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201160 kb
Host smart-22719031-d62b-4d19-97b8-98b8bab46a9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439574013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.439574013
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1537665095
Short name T871
Test name
Test status
Simulation time 881982910 ps
CPU time 2.99 seconds
Started Apr 18 12:43:26 PM PDT 24
Finished Apr 18 12:43:30 PM PDT 24
Peak memory 217880 kb
Host smart-3632010a-508d-4305-b197-a358d4def585
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537665095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1537665095
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3099945620
Short name T107
Test name
Test status
Simulation time 8305966464 ps
CPU time 21.73 seconds
Started Apr 18 12:43:27 PM PDT 24
Finished Apr 18 12:43:50 PM PDT 24
Peak memory 201364 kb
Host smart-a04a2462-68aa-43e9-b62a-931603bc36ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099945620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3099945620
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.724616051
Short name T885
Test name
Test status
Simulation time 543017903 ps
CPU time 0.74 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:48 PM PDT 24
Peak memory 201112 kb
Host smart-aa671893-aa85-4111-9ffa-b2319e755dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724616051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.724616051
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2854645003
Short name T833
Test name
Test status
Simulation time 412577245 ps
CPU time 0.83 seconds
Started Apr 18 12:43:46 PM PDT 24
Finished Apr 18 12:43:48 PM PDT 24
Peak memory 201112 kb
Host smart-1c800449-2500-436e-a7eb-ea254f471422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854645003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2854645003
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2188615482
Short name T822
Test name
Test status
Simulation time 502347661 ps
CPU time 0.76 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:48 PM PDT 24
Peak memory 201104 kb
Host smart-ec8d88e3-6a80-4f8a-8f91-71df366733cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188615482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2188615482
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2779671076
Short name T869
Test name
Test status
Simulation time 431080626 ps
CPU time 0.84 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 201124 kb
Host smart-db4626f2-1a1f-451e-bd99-4fa76eb8d709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779671076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2779671076
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.70387830
Short name T824
Test name
Test status
Simulation time 499683595 ps
CPU time 1.25 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 201216 kb
Host smart-97fd4ddd-242e-42ea-954b-d15774d3f18f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70387830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.70387830
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4126733053
Short name T801
Test name
Test status
Simulation time 353781326 ps
CPU time 1.48 seconds
Started Apr 18 12:43:48 PM PDT 24
Finished Apr 18 12:43:50 PM PDT 24
Peak memory 201092 kb
Host smart-89f608f4-eb2b-440e-80fa-ec9a624e664e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126733053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.4126733053
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.851195678
Short name T861
Test name
Test status
Simulation time 333700771 ps
CPU time 1.44 seconds
Started Apr 18 12:43:46 PM PDT 24
Finished Apr 18 12:43:48 PM PDT 24
Peak memory 201092 kb
Host smart-6300a8e4-a339-40ad-b293-dbcc0fae5e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851195678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.851195678
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.323731710
Short name T843
Test name
Test status
Simulation time 408984433 ps
CPU time 0.81 seconds
Started Apr 18 12:43:49 PM PDT 24
Finished Apr 18 12:43:50 PM PDT 24
Peak memory 201224 kb
Host smart-5f454a3f-247e-44b5-8cda-21f3df4870d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323731710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.323731710
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.4054759387
Short name T795
Test name
Test status
Simulation time 371020576 ps
CPU time 0.84 seconds
Started Apr 18 12:43:47 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 201228 kb
Host smart-726405d2-bb2e-40ae-9add-8914952b60ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054759387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.4054759387
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4169809342
Short name T797
Test name
Test status
Simulation time 441277594 ps
CPU time 1.59 seconds
Started Apr 18 12:43:46 PM PDT 24
Finished Apr 18 12:43:48 PM PDT 24
Peak memory 201128 kb
Host smart-e65a5ec0-9175-44e4-9c42-503a749db733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169809342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4169809342
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1876381726
Short name T831
Test name
Test status
Simulation time 819601801 ps
CPU time 2.37 seconds
Started Apr 18 12:43:33 PM PDT 24
Finished Apr 18 12:43:36 PM PDT 24
Peak memory 201296 kb
Host smart-d622ba10-4a19-4486-9e7d-e86d8658460c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876381726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1876381726
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3049918453
Short name T124
Test name
Test status
Simulation time 39920815524 ps
CPU time 84.41 seconds
Started Apr 18 12:43:29 PM PDT 24
Finished Apr 18 12:44:55 PM PDT 24
Peak memory 201392 kb
Host smart-c5d531bf-4d9c-410f-8e90-4ca5eaf4ac55
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049918453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3049918453
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3444645555
Short name T132
Test name
Test status
Simulation time 1010920560 ps
CPU time 1.93 seconds
Started Apr 18 12:43:29 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201176 kb
Host smart-cf94339a-2a59-424a-87cf-d7353e480791
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444645555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3444645555
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.604008302
Short name T87
Test name
Test status
Simulation time 510427637 ps
CPU time 1.45 seconds
Started Apr 18 12:43:29 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201304 kb
Host smart-df11d5f3-965b-46aa-8601-a33de9124804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604008302 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.604008302
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1319794946
Short name T113
Test name
Test status
Simulation time 410108588 ps
CPU time 0.9 seconds
Started Apr 18 12:43:31 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201228 kb
Host smart-dc4f94a6-fd9b-4ae1-9218-30b3a09bbcb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319794946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1319794946
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1622363035
Short name T855
Test name
Test status
Simulation time 527106399 ps
CPU time 1.73 seconds
Started Apr 18 12:43:30 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201208 kb
Host smart-0b54202f-a0c1-4db0-a929-d78b7c9cd322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622363035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1622363035
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1226266511
Short name T832
Test name
Test status
Simulation time 2398782459 ps
CPU time 1.87 seconds
Started Apr 18 12:43:33 PM PDT 24
Finished Apr 18 12:43:36 PM PDT 24
Peak memory 201180 kb
Host smart-ed3b624c-6b1a-4ddf-8fb1-7e6e8537294d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226266511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1226266511
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2493020493
Short name T821
Test name
Test status
Simulation time 4158999050 ps
CPU time 5.23 seconds
Started Apr 18 12:43:29 PM PDT 24
Finished Apr 18 12:43:37 PM PDT 24
Peak memory 201352 kb
Host smart-442cc790-1fbe-45ed-ab61-17f5d7aae8bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493020493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2493020493
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2441725811
Short name T809
Test name
Test status
Simulation time 541482761 ps
CPU time 0.95 seconds
Started Apr 18 12:43:48 PM PDT 24
Finished Apr 18 12:43:50 PM PDT 24
Peak memory 201116 kb
Host smart-1654cdae-d8b1-4b7b-9c0b-2261fe35268c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441725811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2441725811
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.760661446
Short name T904
Test name
Test status
Simulation time 553184951 ps
CPU time 0.97 seconds
Started Apr 18 12:43:51 PM PDT 24
Finished Apr 18 12:43:52 PM PDT 24
Peak memory 201216 kb
Host smart-d8d429dc-2d56-4895-8cd0-7c51a3f3ac02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760661446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.760661446
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1957427025
Short name T813
Test name
Test status
Simulation time 432190449 ps
CPU time 1.74 seconds
Started Apr 18 12:43:53 PM PDT 24
Finished Apr 18 12:43:55 PM PDT 24
Peak memory 201120 kb
Host smart-0f368466-c4eb-4620-b120-eb59f3065bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957427025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1957427025
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.974839953
Short name T863
Test name
Test status
Simulation time 333059623 ps
CPU time 0.85 seconds
Started Apr 18 12:43:51 PM PDT 24
Finished Apr 18 12:43:53 PM PDT 24
Peak memory 201124 kb
Host smart-53f6f670-e7fa-4ae4-8d94-fb649230ac45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974839953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.974839953
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1144350219
Short name T868
Test name
Test status
Simulation time 471764102 ps
CPU time 0.95 seconds
Started Apr 18 12:43:55 PM PDT 24
Finished Apr 18 12:43:57 PM PDT 24
Peak memory 201224 kb
Host smart-eb764a73-abf0-48a1-9362-ee25eee52981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144350219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1144350219
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1049744261
Short name T864
Test name
Test status
Simulation time 436383838 ps
CPU time 1.2 seconds
Started Apr 18 12:43:53 PM PDT 24
Finished Apr 18 12:43:55 PM PDT 24
Peak memory 201104 kb
Host smart-bc63aaa2-cb62-43ec-9f50-414e82bdc25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049744261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1049744261
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2288939755
Short name T799
Test name
Test status
Simulation time 372518946 ps
CPU time 0.77 seconds
Started Apr 18 12:43:49 PM PDT 24
Finished Apr 18 12:43:51 PM PDT 24
Peak memory 201132 kb
Host smart-138d73ac-9496-4d1e-a40d-fb907ed2864c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288939755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2288939755
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1277281529
Short name T892
Test name
Test status
Simulation time 421141108 ps
CPU time 1.59 seconds
Started Apr 18 12:43:50 PM PDT 24
Finished Apr 18 12:43:52 PM PDT 24
Peak memory 201232 kb
Host smart-242679a2-aa52-49bb-b8c9-ee007cf1db0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277281529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1277281529
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4291311177
Short name T804
Test name
Test status
Simulation time 523107214 ps
CPU time 0.93 seconds
Started Apr 18 12:43:55 PM PDT 24
Finished Apr 18 12:43:58 PM PDT 24
Peak memory 201228 kb
Host smart-e1108e04-5c99-4f3c-9592-8a5ed91afb83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291311177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.4291311177
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.45340414
Short name T912
Test name
Test status
Simulation time 470795831 ps
CPU time 1.44 seconds
Started Apr 18 12:44:00 PM PDT 24
Finished Apr 18 12:44:03 PM PDT 24
Peak memory 201224 kb
Host smart-8984bf92-cb7b-4517-8694-9c82131e0b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45340414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.45340414
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.842824468
Short name T826
Test name
Test status
Simulation time 769077794 ps
CPU time 2.3 seconds
Started Apr 18 12:43:33 PM PDT 24
Finished Apr 18 12:43:36 PM PDT 24
Peak memory 201296 kb
Host smart-24031d39-0120-4e83-b24d-1e869d67082e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842824468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.842824468
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1172831902
Short name T893
Test name
Test status
Simulation time 53469394024 ps
CPU time 110.56 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:45:20 PM PDT 24
Peak memory 201492 kb
Host smart-200008df-0ba9-44b2-87c6-b9d968c95114
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172831902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1172831902
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.823864711
Short name T880
Test name
Test status
Simulation time 666869670 ps
CPU time 2.27 seconds
Started Apr 18 12:43:27 PM PDT 24
Finished Apr 18 12:43:31 PM PDT 24
Peak memory 201144 kb
Host smart-957ac7f4-d420-4a8e-b6aa-e7cc9e71dac8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823864711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.823864711
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2611638347
Short name T901
Test name
Test status
Simulation time 418661546 ps
CPU time 1.74 seconds
Started Apr 18 12:43:30 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201304 kb
Host smart-60462895-0107-4273-ab15-7e1f842a32af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611638347 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2611638347
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1442988273
Short name T126
Test name
Test status
Simulation time 489390051 ps
CPU time 1.11 seconds
Started Apr 18 12:43:30 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201228 kb
Host smart-794f6790-57a2-4eca-b8fc-bc9c18ea13aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442988273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1442988273
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1797748357
Short name T862
Test name
Test status
Simulation time 514541958 ps
CPU time 0.96 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:43:31 PM PDT 24
Peak memory 201224 kb
Host smart-799efb25-aaca-4068-86c5-6df69aa3722a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797748357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1797748357
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3951392130
Short name T127
Test name
Test status
Simulation time 2160182188 ps
CPU time 7.71 seconds
Started Apr 18 12:43:34 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 201180 kb
Host smart-25d141a9-6379-4ad2-958e-685a11265e89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951392130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3951392130
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2593009439
Short name T66
Test name
Test status
Simulation time 678916198 ps
CPU time 1.91 seconds
Started Apr 18 12:43:30 PM PDT 24
Finished Apr 18 12:43:33 PM PDT 24
Peak memory 201336 kb
Host smart-b0bbe9b0-23bd-4e96-a261-17bc5aa263bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593009439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2593009439
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3389336899
Short name T889
Test name
Test status
Simulation time 4467570943 ps
CPU time 8.08 seconds
Started Apr 18 12:43:35 PM PDT 24
Finished Apr 18 12:43:44 PM PDT 24
Peak memory 201480 kb
Host smart-d0108a43-c52d-49be-9b0d-59a03d597a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389336899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3389336899
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.642543459
Short name T853
Test name
Test status
Simulation time 304431831 ps
CPU time 1.32 seconds
Started Apr 18 12:43:52 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 201200 kb
Host smart-6a96443c-a551-474f-8485-380929d26550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642543459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.642543459
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3933904469
Short name T814
Test name
Test status
Simulation time 357386169 ps
CPU time 0.87 seconds
Started Apr 18 12:43:54 PM PDT 24
Finished Apr 18 12:43:55 PM PDT 24
Peak memory 201136 kb
Host smart-4362f78e-78fd-47fe-b353-8f95cf4a37dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933904469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3933904469
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1379742965
Short name T852
Test name
Test status
Simulation time 453466272 ps
CPU time 0.82 seconds
Started Apr 18 12:43:54 PM PDT 24
Finished Apr 18 12:43:56 PM PDT 24
Peak memory 201192 kb
Host smart-669232e9-0ecb-4ec3-980a-1cf77716f05e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379742965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1379742965
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4021608480
Short name T911
Test name
Test status
Simulation time 421129956 ps
CPU time 1.73 seconds
Started Apr 18 12:43:54 PM PDT 24
Finished Apr 18 12:43:57 PM PDT 24
Peak memory 201096 kb
Host smart-41c8368b-a1ee-4016-8934-a6064ea0340a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021608480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4021608480
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1890570087
Short name T802
Test name
Test status
Simulation time 498950474 ps
CPU time 0.93 seconds
Started Apr 18 12:43:55 PM PDT 24
Finished Apr 18 12:43:58 PM PDT 24
Peak memory 201224 kb
Host smart-fce27b92-38ed-4b1a-89a2-c3fe1503addb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890570087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1890570087
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1720771984
Short name T796
Test name
Test status
Simulation time 525511968 ps
CPU time 0.93 seconds
Started Apr 18 12:43:51 PM PDT 24
Finished Apr 18 12:43:52 PM PDT 24
Peak memory 201176 kb
Host smart-f3e074ac-34c0-4674-9c5e-51b4752271e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720771984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1720771984
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4269175932
Short name T847
Test name
Test status
Simulation time 478805029 ps
CPU time 0.73 seconds
Started Apr 18 12:43:54 PM PDT 24
Finished Apr 18 12:43:55 PM PDT 24
Peak memory 201220 kb
Host smart-819137c4-cdec-4b9f-a1cc-fce2985c29f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269175932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4269175932
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2355472080
Short name T908
Test name
Test status
Simulation time 490228487 ps
CPU time 0.88 seconds
Started Apr 18 12:43:51 PM PDT 24
Finished Apr 18 12:43:53 PM PDT 24
Peak memory 201104 kb
Host smart-66a27ebc-bfe2-4db2-8ccf-b1381f4c1765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355472080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2355472080
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1947870605
Short name T916
Test name
Test status
Simulation time 540040447 ps
CPU time 0.86 seconds
Started Apr 18 12:43:55 PM PDT 24
Finished Apr 18 12:43:56 PM PDT 24
Peak memory 201220 kb
Host smart-c99ea47a-f330-45a9-b42b-1aa0ab918f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947870605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1947870605
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2835806095
Short name T800
Test name
Test status
Simulation time 487222951 ps
CPU time 1.86 seconds
Started Apr 18 12:43:51 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 201104 kb
Host smart-fac51dcb-7483-418c-910d-31de712caf72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835806095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2835806095
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.578431169
Short name T839
Test name
Test status
Simulation time 672381381 ps
CPU time 1.35 seconds
Started Apr 18 12:43:38 PM PDT 24
Finished Apr 18 12:43:41 PM PDT 24
Peak memory 201304 kb
Host smart-835cf5ca-6f95-4186-9a79-26cff861c826
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578431169 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.578431169
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4199002233
Short name T902
Test name
Test status
Simulation time 417713761 ps
CPU time 1.01 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:43:31 PM PDT 24
Peak memory 201136 kb
Host smart-b1980305-52ff-48ea-a873-937d71a980ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199002233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4199002233
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.155198909
Short name T805
Test name
Test status
Simulation time 371709621 ps
CPU time 1.47 seconds
Started Apr 18 12:43:29 PM PDT 24
Finished Apr 18 12:43:32 PM PDT 24
Peak memory 201088 kb
Host smart-f0f80475-336e-4bf4-a209-0458ff9aeb28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155198909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.155198909
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4098486939
Short name T818
Test name
Test status
Simulation time 4389038311 ps
CPU time 15.28 seconds
Started Apr 18 12:43:28 PM PDT 24
Finished Apr 18 12:43:44 PM PDT 24
Peak memory 201524 kb
Host smart-587bd4a8-7aa9-4a88-8bd9-da07111f368f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098486939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.4098486939
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3353293459
Short name T845
Test name
Test status
Simulation time 313933665 ps
CPU time 1.93 seconds
Started Apr 18 12:43:32 PM PDT 24
Finished Apr 18 12:43:34 PM PDT 24
Peak memory 201512 kb
Host smart-2c6fc922-bd65-488e-ac45-a4044a3ceb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353293459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3353293459
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.146360988
Short name T59
Test name
Test status
Simulation time 9111706494 ps
CPU time 7.73 seconds
Started Apr 18 12:43:30 PM PDT 24
Finished Apr 18 12:43:39 PM PDT 24
Peak memory 201336 kb
Host smart-6e4ac63b-a610-4679-9496-d890904210c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146360988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.146360988
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2087083232
Short name T900
Test name
Test status
Simulation time 462600735 ps
CPU time 0.99 seconds
Started Apr 18 12:43:43 PM PDT 24
Finished Apr 18 12:43:45 PM PDT 24
Peak memory 201472 kb
Host smart-05552c53-a823-4a13-ab1d-cb27e1901848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087083232 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2087083232
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1151054690
Short name T122
Test name
Test status
Simulation time 379273815 ps
CPU time 1.34 seconds
Started Apr 18 12:43:37 PM PDT 24
Finished Apr 18 12:43:40 PM PDT 24
Peak memory 201104 kb
Host smart-3653b75c-65b8-4a1a-b824-595b57bd6962
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151054690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1151054690
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2741156223
Short name T811
Test name
Test status
Simulation time 340361126 ps
CPU time 1.48 seconds
Started Apr 18 12:43:36 PM PDT 24
Finished Apr 18 12:43:39 PM PDT 24
Peak memory 201220 kb
Host smart-8aecc3a2-fd23-449f-9bcb-d0e426b57a9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741156223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2741156223
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1863181796
Short name T873
Test name
Test status
Simulation time 4174712987 ps
CPU time 10.71 seconds
Started Apr 18 12:43:35 PM PDT 24
Finished Apr 18 12:43:47 PM PDT 24
Peak memory 201368 kb
Host smart-6e2262e3-570a-4b16-9468-d703b25e7893
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863181796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1863181796
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.788019262
Short name T896
Test name
Test status
Simulation time 469939050 ps
CPU time 2.89 seconds
Started Apr 18 12:43:38 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 217680 kb
Host smart-091af333-b19e-42f0-bd10-3568b713355e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788019262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.788019262
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1231912885
Short name T886
Test name
Test status
Simulation time 8270878875 ps
CPU time 12.24 seconds
Started Apr 18 12:43:35 PM PDT 24
Finished Apr 18 12:43:49 PM PDT 24
Peak memory 201380 kb
Host smart-9a680456-d959-431d-91ee-4545f8beed86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231912885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1231912885
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3379497316
Short name T856
Test name
Test status
Simulation time 367432938 ps
CPU time 1.55 seconds
Started Apr 18 12:43:37 PM PDT 24
Finished Apr 18 12:43:40 PM PDT 24
Peak memory 201300 kb
Host smart-2d188aa8-a0c9-467e-97df-464e9c151fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379497316 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3379497316
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.833908904
Short name T837
Test name
Test status
Simulation time 440705910 ps
CPU time 1.24 seconds
Started Apr 18 12:43:40 PM PDT 24
Finished Apr 18 12:43:43 PM PDT 24
Peak memory 201156 kb
Host smart-03654c3d-83c3-43f0-8a52-354e15084616
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833908904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.833908904
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1013118235
Short name T798
Test name
Test status
Simulation time 379374225 ps
CPU time 1.17 seconds
Started Apr 18 12:43:36 PM PDT 24
Finished Apr 18 12:43:38 PM PDT 24
Peak memory 201088 kb
Host smart-cc910d71-ab07-41e7-990a-46be6aa52eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013118235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1013118235
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1260093646
Short name T842
Test name
Test status
Simulation time 3760178537 ps
CPU time 9.41 seconds
Started Apr 18 12:43:36 PM PDT 24
Finished Apr 18 12:43:46 PM PDT 24
Peak memory 201336 kb
Host smart-9652383d-f992-48e4-84e5-fc3931c98731
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260093646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1260093646
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3808533776
Short name T844
Test name
Test status
Simulation time 582321624 ps
CPU time 3.49 seconds
Started Apr 18 12:43:39 PM PDT 24
Finished Apr 18 12:43:44 PM PDT 24
Peak memory 201368 kb
Host smart-446181be-1909-40e3-a6b8-4105f8db4bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808533776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3808533776
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2300988089
Short name T58
Test name
Test status
Simulation time 4369532791 ps
CPU time 4.23 seconds
Started Apr 18 12:43:36 PM PDT 24
Finished Apr 18 12:43:42 PM PDT 24
Peak memory 201524 kb
Host smart-7909cd5c-ae38-42d4-9044-8a848bb72dce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300988089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2300988089
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3282994878
Short name T870
Test name
Test status
Simulation time 580037017 ps
CPU time 1.11 seconds
Started Apr 18 12:43:37 PM PDT 24
Finished Apr 18 12:43:39 PM PDT 24
Peak memory 201268 kb
Host smart-6bdb88dc-cf3d-467d-8fe4-54fc4be6c2eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282994878 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3282994878
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1846821322
Short name T830
Test name
Test status
Simulation time 423501048 ps
CPU time 0.94 seconds
Started Apr 18 12:43:38 PM PDT 24
Finished Apr 18 12:43:40 PM PDT 24
Peak memory 201232 kb
Host smart-258a50cc-e8f0-42b5-9416-1b45d97a11c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846821322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1846821322
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1285044258
Short name T807
Test name
Test status
Simulation time 430459813 ps
CPU time 0.84 seconds
Started Apr 18 12:43:37 PM PDT 24
Finished Apr 18 12:43:39 PM PDT 24
Peak memory 201136 kb
Host smart-83316929-fb66-4797-b754-62b42ea57ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285044258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1285044258
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3389310770
Short name T131
Test name
Test status
Simulation time 4560782688 ps
CPU time 10.91 seconds
Started Apr 18 12:43:36 PM PDT 24
Finished Apr 18 12:43:48 PM PDT 24
Peak memory 201392 kb
Host smart-ae72bfcc-30f1-4542-9c0a-7ae3e96d3e62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389310770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3389310770
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2817291386
Short name T877
Test name
Test status
Simulation time 534398193 ps
CPU time 2.4 seconds
Started Apr 18 12:43:55 PM PDT 24
Finished Apr 18 12:43:59 PM PDT 24
Peak memory 201488 kb
Host smart-d849ea2c-695a-43d9-ac4e-41ab9aeaff3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817291386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2817291386
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3892058581
Short name T851
Test name
Test status
Simulation time 8533401604 ps
CPU time 6.73 seconds
Started Apr 18 12:43:37 PM PDT 24
Finished Apr 18 12:43:46 PM PDT 24
Peak memory 201472 kb
Host smart-33fd808f-2bc0-4ae8-a71d-cc1ddb592a60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892058581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3892058581
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2431893253
Short name T875
Test name
Test status
Simulation time 490033293 ps
CPU time 1.16 seconds
Started Apr 18 12:43:35 PM PDT 24
Finished Apr 18 12:43:37 PM PDT 24
Peak memory 201184 kb
Host smart-3f5b76cd-3911-4c94-b420-f45fd7e1665d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431893253 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2431893253
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2054790496
Short name T119
Test name
Test status
Simulation time 409126761 ps
CPU time 1.76 seconds
Started Apr 18 12:43:36 PM PDT 24
Finished Apr 18 12:43:38 PM PDT 24
Peak memory 201100 kb
Host smart-dedffe63-72d6-4263-a56e-26e338685bdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054790496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2054790496
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1063963828
Short name T914
Test name
Test status
Simulation time 518375011 ps
CPU time 1.3 seconds
Started Apr 18 12:43:45 PM PDT 24
Finished Apr 18 12:43:47 PM PDT 24
Peak memory 201424 kb
Host smart-b3cae31b-0d57-4eec-b56d-5f85e794a275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063963828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1063963828
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2966496162
Short name T913
Test name
Test status
Simulation time 3996426469 ps
CPU time 4.28 seconds
Started Apr 18 12:43:37 PM PDT 24
Finished Apr 18 12:43:42 PM PDT 24
Peak memory 201252 kb
Host smart-45095e76-cc9a-4603-a513-b6b2cd4e2994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966496162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2966496162
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2256182269
Short name T866
Test name
Test status
Simulation time 804042464 ps
CPU time 2.56 seconds
Started Apr 18 12:43:38 PM PDT 24
Finished Apr 18 12:43:42 PM PDT 24
Peak memory 201436 kb
Host smart-e46d6070-2f2a-499f-9c08-36caa67ed41b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256182269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2256182269
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1739932004
Short name T817
Test name
Test status
Simulation time 4683716680 ps
CPU time 4.31 seconds
Started Apr 18 12:43:37 PM PDT 24
Finished Apr 18 12:43:42 PM PDT 24
Peak memory 201388 kb
Host smart-8121dc5d-9131-4f4e-a182-6eccbe7443c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739932004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1739932004
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3944050242
Short name T481
Test name
Test status
Simulation time 442948273 ps
CPU time 0.89 seconds
Started Apr 18 12:46:54 PM PDT 24
Finished Apr 18 12:46:56 PM PDT 24
Peak memory 201888 kb
Host smart-5cb6b35c-a958-4fa3-90af-0e7b92213a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944050242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3944050242
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2860084267
Short name T355
Test name
Test status
Simulation time 164225718335 ps
CPU time 109.51 seconds
Started Apr 18 12:47:00 PM PDT 24
Finished Apr 18 12:48:50 PM PDT 24
Peak memory 202308 kb
Host smart-82f26658-e5f0-44a4-83f6-9ba5388641aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860084267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2860084267
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1583485770
Short name T712
Test name
Test status
Simulation time 495512956700 ps
CPU time 1232.81 seconds
Started Apr 18 12:46:55 PM PDT 24
Finished Apr 18 01:07:29 PM PDT 24
Peak memory 202176 kb
Host smart-35e467e8-32fd-4982-813b-6552cbaef7c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583485770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1583485770
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2122924412
Short name T84
Test name
Test status
Simulation time 496901227039 ps
CPU time 1181.45 seconds
Started Apr 18 12:46:55 PM PDT 24
Finished Apr 18 01:06:37 PM PDT 24
Peak memory 202192 kb
Host smart-59f499cd-c0e9-4f45-acc4-bab62053262a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122924412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2122924412
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1026737548
Short name T85
Test name
Test status
Simulation time 162585079814 ps
CPU time 365.58 seconds
Started Apr 18 12:46:54 PM PDT 24
Finished Apr 18 12:53:01 PM PDT 24
Peak memory 202196 kb
Host smart-9cbeaecc-51c8-46a4-a587-b796e2a6d284
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026737548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1026737548
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.988577122
Short name T353
Test name
Test status
Simulation time 542102010269 ps
CPU time 1176.16 seconds
Started Apr 18 12:46:55 PM PDT 24
Finished Apr 18 01:06:32 PM PDT 24
Peak memory 202240 kb
Host smart-8cb92ddb-76f1-4be9-bf73-9ade762c6f75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988577122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.988577122
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1955724446
Short name T220
Test name
Test status
Simulation time 610241495855 ps
CPU time 1427.78 seconds
Started Apr 18 12:46:56 PM PDT 24
Finished Apr 18 01:10:45 PM PDT 24
Peak memory 202284 kb
Host smart-f2d030e6-da5a-4c19-b634-828095cad66a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955724446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1955724446
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.4195745966
Short name T653
Test name
Test status
Simulation time 39985632992 ps
CPU time 15.09 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:47:20 PM PDT 24
Peak memory 202024 kb
Host smart-9ab904a6-a442-4841-bd9e-d309b59244ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195745966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.4195745966
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.604733898
Short name T715
Test name
Test status
Simulation time 5121442226 ps
CPU time 3.8 seconds
Started Apr 18 12:46:54 PM PDT 24
Finished Apr 18 12:46:59 PM PDT 24
Peak memory 201948 kb
Host smart-6a7202eb-5ff6-4c2d-abec-b3bf0517cfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604733898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.604733898
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2113730030
Short name T446
Test name
Test status
Simulation time 6119440230 ps
CPU time 5.3 seconds
Started Apr 18 12:46:56 PM PDT 24
Finished Apr 18 12:47:03 PM PDT 24
Peak memory 202068 kb
Host smart-696c7f16-77dd-4d9e-9359-ee293a53948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113730030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2113730030
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1225381821
Short name T39
Test name
Test status
Simulation time 114834657676 ps
CPU time 563.2 seconds
Started Apr 18 12:46:53 PM PDT 24
Finished Apr 18 12:56:18 PM PDT 24
Peak memory 210624 kb
Host smart-799eac8e-cff7-4e15-8b90-7a0cfab633d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225381821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1225381821
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2391422177
Short name T60
Test name
Test status
Simulation time 154582648985 ps
CPU time 455.94 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:54:41 PM PDT 24
Peak memory 211908 kb
Host smart-44be2efa-ab5e-433a-8496-cbda89f471bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391422177 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2391422177
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2005353386
Short name T738
Test name
Test status
Simulation time 509523518 ps
CPU time 0.95 seconds
Started Apr 18 12:47:05 PM PDT 24
Finished Apr 18 12:47:07 PM PDT 24
Peak memory 201968 kb
Host smart-630d6b20-33ec-4f00-8049-6eee9668943a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005353386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2005353386
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3451523931
Short name T628
Test name
Test status
Simulation time 163077521701 ps
CPU time 385.03 seconds
Started Apr 18 12:47:06 PM PDT 24
Finished Apr 18 12:53:32 PM PDT 24
Peak memory 202144 kb
Host smart-17c2b024-9fbd-42d4-8244-3ba2db42cdb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451523931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3451523931
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2119238640
Short name T666
Test name
Test status
Simulation time 322002442363 ps
CPU time 195.38 seconds
Started Apr 18 12:46:53 PM PDT 24
Finished Apr 18 12:50:10 PM PDT 24
Peak memory 202136 kb
Host smart-5c267922-909a-4732-92e9-b31ea5c7b8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119238640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2119238640
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3242381269
Short name T13
Test name
Test status
Simulation time 162704316882 ps
CPU time 244.51 seconds
Started Apr 18 12:46:57 PM PDT 24
Finished Apr 18 12:51:03 PM PDT 24
Peak memory 202200 kb
Host smart-5cc94e12-69a9-4814-9795-04f146613658
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242381269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3242381269
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3990787525
Short name T426
Test name
Test status
Simulation time 195268333272 ps
CPU time 112.43 seconds
Started Apr 18 12:47:01 PM PDT 24
Finished Apr 18 12:48:54 PM PDT 24
Peak memory 202120 kb
Host smart-57277022-a587-4f3e-ad61-78bb0f3c1951
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990787525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3990787525
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.881291685
Short name T89
Test name
Test status
Simulation time 28715898126 ps
CPU time 62.73 seconds
Started Apr 18 12:47:00 PM PDT 24
Finished Apr 18 12:48:03 PM PDT 24
Peak memory 202056 kb
Host smart-6e6f7e4e-be3b-43dc-8b5e-473b62e0c504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881291685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.881291685
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1524519016
Short name T77
Test name
Test status
Simulation time 5367923814 ps
CPU time 15.46 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:47:20 PM PDT 24
Peak memory 202040 kb
Host smart-309e3d83-75c5-40ef-a50c-18e26c735b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524519016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1524519016
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3696324279
Short name T63
Test name
Test status
Simulation time 8563626883 ps
CPU time 20.71 seconds
Started Apr 18 12:47:06 PM PDT 24
Finished Apr 18 12:47:28 PM PDT 24
Peak memory 218844 kb
Host smart-bc506f17-8f18-4912-af05-8fc2678673e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696324279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3696324279
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.688239537
Short name T483
Test name
Test status
Simulation time 5945469175 ps
CPU time 4.79 seconds
Started Apr 18 12:46:57 PM PDT 24
Finished Apr 18 12:47:04 PM PDT 24
Peak memory 202064 kb
Host smart-0c639375-56cd-4058-9253-01bdf0ebc20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688239537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.688239537
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.412063968
Short name T725
Test name
Test status
Simulation time 6557019599 ps
CPU time 6.56 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:47:11 PM PDT 24
Peak memory 202084 kb
Host smart-ab9e12fc-9166-41ea-b9c1-6053c16674eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412063968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.412063968
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3372033436
Short name T743
Test name
Test status
Simulation time 178117281544 ps
CPU time 616.37 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:57:21 PM PDT 24
Peak memory 210864 kb
Host smart-22289659-f284-4949-8b6b-97c28410e1c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372033436 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3372033436
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.394013464
Short name T424
Test name
Test status
Simulation time 305408562 ps
CPU time 0.98 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:47:20 PM PDT 24
Peak memory 201888 kb
Host smart-d9f15995-2b2a-419f-b1f8-e0f7a4d1fd39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394013464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.394013464
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1794791551
Short name T80
Test name
Test status
Simulation time 172084338976 ps
CPU time 220.54 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:51:01 PM PDT 24
Peak memory 202152 kb
Host smart-a5faf6b1-70b3-4fea-8d29-0a01ff4abe14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794791551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1794791551
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.55173413
Short name T312
Test name
Test status
Simulation time 180599416169 ps
CPU time 391.82 seconds
Started Apr 18 12:47:19 PM PDT 24
Finished Apr 18 12:53:52 PM PDT 24
Peak memory 202240 kb
Host smart-6174d7d5-fc2e-4151-98e4-5c70216b2a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55173413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.55173413
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2708330570
Short name T270
Test name
Test status
Simulation time 330138921510 ps
CPU time 792.54 seconds
Started Apr 18 12:47:41 PM PDT 24
Finished Apr 18 01:00:54 PM PDT 24
Peak memory 202308 kb
Host smart-33b746bb-fdab-467c-af7c-95f7320ec427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708330570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2708330570
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1283478754
Short name T455
Test name
Test status
Simulation time 488972267888 ps
CPU time 1056.71 seconds
Started Apr 18 12:47:13 PM PDT 24
Finished Apr 18 01:04:51 PM PDT 24
Peak memory 202120 kb
Host smart-51ca809c-5b77-4658-b0ab-c22a048bbc7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283478754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1283478754
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.74004860
Short name T12
Test name
Test status
Simulation time 329402348384 ps
CPU time 407.73 seconds
Started Apr 18 12:47:14 PM PDT 24
Finished Apr 18 12:54:03 PM PDT 24
Peak memory 202168 kb
Host smart-1b422121-5c88-42b7-9a90-ddc87bb4ceec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=74004860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixed
.74004860
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.810758219
Short name T704
Test name
Test status
Simulation time 587843758475 ps
CPU time 324.41 seconds
Started Apr 18 12:47:41 PM PDT 24
Finished Apr 18 12:53:06 PM PDT 24
Peak memory 202208 kb
Host smart-40539240-0f32-469a-ae1f-bbeb1d33f7a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810758219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.810758219
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2581287610
Short name T399
Test name
Test status
Simulation time 404878637150 ps
CPU time 248.48 seconds
Started Apr 18 12:47:16 PM PDT 24
Finished Apr 18 12:51:26 PM PDT 24
Peak memory 202224 kb
Host smart-975f1fa1-9aee-4627-b2a0-d209c510b6bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581287610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2581287610
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2170860438
Short name T528
Test name
Test status
Simulation time 101835590550 ps
CPU time 338.79 seconds
Started Apr 18 12:47:21 PM PDT 24
Finished Apr 18 12:53:01 PM PDT 24
Peak memory 202608 kb
Host smart-14aabc61-ff74-4211-ad57-df0718a32d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170860438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2170860438
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1191189307
Short name T756
Test name
Test status
Simulation time 22301646423 ps
CPU time 13.83 seconds
Started Apr 18 12:47:20 PM PDT 24
Finished Apr 18 12:47:35 PM PDT 24
Peak memory 201976 kb
Host smart-ccf7c2c1-dc16-42bc-9a94-cedcb3d7d470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191189307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1191189307
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3852481697
Short name T390
Test name
Test status
Simulation time 4518007097 ps
CPU time 3.33 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:47:23 PM PDT 24
Peak memory 202004 kb
Host smart-1f9cfced-8b08-4481-85ab-0548788e9962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852481697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3852481697
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.959280401
Short name T493
Test name
Test status
Simulation time 5580262845 ps
CPU time 7.81 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:47:24 PM PDT 24
Peak memory 202012 kb
Host smart-c35e79af-f5ea-44d3-a5c1-df9b5e7102f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959280401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.959280401
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3760568337
Short name T724
Test name
Test status
Simulation time 205745701637 ps
CPU time 202.95 seconds
Started Apr 18 12:47:25 PM PDT 24
Finished Apr 18 12:50:49 PM PDT 24
Peak memory 202140 kb
Host smart-f1152bd1-5eba-45b3-80f5-2905f1a386c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760568337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3760568337
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.4206803696
Short name T425
Test name
Test status
Simulation time 296548873 ps
CPU time 1.29 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:47:21 PM PDT 24
Peak memory 201580 kb
Host smart-dba806a8-2196-4cb0-8453-c75b01e5db6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206803696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4206803696
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3259857252
Short name T306
Test name
Test status
Simulation time 487074276334 ps
CPU time 582.25 seconds
Started Apr 18 12:47:21 PM PDT 24
Finished Apr 18 12:57:04 PM PDT 24
Peak memory 202304 kb
Host smart-cee3ef01-d990-42e2-8482-a4f213e1fb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259857252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3259857252
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2279083494
Short name T442
Test name
Test status
Simulation time 485714497385 ps
CPU time 99.05 seconds
Started Apr 18 12:47:20 PM PDT 24
Finished Apr 18 12:49:00 PM PDT 24
Peak memory 202068 kb
Host smart-4802ba49-a38b-4cb0-a85e-a0d8ea1ab8ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279083494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2279083494
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1015553072
Short name T478
Test name
Test status
Simulation time 326088133206 ps
CPU time 199.46 seconds
Started Apr 18 12:47:16 PM PDT 24
Finished Apr 18 12:50:37 PM PDT 24
Peak memory 202140 kb
Host smart-0e1c4529-7614-4816-9f2d-4c9c68964ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015553072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1015553072
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.519991295
Short name T492
Test name
Test status
Simulation time 160865372678 ps
CPU time 350.74 seconds
Started Apr 18 12:47:23 PM PDT 24
Finished Apr 18 12:53:14 PM PDT 24
Peak memory 202100 kb
Host smart-367eea13-13b8-474d-bffb-a799bfbc2804
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=519991295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.519991295
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.675073494
Short name T339
Test name
Test status
Simulation time 382013926648 ps
CPU time 934.4 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 01:02:54 PM PDT 24
Peak memory 202236 kb
Host smart-cad18cd5-c9ca-49fa-bfe6-f2d1613770ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675073494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.675073494
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.360041081
Short name T691
Test name
Test status
Simulation time 198818423641 ps
CPU time 440.22 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:54:40 PM PDT 24
Peak memory 202236 kb
Host smart-ce60c639-872d-4aaa-81ce-a3adb019a245
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360041081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.360041081
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3580903246
Short name T651
Test name
Test status
Simulation time 43766559936 ps
CPU time 98.86 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:48:57 PM PDT 24
Peak memory 202032 kb
Host smart-388ed09d-898c-4ec7-a932-f2d3044770e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580903246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3580903246
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.324139831
Short name T661
Test name
Test status
Simulation time 4970199895 ps
CPU time 11.66 seconds
Started Apr 18 12:47:16 PM PDT 24
Finished Apr 18 12:47:29 PM PDT 24
Peak memory 201992 kb
Host smart-d388ae72-bb32-4ce8-9f4b-b90a1059673b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324139831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.324139831
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2184404941
Short name T668
Test name
Test status
Simulation time 5805854600 ps
CPU time 4.19 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:47:23 PM PDT 24
Peak memory 201924 kb
Host smart-0ab629f2-8752-4d0b-9ee8-036eba2d34f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184404941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2184404941
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2993627518
Short name T268
Test name
Test status
Simulation time 328158962240 ps
CPU time 564.94 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:56:44 PM PDT 24
Peak memory 202248 kb
Host smart-ada72b71-29a0-4d3c-9359-d84256850575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993627518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2993627518
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.870158836
Short name T323
Test name
Test status
Simulation time 177666583393 ps
CPU time 70.84 seconds
Started Apr 18 12:47:16 PM PDT 24
Finished Apr 18 12:48:28 PM PDT 24
Peak memory 210572 kb
Host smart-ca9cff9d-baf5-4fff-9a61-80cb300d8cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870158836 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.870158836
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3521169775
Short name T658
Test name
Test status
Simulation time 382973026 ps
CPU time 1.38 seconds
Started Apr 18 12:47:30 PM PDT 24
Finished Apr 18 12:47:32 PM PDT 24
Peak memory 201928 kb
Host smart-604df818-9a1d-4f76-a434-cdccbd699e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521169775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3521169775
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1887400319
Short name T596
Test name
Test status
Simulation time 162735053532 ps
CPU time 56.7 seconds
Started Apr 18 12:47:37 PM PDT 24
Finished Apr 18 12:48:36 PM PDT 24
Peak memory 202344 kb
Host smart-1b53084f-794f-4b95-ad6b-4c189c356202
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887400319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1887400319
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3865877495
Short name T302
Test name
Test status
Simulation time 179211667387 ps
CPU time 72.29 seconds
Started Apr 18 12:47:26 PM PDT 24
Finished Apr 18 12:48:39 PM PDT 24
Peak memory 202224 kb
Host smart-87cf73ae-af08-4125-8a2d-a51637f748c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865877495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3865877495
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3228133919
Short name T190
Test name
Test status
Simulation time 166016846257 ps
CPU time 205.5 seconds
Started Apr 18 12:47:19 PM PDT 24
Finished Apr 18 12:50:46 PM PDT 24
Peak memory 202252 kb
Host smart-bedd5788-c23e-4dff-8b0c-0a39a0095eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228133919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3228133919
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1955061845
Short name T674
Test name
Test status
Simulation time 161596529456 ps
CPU time 183.97 seconds
Started Apr 18 12:47:20 PM PDT 24
Finished Apr 18 12:50:25 PM PDT 24
Peak memory 202128 kb
Host smart-7313216e-983c-4c34-b5e8-8c32ccf6a81d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955061845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1955061845
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2405051885
Short name T294
Test name
Test status
Simulation time 333607185869 ps
CPU time 737.65 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:59:38 PM PDT 24
Peak memory 202216 kb
Host smart-fc8c3f3d-9c8e-4917-9419-e32aebcebc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405051885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2405051885
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1495570990
Short name T476
Test name
Test status
Simulation time 163149938729 ps
CPU time 90.39 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:48:50 PM PDT 24
Peak memory 202252 kb
Host smart-31c731d3-09e9-4d88-88d9-f877cb5b773f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495570990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1495570990
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.302309970
Short name T685
Test name
Test status
Simulation time 190990606861 ps
CPU time 429.35 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:54:27 PM PDT 24
Peak memory 202228 kb
Host smart-8aea2f16-93c2-4440-95e2-3f184b021117
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302309970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.302309970
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3549946491
Short name T428
Test name
Test status
Simulation time 602519830433 ps
CPU time 736.2 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:59:36 PM PDT 24
Peak memory 201836 kb
Host smart-3ccbcb3d-0960-4bad-a63c-91b472e01960
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549946491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3549946491
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2758351915
Short name T706
Test name
Test status
Simulation time 115897503169 ps
CPU time 601.02 seconds
Started Apr 18 12:47:26 PM PDT 24
Finished Apr 18 12:57:28 PM PDT 24
Peak memory 202480 kb
Host smart-8ad9f763-1516-46a1-be62-69989e87d420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758351915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2758351915
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2498090821
Short name T573
Test name
Test status
Simulation time 35046514547 ps
CPU time 20.35 seconds
Started Apr 18 12:47:24 PM PDT 24
Finished Apr 18 12:47:45 PM PDT 24
Peak memory 202080 kb
Host smart-d37ef0f7-e9d3-45ed-8a3e-dd735a5e551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498090821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2498090821
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1334732914
Short name T555
Test name
Test status
Simulation time 4334912357 ps
CPU time 10.78 seconds
Started Apr 18 12:47:26 PM PDT 24
Finished Apr 18 12:47:37 PM PDT 24
Peak memory 201972 kb
Host smart-c44d96ab-3c1b-4568-a002-3656492ecf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334732914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1334732914
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1734969793
Short name T754
Test name
Test status
Simulation time 5864856295 ps
CPU time 7.72 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:47:28 PM PDT 24
Peak memory 202036 kb
Host smart-fdf2a445-e574-4135-8f57-d5ec553d4663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734969793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1734969793
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.474367036
Short name T621
Test name
Test status
Simulation time 317678716 ps
CPU time 1.34 seconds
Started Apr 18 12:47:23 PM PDT 24
Finished Apr 18 12:47:25 PM PDT 24
Peak memory 201888 kb
Host smart-108417a2-a46d-44b9-aadd-fe07756787f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474367036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.474367036
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.161161689
Short name T258
Test name
Test status
Simulation time 318248389711 ps
CPU time 730.48 seconds
Started Apr 18 12:47:38 PM PDT 24
Finished Apr 18 12:59:50 PM PDT 24
Peak memory 202236 kb
Host smart-d2cb5b6e-9b6c-4304-b5b7-8081456623c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161161689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.161161689
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1974617359
Short name T338
Test name
Test status
Simulation time 490661169103 ps
CPU time 286.48 seconds
Started Apr 18 12:47:28 PM PDT 24
Finished Apr 18 12:52:15 PM PDT 24
Peak memory 202224 kb
Host smart-5ad17613-7775-4455-a599-6c84aed59299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974617359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1974617359
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1321006365
Short name T395
Test name
Test status
Simulation time 334154338804 ps
CPU time 404.06 seconds
Started Apr 18 12:47:24 PM PDT 24
Finished Apr 18 12:54:09 PM PDT 24
Peak memory 202188 kb
Host smart-6bdec784-007b-4f62-acda-eb5e5b056449
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321006365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1321006365
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3407173613
Short name T303
Test name
Test status
Simulation time 324701318299 ps
CPU time 189.28 seconds
Started Apr 18 12:47:24 PM PDT 24
Finished Apr 18 12:50:34 PM PDT 24
Peak memory 202212 kb
Host smart-8184910e-02aa-47c4-87e4-df49b5796958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407173613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3407173613
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.4008389308
Short name T599
Test name
Test status
Simulation time 333692376587 ps
CPU time 60.56 seconds
Started Apr 18 12:47:27 PM PDT 24
Finished Apr 18 12:48:29 PM PDT 24
Peak memory 202088 kb
Host smart-ecf3298c-b939-49c7-aeb0-965f8070fa91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008389308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.4008389308
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2313049780
Short name T180
Test name
Test status
Simulation time 177659760917 ps
CPU time 219.32 seconds
Started Apr 18 12:47:40 PM PDT 24
Finished Apr 18 12:51:20 PM PDT 24
Peak memory 202248 kb
Host smart-725bce05-fd16-4706-a55c-584ad1016b10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313049780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2313049780
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2937140505
Short name T152
Test name
Test status
Simulation time 606391674698 ps
CPU time 201.57 seconds
Started Apr 18 12:47:26 PM PDT 24
Finished Apr 18 12:50:48 PM PDT 24
Peak memory 202080 kb
Host smart-642c550e-8623-4cfa-a43b-2705b2e7a656
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937140505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2937140505
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3211002965
Short name T234
Test name
Test status
Simulation time 87118602513 ps
CPU time 290.33 seconds
Started Apr 18 12:47:32 PM PDT 24
Finished Apr 18 12:52:24 PM PDT 24
Peak memory 202636 kb
Host smart-68889b03-a0d4-4c7d-b701-eba015b07575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211002965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3211002965
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2355950550
Short name T219
Test name
Test status
Simulation time 36522066674 ps
CPU time 67.85 seconds
Started Apr 18 12:47:34 PM PDT 24
Finished Apr 18 12:48:44 PM PDT 24
Peak memory 201968 kb
Host smart-0f732bc8-b32e-4cd9-9bb4-a3d1755e0d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355950550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2355950550
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.598663943
Short name T696
Test name
Test status
Simulation time 3971888134 ps
CPU time 9.05 seconds
Started Apr 18 12:47:40 PM PDT 24
Finished Apr 18 12:47:49 PM PDT 24
Peak memory 202020 kb
Host smart-049b68c7-85fd-49ec-89eb-7110592b325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598663943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.598663943
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1658491878
Short name T95
Test name
Test status
Simulation time 6058794697 ps
CPU time 7.94 seconds
Started Apr 18 12:47:34 PM PDT 24
Finished Apr 18 12:47:44 PM PDT 24
Peak memory 202012 kb
Host smart-36dc8ca6-43bc-45d5-a979-0813e9b21d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658491878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1658491878
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.154302575
Short name T681
Test name
Test status
Simulation time 332702909641 ps
CPU time 205.5 seconds
Started Apr 18 12:47:23 PM PDT 24
Finished Apr 18 12:50:49 PM PDT 24
Peak memory 202192 kb
Host smart-d9c396b3-ccb1-4926-b836-79ccf202347d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154302575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
154302575
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3640887446
Short name T678
Test name
Test status
Simulation time 28395802882 ps
CPU time 62.8 seconds
Started Apr 18 12:47:40 PM PDT 24
Finished Apr 18 12:48:43 PM PDT 24
Peak memory 210624 kb
Host smart-5c8ef1cb-26e6-47ae-a2eb-c70cdf2118ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640887446 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3640887446
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1355293550
Short name T432
Test name
Test status
Simulation time 325399043 ps
CPU time 0.84 seconds
Started Apr 18 12:47:37 PM PDT 24
Finished Apr 18 12:47:40 PM PDT 24
Peak memory 201880 kb
Host smart-22cf9e1b-7a82-46fa-baae-7ebd6d9ade3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355293550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1355293550
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.169171432
Short name T514
Test name
Test status
Simulation time 363187666695 ps
CPU time 200.86 seconds
Started Apr 18 12:47:39 PM PDT 24
Finished Apr 18 12:51:01 PM PDT 24
Peak memory 202272 kb
Host smart-6429530b-1230-4630-97e1-5c47cea0ff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169171432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.169171432
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3122901754
Short name T550
Test name
Test status
Simulation time 326687092861 ps
CPU time 780.86 seconds
Started Apr 18 12:47:42 PM PDT 24
Finished Apr 18 01:00:44 PM PDT 24
Peak memory 202252 kb
Host smart-d4e9fc38-fe9c-4f61-8c60-380ae51a8b06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122901754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3122901754
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.965964077
Short name T714
Test name
Test status
Simulation time 160139234965 ps
CPU time 360.23 seconds
Started Apr 18 12:47:27 PM PDT 24
Finished Apr 18 12:53:28 PM PDT 24
Peak memory 202296 kb
Host smart-007855eb-568d-4e17-9dd4-bc2268cdca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965964077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.965964077
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.820564773
Short name T632
Test name
Test status
Simulation time 163518785236 ps
CPU time 181.58 seconds
Started Apr 18 12:47:23 PM PDT 24
Finished Apr 18 12:50:25 PM PDT 24
Peak memory 202140 kb
Host smart-2737f204-b9d6-48f5-9bc9-c6198c2192de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=820564773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.820564773
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2353133980
Short name T300
Test name
Test status
Simulation time 418780679521 ps
CPU time 1016.44 seconds
Started Apr 18 12:47:25 PM PDT 24
Finished Apr 18 01:04:22 PM PDT 24
Peak memory 202236 kb
Host smart-53b8ceeb-6319-4e7b-91bd-f6fb1d87e549
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353133980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2353133980
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3587036824
Short name T776
Test name
Test status
Simulation time 408965814318 ps
CPU time 942.42 seconds
Started Apr 18 12:47:23 PM PDT 24
Finished Apr 18 01:03:07 PM PDT 24
Peak memory 202512 kb
Host smart-5da1c91b-55fe-4cb3-9aca-76a490ab2833
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587036824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3587036824
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3053380298
Short name T784
Test name
Test status
Simulation time 85256092267 ps
CPU time 493.46 seconds
Started Apr 18 12:47:29 PM PDT 24
Finished Apr 18 12:55:44 PM PDT 24
Peak memory 202604 kb
Host smart-dd0b4bc4-d53b-41d4-b1e2-95c78091d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053380298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3053380298
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2317058854
Short name T683
Test name
Test status
Simulation time 24144671436 ps
CPU time 3.99 seconds
Started Apr 18 12:47:25 PM PDT 24
Finished Apr 18 12:47:29 PM PDT 24
Peak memory 202000 kb
Host smart-449afa26-def8-4871-941b-aecdd0bff8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317058854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2317058854
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.4100718978
Short name T397
Test name
Test status
Simulation time 3395117603 ps
CPU time 9.02 seconds
Started Apr 18 12:47:24 PM PDT 24
Finished Apr 18 12:47:34 PM PDT 24
Peak memory 202024 kb
Host smart-4dc6919a-5007-4757-a769-332d8fdf3722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100718978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.4100718978
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2869903359
Short name T699
Test name
Test status
Simulation time 5599248708 ps
CPU time 4.09 seconds
Started Apr 18 12:47:22 PM PDT 24
Finished Apr 18 12:47:27 PM PDT 24
Peak memory 202068 kb
Host smart-3ee8542e-a84c-4db5-872e-18aa2f77b09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869903359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2869903359
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2101680303
Short name T298
Test name
Test status
Simulation time 563598499942 ps
CPU time 523.93 seconds
Started Apr 18 12:47:34 PM PDT 24
Finished Apr 18 12:56:19 PM PDT 24
Peak memory 202660 kb
Host smart-a20c5836-1241-4be0-a33d-15226d6556cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101680303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2101680303
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2600782749
Short name T40
Test name
Test status
Simulation time 22883283471 ps
CPU time 70.61 seconds
Started Apr 18 12:47:22 PM PDT 24
Finished Apr 18 12:48:33 PM PDT 24
Peak memory 210840 kb
Host smart-145d23a9-cff5-4675-be1b-357fa69663fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600782749 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2600782749
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1369848629
Short name T652
Test name
Test status
Simulation time 422184984 ps
CPU time 0.85 seconds
Started Apr 18 12:47:33 PM PDT 24
Finished Apr 18 12:47:36 PM PDT 24
Peak memory 201952 kb
Host smart-a7ef3595-6adb-45de-a345-29babec35c2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369848629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1369848629
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3468387477
Short name T156
Test name
Test status
Simulation time 173283702950 ps
CPU time 82.46 seconds
Started Apr 18 12:47:33 PM PDT 24
Finished Apr 18 12:48:56 PM PDT 24
Peak memory 202312 kb
Host smart-e162b58b-c493-4212-883f-d6b2e012d0b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468387477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3468387477
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.87230679
Short name T766
Test name
Test status
Simulation time 334869612550 ps
CPU time 746.12 seconds
Started Apr 18 12:47:40 PM PDT 24
Finished Apr 18 01:00:07 PM PDT 24
Peak memory 202328 kb
Host smart-62ade720-8a99-4b40-902c-710108a04996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87230679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.87230679
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2555016522
Short name T394
Test name
Test status
Simulation time 169732708855 ps
CPU time 391.32 seconds
Started Apr 18 12:47:32 PM PDT 24
Finished Apr 18 12:54:04 PM PDT 24
Peak memory 202232 kb
Host smart-6f44a93c-16fe-49b9-85ae-73d0c7805e7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555016522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2555016522
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2806478902
Short name T792
Test name
Test status
Simulation time 162669583246 ps
CPU time 102.38 seconds
Started Apr 18 12:47:29 PM PDT 24
Finished Apr 18 12:49:12 PM PDT 24
Peak memory 202152 kb
Host smart-6b01fa54-b07b-47dc-b457-00a768179f76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806478902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2806478902
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1623296105
Short name T100
Test name
Test status
Simulation time 171854975928 ps
CPU time 419.38 seconds
Started Apr 18 12:47:33 PM PDT 24
Finished Apr 18 12:54:33 PM PDT 24
Peak memory 202144 kb
Host smart-702c4c00-89b0-45d5-a11f-0081f802b55f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623296105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1623296105
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.730890623
Short name T433
Test name
Test status
Simulation time 404618187255 ps
CPU time 245.54 seconds
Started Apr 18 12:47:33 PM PDT 24
Finished Apr 18 12:51:40 PM PDT 24
Peak memory 202080 kb
Host smart-3f9e1d7f-efb1-4f1f-b7a7-e713bbaa8519
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730890623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.730890623
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.893529941
Short name T225
Test name
Test status
Simulation time 94490615211 ps
CPU time 517.94 seconds
Started Apr 18 12:47:28 PM PDT 24
Finished Apr 18 12:56:06 PM PDT 24
Peak memory 202532 kb
Host smart-33e8a547-9832-4d1b-b928-4b13cb91dd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893529941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.893529941
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.566511362
Short name T444
Test name
Test status
Simulation time 27692342789 ps
CPU time 15.23 seconds
Started Apr 18 12:48:20 PM PDT 24
Finished Apr 18 12:48:35 PM PDT 24
Peak memory 202060 kb
Host smart-e52682a1-e42f-44a1-b16f-b92eaed0dbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566511362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.566511362
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.154834086
Short name T452
Test name
Test status
Simulation time 5492535898 ps
CPU time 8.04 seconds
Started Apr 18 12:47:29 PM PDT 24
Finished Apr 18 12:47:38 PM PDT 24
Peak memory 202000 kb
Host smart-38027856-f464-45b3-9a38-91e5a52cca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154834086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.154834086
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2110248293
Short name T672
Test name
Test status
Simulation time 5545184492 ps
CPU time 12.99 seconds
Started Apr 18 12:47:34 PM PDT 24
Finished Apr 18 12:47:49 PM PDT 24
Peak memory 201960 kb
Host smart-cfb8c629-df50-4d8a-84bd-7ede8edd649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110248293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2110248293
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2597476600
Short name T489
Test name
Test status
Simulation time 11996835676 ps
CPU time 18.36 seconds
Started Apr 18 12:47:30 PM PDT 24
Finished Apr 18 12:47:50 PM PDT 24
Peak memory 202348 kb
Host smart-ea3291b2-1b44-4b7a-a5cf-8c34f2184d25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597476600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2597476600
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2119652704
Short name T721
Test name
Test status
Simulation time 516121787 ps
CPU time 0.65 seconds
Started Apr 18 12:47:32 PM PDT 24
Finished Apr 18 12:47:34 PM PDT 24
Peak memory 201852 kb
Host smart-fc3c844b-412b-474a-842c-9e00c7563b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119652704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2119652704
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.958738290
Short name T332
Test name
Test status
Simulation time 358115463431 ps
CPU time 50.98 seconds
Started Apr 18 12:47:27 PM PDT 24
Finished Apr 18 12:48:19 PM PDT 24
Peak memory 202256 kb
Host smart-28d8fa72-6291-40db-ba50-b5e327b1230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958738290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.958738290
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1674236829
Short name T765
Test name
Test status
Simulation time 168259295684 ps
CPU time 65.38 seconds
Started Apr 18 12:47:33 PM PDT 24
Finished Apr 18 12:48:41 PM PDT 24
Peak memory 202232 kb
Host smart-b9ab25d2-0f8f-4460-aff7-3f976a6c9ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674236829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1674236829
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1033401481
Short name T630
Test name
Test status
Simulation time 161657109585 ps
CPU time 25.37 seconds
Started Apr 18 12:47:33 PM PDT 24
Finished Apr 18 12:48:00 PM PDT 24
Peak memory 202184 kb
Host smart-d53f9055-e45d-4b79-a5f9-7a43d463f282
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033401481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1033401481
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3523246178
Short name T362
Test name
Test status
Simulation time 164986769792 ps
CPU time 42.62 seconds
Started Apr 18 12:47:30 PM PDT 24
Finished Apr 18 12:48:13 PM PDT 24
Peak memory 202272 kb
Host smart-9403fe11-be78-48f0-b7a9-8b79d6834736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523246178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3523246178
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2562108464
Short name T641
Test name
Test status
Simulation time 505939632932 ps
CPU time 308.32 seconds
Started Apr 18 12:47:33 PM PDT 24
Finished Apr 18 12:52:43 PM PDT 24
Peak memory 202296 kb
Host smart-d9a43c26-d786-4bad-a704-6c0d92e01559
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562108464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2562108464
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1129231034
Short name T366
Test name
Test status
Simulation time 186604773813 ps
CPU time 410.56 seconds
Started Apr 18 12:47:30 PM PDT 24
Finished Apr 18 12:54:22 PM PDT 24
Peak memory 202236 kb
Host smart-59205015-0b24-452b-ab54-d609d97888f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129231034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1129231034
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3696439133
Short name T560
Test name
Test status
Simulation time 395977308601 ps
CPU time 237.1 seconds
Started Apr 18 12:47:36 PM PDT 24
Finished Apr 18 12:51:35 PM PDT 24
Peak memory 202236 kb
Host smart-4cef734e-3aee-408f-bec0-e3a37a898bda
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696439133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3696439133
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3960553593
Short name T536
Test name
Test status
Simulation time 122079126013 ps
CPU time 445.73 seconds
Started Apr 18 12:47:28 PM PDT 24
Finished Apr 18 12:54:55 PM PDT 24
Peak memory 202628 kb
Host smart-eb0a1fea-5760-4914-9cb8-73c01e87bb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960553593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3960553593
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1039779405
Short name T702
Test name
Test status
Simulation time 28501202168 ps
CPU time 32.28 seconds
Started Apr 18 12:47:40 PM PDT 24
Finished Apr 18 12:48:13 PM PDT 24
Peak memory 201960 kb
Host smart-f7b2bf86-2757-4ef9-846a-2d7d651e6eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039779405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1039779405
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.268437646
Short name T3
Test name
Test status
Simulation time 4209867353 ps
CPU time 6.06 seconds
Started Apr 18 12:47:29 PM PDT 24
Finished Apr 18 12:47:36 PM PDT 24
Peak memory 202064 kb
Host smart-a1caa878-2c0b-48d9-9706-4382779f65c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268437646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.268437646
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.619304847
Short name T779
Test name
Test status
Simulation time 6086031402 ps
CPU time 4.5 seconds
Started Apr 18 12:47:34 PM PDT 24
Finished Apr 18 12:47:41 PM PDT 24
Peak memory 201956 kb
Host smart-9585a853-99ca-47c1-b0b8-8143bd6197e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619304847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.619304847
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3036293110
Short name T259
Test name
Test status
Simulation time 335745997196 ps
CPU time 784.5 seconds
Started Apr 18 12:47:37 PM PDT 24
Finished Apr 18 01:00:43 PM PDT 24
Peak memory 202348 kb
Host smart-66efc0bc-6367-4973-b26b-e2745a6a73e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036293110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3036293110
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3292238060
Short name T17
Test name
Test status
Simulation time 20392581014 ps
CPU time 44.77 seconds
Started Apr 18 12:47:34 PM PDT 24
Finished Apr 18 12:48:20 PM PDT 24
Peak memory 210452 kb
Host smart-d8d880d9-e68f-4c2f-a4e0-fa1019a2527a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292238060 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3292238060
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.128560551
Short name T468
Test name
Test status
Simulation time 520583574 ps
CPU time 0.88 seconds
Started Apr 18 12:47:37 PM PDT 24
Finished Apr 18 12:47:39 PM PDT 24
Peak memory 201932 kb
Host smart-c39df2c0-d614-4f12-a1d7-77ce0a878d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128560551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.128560551
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2991612124
Short name T563
Test name
Test status
Simulation time 487392600243 ps
CPU time 1173.14 seconds
Started Apr 18 12:47:35 PM PDT 24
Finished Apr 18 01:07:10 PM PDT 24
Peak memory 202276 kb
Host smart-e02a4a88-fb59-452a-9aa4-a093daea5e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991612124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2991612124
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3360294741
Short name T429
Test name
Test status
Simulation time 487998284799 ps
CPU time 74.34 seconds
Started Apr 18 12:47:30 PM PDT 24
Finished Apr 18 12:48:46 PM PDT 24
Peak memory 202120 kb
Host smart-06c571e3-0110-4c53-a90d-70850dd87c68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360294741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3360294741
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2332956094
Short name T322
Test name
Test status
Simulation time 492390069161 ps
CPU time 296.18 seconds
Started Apr 18 12:47:37 PM PDT 24
Finished Apr 18 12:52:34 PM PDT 24
Peak memory 202120 kb
Host smart-a1ab9521-885d-4bf8-ab8a-f9bca358c6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332956094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2332956094
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3614330745
Short name T589
Test name
Test status
Simulation time 331377786021 ps
CPU time 385.14 seconds
Started Apr 18 12:47:29 PM PDT 24
Finished Apr 18 12:53:55 PM PDT 24
Peak memory 202232 kb
Host smart-8ebc266e-275e-4d25-9a6c-cf959a8f14c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614330745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3614330745
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.789323640
Short name T646
Test name
Test status
Simulation time 390029234539 ps
CPU time 237.93 seconds
Started Apr 18 12:47:33 PM PDT 24
Finished Apr 18 12:51:32 PM PDT 24
Peak memory 202232 kb
Host smart-cfeaf82b-b4c8-490a-933d-f4fb127e151b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789323640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.789323640
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.245991611
Short name T191
Test name
Test status
Simulation time 408372319004 ps
CPU time 241.66 seconds
Started Apr 18 12:47:34 PM PDT 24
Finished Apr 18 12:51:37 PM PDT 24
Peak memory 202288 kb
Host smart-4bf4c9ab-e7ed-4b80-92de-e39d4ad436a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245991611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.245991611
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1381406491
Short name T408
Test name
Test status
Simulation time 40108921484 ps
CPU time 48.43 seconds
Started Apr 18 12:47:39 PM PDT 24
Finished Apr 18 12:48:29 PM PDT 24
Peak memory 202032 kb
Host smart-a27a22ea-ae6f-43d6-9389-ed81aa3cbaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381406491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1381406491
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3362318179
Short name T736
Test name
Test status
Simulation time 5324174394 ps
CPU time 3.63 seconds
Started Apr 18 12:47:41 PM PDT 24
Finished Apr 18 12:47:45 PM PDT 24
Peak memory 201956 kb
Host smart-ecca61c6-fc34-4690-9a7c-669a8abb0792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362318179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3362318179
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3015774919
Short name T494
Test name
Test status
Simulation time 5993460407 ps
CPU time 9.39 seconds
Started Apr 18 12:47:41 PM PDT 24
Finished Apr 18 12:47:52 PM PDT 24
Peak memory 202068 kb
Host smart-1d1c3e81-f948-46ea-84a0-0912acf1d773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015774919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3015774919
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3790717670
Short name T231
Test name
Test status
Simulation time 122349739457 ps
CPU time 603.87 seconds
Started Apr 18 12:47:36 PM PDT 24
Finished Apr 18 12:57:42 PM PDT 24
Peak memory 202500 kb
Host smart-feff4ee4-4e15-479b-b01b-288f802bec98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790717670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3790717670
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1152080326
Short name T98
Test name
Test status
Simulation time 168691112312 ps
CPU time 308.97 seconds
Started Apr 18 12:47:37 PM PDT 24
Finished Apr 18 12:52:47 PM PDT 24
Peak memory 210888 kb
Host smart-5aeea69d-b270-4721-86c0-9a82bfc76086
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152080326 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1152080326
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2442865143
Short name T486
Test name
Test status
Simulation time 549944702 ps
CPU time 0.93 seconds
Started Apr 18 12:47:34 PM PDT 24
Finished Apr 18 12:47:37 PM PDT 24
Peak memory 202172 kb
Host smart-47e7b627-8e8d-4cb9-8ab4-3889ca84320c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442865143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2442865143
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.852650636
Short name T347
Test name
Test status
Simulation time 163830553436 ps
CPU time 355.98 seconds
Started Apr 18 12:47:34 PM PDT 24
Finished Apr 18 12:53:32 PM PDT 24
Peak memory 202252 kb
Host smart-7b1369d5-5e32-460e-9c2d-f61961cf6f89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852650636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.852650636
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.834377610
Short name T635
Test name
Test status
Simulation time 168531426599 ps
CPU time 119.16 seconds
Started Apr 18 12:47:37 PM PDT 24
Finished Apr 18 12:49:38 PM PDT 24
Peak memory 202248 kb
Host smart-93630598-e29e-4d90-908a-05792c6c5e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834377610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.834377610
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1978982664
Short name T479
Test name
Test status
Simulation time 166856423165 ps
CPU time 194.76 seconds
Started Apr 18 12:47:48 PM PDT 24
Finished Apr 18 12:51:03 PM PDT 24
Peak memory 202144 kb
Host smart-fad990c7-b40d-481d-a2b1-4db2929578d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978982664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1978982664
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1004617120
Short name T30
Test name
Test status
Simulation time 329806582273 ps
CPU time 769.06 seconds
Started Apr 18 12:47:35 PM PDT 24
Finished Apr 18 01:00:26 PM PDT 24
Peak memory 202292 kb
Host smart-04e57a2c-67de-4758-a1e0-ca254c5f69b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004617120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1004617120
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3587184950
Short name T460
Test name
Test status
Simulation time 329092752257 ps
CPU time 789.87 seconds
Started Apr 18 12:47:36 PM PDT 24
Finished Apr 18 01:00:47 PM PDT 24
Peak memory 202208 kb
Host smart-ca19f231-5560-43d9-a129-3b0bff06f797
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587184950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3587184950
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.524887201
Short name T770
Test name
Test status
Simulation time 572168653784 ps
CPU time 1162.87 seconds
Started Apr 18 12:47:38 PM PDT 24
Finished Apr 18 01:07:02 PM PDT 24
Peak memory 202244 kb
Host smart-6efe5bba-84b6-4857-8f8d-bb8ba8d58ab1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524887201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.524887201
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3705682262
Short name T791
Test name
Test status
Simulation time 425177802353 ps
CPU time 65.18 seconds
Started Apr 18 12:47:44 PM PDT 24
Finished Apr 18 12:48:50 PM PDT 24
Peak memory 202296 kb
Host smart-4b7a7c2a-3995-4a1b-a96a-1871f7ed492a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705682262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3705682262
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2903952607
Short name T223
Test name
Test status
Simulation time 133110432462 ps
CPU time 533.81 seconds
Started Apr 18 12:47:35 PM PDT 24
Finished Apr 18 12:56:31 PM PDT 24
Peak memory 202488 kb
Host smart-666dd017-06e2-4e9d-b1b8-6b33d29d2c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903952607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2903952607
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1861797995
Short name T544
Test name
Test status
Simulation time 45477752551 ps
CPU time 88 seconds
Started Apr 18 12:47:39 PM PDT 24
Finished Apr 18 12:49:07 PM PDT 24
Peak memory 202068 kb
Host smart-57e0b5c3-466b-4aaa-ae8a-25f49a657e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861797995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1861797995
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3239666101
Short name T718
Test name
Test status
Simulation time 4766353642 ps
CPU time 11.97 seconds
Started Apr 18 12:47:45 PM PDT 24
Finished Apr 18 12:47:57 PM PDT 24
Peak memory 202064 kb
Host smart-2df9c34d-5921-473e-a0c1-c3cfdcdc6bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239666101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3239666101
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1174872305
Short name T572
Test name
Test status
Simulation time 6084662077 ps
CPU time 7.83 seconds
Started Apr 18 12:47:42 PM PDT 24
Finished Apr 18 12:47:50 PM PDT 24
Peak memory 202044 kb
Host smart-641bfa33-19f1-4120-9f0b-8305880d030d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174872305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1174872305
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2945153573
Short name T545
Test name
Test status
Simulation time 195393944297 ps
CPU time 113.82 seconds
Started Apr 18 12:47:37 PM PDT 24
Finished Apr 18 12:49:33 PM PDT 24
Peak memory 202224 kb
Host smart-6ecc1dac-453b-4464-bd9e-6fe43082b455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945153573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2945153573
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3573690128
Short name T449
Test name
Test status
Simulation time 54885242941 ps
CPU time 206.79 seconds
Started Apr 18 12:47:36 PM PDT 24
Finished Apr 18 12:51:05 PM PDT 24
Peak memory 210880 kb
Host smart-9f9bd43f-95eb-4eee-ba4b-f0cd3163cb30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573690128 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3573690128
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2211498667
Short name T617
Test name
Test status
Simulation time 379086489 ps
CPU time 1.5 seconds
Started Apr 18 12:47:42 PM PDT 24
Finished Apr 18 12:47:44 PM PDT 24
Peak memory 201884 kb
Host smart-678d00f8-7611-496a-8cf3-b1681a3609fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211498667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2211498667
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1220925662
Short name T208
Test name
Test status
Simulation time 169777907512 ps
CPU time 412.31 seconds
Started Apr 18 12:47:47 PM PDT 24
Finished Apr 18 12:54:40 PM PDT 24
Peak memory 202152 kb
Host smart-e1ebb674-6bb8-4e88-8149-3e0ff5f3e650
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220925662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1220925662
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.965479912
Short name T289
Test name
Test status
Simulation time 327005005948 ps
CPU time 775.65 seconds
Started Apr 18 12:47:46 PM PDT 24
Finished Apr 18 01:00:43 PM PDT 24
Peak memory 202152 kb
Host smart-a77a3202-716e-48bf-8164-5bb0a0a331d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965479912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.965479912
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1426114117
Short name T510
Test name
Test status
Simulation time 492040845634 ps
CPU time 1219.44 seconds
Started Apr 18 12:47:42 PM PDT 24
Finished Apr 18 01:08:02 PM PDT 24
Peak memory 202276 kb
Host smart-6a358581-89ce-422b-b43e-81299c54c9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426114117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1426114117
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.101743030
Short name T570
Test name
Test status
Simulation time 486878433578 ps
CPU time 580.25 seconds
Started Apr 18 12:47:47 PM PDT 24
Finished Apr 18 12:57:28 PM PDT 24
Peak memory 202136 kb
Host smart-3cbb02e3-48cf-4d6e-b1b1-a5a709d3a727
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=101743030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.101743030
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2734542803
Short name T178
Test name
Test status
Simulation time 495563214810 ps
CPU time 1176.02 seconds
Started Apr 18 12:47:42 PM PDT 24
Finished Apr 18 01:07:19 PM PDT 24
Peak memory 202264 kb
Host smart-b057c9bd-da1d-4808-90ba-2294f7897d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734542803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2734542803
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.540806216
Short name T684
Test name
Test status
Simulation time 486542226780 ps
CPU time 1084.92 seconds
Started Apr 18 12:47:48 PM PDT 24
Finished Apr 18 01:05:54 PM PDT 24
Peak memory 202220 kb
Host smart-a770cd69-e6b7-4135-9c1b-b256438e38de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=540806216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.540806216
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.687567699
Short name T753
Test name
Test status
Simulation time 177154934167 ps
CPU time 212.54 seconds
Started Apr 18 12:47:48 PM PDT 24
Finished Apr 18 12:51:21 PM PDT 24
Peak memory 202212 kb
Host smart-2d6fc849-0ffa-4184-bd9e-f80bbd4bee9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687567699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.687567699
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.78376939
Short name T580
Test name
Test status
Simulation time 600553290453 ps
CPU time 1431.95 seconds
Started Apr 18 12:47:46 PM PDT 24
Finished Apr 18 01:11:39 PM PDT 24
Peak memory 202312 kb
Host smart-c6d53cd3-9427-4b3f-9cfc-599b6285cb32
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78376939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.a
dc_ctrl_filters_wakeup_fixed.78376939
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.104546603
Short name T737
Test name
Test status
Simulation time 93206336019 ps
CPU time 524.63 seconds
Started Apr 18 12:47:51 PM PDT 24
Finished Apr 18 12:56:36 PM PDT 24
Peak memory 202456 kb
Host smart-9c7161f9-14ea-4b53-9355-d05d630d69ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104546603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.104546603
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.855563750
Short name T561
Test name
Test status
Simulation time 25851741497 ps
CPU time 59.13 seconds
Started Apr 18 12:47:48 PM PDT 24
Finished Apr 18 12:48:48 PM PDT 24
Peak memory 202060 kb
Host smart-91d2be14-c32a-4c97-b52c-5219c03358d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855563750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.855563750
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.702720113
Short name T413
Test name
Test status
Simulation time 5503794725 ps
CPU time 3.94 seconds
Started Apr 18 12:47:42 PM PDT 24
Finished Apr 18 12:47:47 PM PDT 24
Peak memory 201932 kb
Host smart-6118a7f0-0ef2-40a7-a274-2704c353c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702720113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.702720113
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1518080854
Short name T757
Test name
Test status
Simulation time 5831766469 ps
CPU time 14.62 seconds
Started Apr 18 12:47:42 PM PDT 24
Finished Apr 18 12:47:57 PM PDT 24
Peak memory 201944 kb
Host smart-d8ac005d-be03-45b9-95c5-9cad00b34f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518080854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1518080854
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3333038879
Short name T227
Test name
Test status
Simulation time 128389484480 ps
CPU time 491.88 seconds
Started Apr 18 12:47:47 PM PDT 24
Finished Apr 18 12:56:00 PM PDT 24
Peak memory 210752 kb
Host smart-e6cdb60f-32f7-4aa0-99d3-5b9a858391eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333038879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3333038879
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3630656990
Short name T104
Test name
Test status
Simulation time 448549569 ps
CPU time 1.56 seconds
Started Apr 18 12:47:04 PM PDT 24
Finished Apr 18 12:47:07 PM PDT 24
Peak memory 201968 kb
Host smart-4f1bb607-9e59-43c3-b388-e1b3941a0b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630656990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3630656990
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2797667835
Short name T324
Test name
Test status
Simulation time 490155879209 ps
CPU time 990.31 seconds
Started Apr 18 12:47:00 PM PDT 24
Finished Apr 18 01:03:31 PM PDT 24
Peak memory 202276 kb
Host smart-a1a290e4-3645-4bdd-856e-be7069afd7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797667835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2797667835
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3969013221
Short name T423
Test name
Test status
Simulation time 488702357338 ps
CPU time 1099.42 seconds
Started Apr 18 12:47:00 PM PDT 24
Finished Apr 18 01:05:21 PM PDT 24
Peak memory 202088 kb
Host smart-abd15630-fe87-4f06-8ffb-90a55ba9513b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969013221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3969013221
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.641196343
Short name T351
Test name
Test status
Simulation time 483818363551 ps
CPU time 423.31 seconds
Started Apr 18 12:47:01 PM PDT 24
Finished Apr 18 12:54:06 PM PDT 24
Peak memory 202328 kb
Host smart-7cc279c0-df6d-46fa-9502-1fc1afc08d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641196343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.641196343
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2274752585
Short name T728
Test name
Test status
Simulation time 163310321708 ps
CPU time 93.92 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:48:38 PM PDT 24
Peak memory 202228 kb
Host smart-34b907d5-cdfd-4cd3-8be3-9dde731c08c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274752585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2274752585
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3794307346
Short name T199
Test name
Test status
Simulation time 558355621429 ps
CPU time 369.68 seconds
Started Apr 18 12:47:00 PM PDT 24
Finished Apr 18 12:53:11 PM PDT 24
Peak memory 202240 kb
Host smart-b61abd74-505c-47c3-8641-f63f1264f24b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794307346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3794307346
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3498532578
Short name T662
Test name
Test status
Simulation time 420207448038 ps
CPU time 776.99 seconds
Started Apr 18 12:47:04 PM PDT 24
Finished Apr 18 01:00:02 PM PDT 24
Peak memory 202200 kb
Host smart-cea945c6-4ce5-4e86-b989-dac1471fda15
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498532578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3498532578
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.4090891395
Short name T92
Test name
Test status
Simulation time 100379388109 ps
CPU time 445.31 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 12:54:29 PM PDT 24
Peak memory 202600 kb
Host smart-c445c0e4-0fed-435b-b957-94b04eec08a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090891395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.4090891395
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2383391814
Short name T400
Test name
Test status
Simulation time 34418716446 ps
CPU time 84.36 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 12:48:28 PM PDT 24
Peak memory 201948 kb
Host smart-df02ad51-3ce2-4f0a-b711-eaa4579bcdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383391814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2383391814
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3940781582
Short name T554
Test name
Test status
Simulation time 4964170884 ps
CPU time 3.97 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 12:47:07 PM PDT 24
Peak memory 201944 kb
Host smart-a70eb847-7c9a-4d94-8b43-88ae0371f321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940781582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3940781582
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.828780999
Short name T64
Test name
Test status
Simulation time 7861905650 ps
CPU time 10.2 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 12:47:14 PM PDT 24
Peak memory 218792 kb
Host smart-2026a4b4-9498-48dc-801a-837db68f9292
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828780999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.828780999
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3954976527
Short name T511
Test name
Test status
Simulation time 5732638788 ps
CPU time 12.68 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:47:17 PM PDT 24
Peak memory 202068 kb
Host smart-bdcf15cb-77f9-4284-9422-c328fcc3acfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954976527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3954976527
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3133764116
Short name T38
Test name
Test status
Simulation time 353406436248 ps
CPU time 339.49 seconds
Started Apr 18 12:47:04 PM PDT 24
Finished Apr 18 12:52:45 PM PDT 24
Peak memory 202320 kb
Host smart-4f259571-026a-4542-8ca2-a7f44ea0be2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133764116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3133764116
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.4168981354
Short name T19
Test name
Test status
Simulation time 180485031786 ps
CPU time 190.59 seconds
Started Apr 18 12:47:04 PM PDT 24
Finished Apr 18 12:50:15 PM PDT 24
Peak memory 210848 kb
Host smart-110e006c-9f46-4675-b441-3a9cac7aa3be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168981354 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.4168981354
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.254893788
Short name T215
Test name
Test status
Simulation time 517813372299 ps
CPU time 1142.36 seconds
Started Apr 18 12:47:50 PM PDT 24
Finished Apr 18 01:06:53 PM PDT 24
Peak memory 202296 kb
Host smart-6bc6751a-1874-43ad-97f2-cacaab4319cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254893788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.254893788
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4079138804
Short name T45
Test name
Test status
Simulation time 173739397933 ps
CPU time 385.7 seconds
Started Apr 18 12:47:49 PM PDT 24
Finished Apr 18 12:54:15 PM PDT 24
Peak memory 202152 kb
Host smart-43aee40f-fe53-4d5c-80d5-adcfebb30b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079138804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4079138804
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.4103917231
Short name T740
Test name
Test status
Simulation time 161120510516 ps
CPU time 188.25 seconds
Started Apr 18 12:47:46 PM PDT 24
Finished Apr 18 12:50:55 PM PDT 24
Peak memory 202336 kb
Host smart-27a49ca5-c8a0-4ff5-8a0d-bc925334ae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103917231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4103917231
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1401118099
Short name T643
Test name
Test status
Simulation time 161588269522 ps
CPU time 347.87 seconds
Started Apr 18 12:47:52 PM PDT 24
Finished Apr 18 12:53:40 PM PDT 24
Peak memory 202100 kb
Host smart-6c73ab6c-9da9-47de-9f92-57c2c1d67154
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401118099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1401118099
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2307603120
Short name T320
Test name
Test status
Simulation time 486655760214 ps
CPU time 1070.35 seconds
Started Apr 18 12:47:48 PM PDT 24
Finished Apr 18 01:05:39 PM PDT 24
Peak memory 202356 kb
Host smart-a1e0144e-9b7a-4fbc-8840-2f24672275b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307603120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2307603120
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3349872606
Short name T473
Test name
Test status
Simulation time 325617606416 ps
CPU time 746.95 seconds
Started Apr 18 12:47:46 PM PDT 24
Finished Apr 18 01:00:14 PM PDT 24
Peak memory 202192 kb
Host smart-005f97cd-9268-43da-9f5c-33da0f063fba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349872606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3349872606
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1274970816
Short name T588
Test name
Test status
Simulation time 200244247391 ps
CPU time 214.19 seconds
Started Apr 18 12:47:50 PM PDT 24
Finished Apr 18 12:51:25 PM PDT 24
Peak memory 202228 kb
Host smart-6eac711d-5509-4c8b-9b41-2863f5485909
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274970816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1274970816
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1535773350
Short name T232
Test name
Test status
Simulation time 120319480790 ps
CPU time 678.37 seconds
Started Apr 18 12:48:05 PM PDT 24
Finished Apr 18 12:59:24 PM PDT 24
Peak memory 202476 kb
Host smart-1344d0da-6210-41e8-a7bd-ebad81d9e4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535773350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1535773350
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1680721592
Short name T598
Test name
Test status
Simulation time 47054664645 ps
CPU time 54.84 seconds
Started Apr 18 12:47:45 PM PDT 24
Finished Apr 18 12:48:41 PM PDT 24
Peak memory 202084 kb
Host smart-181fc236-897c-4c72-a58e-492fa10ad3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680721592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1680721592
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3398622792
Short name T771
Test name
Test status
Simulation time 3813431165 ps
CPU time 1.43 seconds
Started Apr 18 12:47:48 PM PDT 24
Finished Apr 18 12:47:50 PM PDT 24
Peak memory 202028 kb
Host smart-bfd30efe-d796-4450-8399-d752505451ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398622792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3398622792
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2738665088
Short name T546
Test name
Test status
Simulation time 5638294132 ps
CPU time 6.63 seconds
Started Apr 18 12:47:47 PM PDT 24
Finished Apr 18 12:47:54 PM PDT 24
Peak memory 201968 kb
Host smart-11e376a5-82ae-4a92-abf8-6a762941e174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738665088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2738665088
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.4197740967
Short name T777
Test name
Test status
Simulation time 2795639982 ps
CPU time 8.32 seconds
Started Apr 18 12:47:47 PM PDT 24
Finished Apr 18 12:47:56 PM PDT 24
Peak memory 210696 kb
Host smart-7ce68b08-6b1b-44db-80ec-c5ad1eee8be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197740967 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.4197740967
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1021411855
Short name T484
Test name
Test status
Simulation time 379215431 ps
CPU time 1.51 seconds
Started Apr 18 12:47:53 PM PDT 24
Finished Apr 18 12:47:56 PM PDT 24
Peak memory 201984 kb
Host smart-0438fac2-48c4-44a6-bdc4-2bb62374fdf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021411855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1021411855
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1919268712
Short name T578
Test name
Test status
Simulation time 339950144076 ps
CPU time 108.9 seconds
Started Apr 18 12:47:53 PM PDT 24
Finished Apr 18 12:49:43 PM PDT 24
Peak memory 202168 kb
Host smart-dde3516e-49d0-4db9-a3d4-cc3a7b40a592
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919268712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1919268712
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2756809817
Short name T167
Test name
Test status
Simulation time 165980332385 ps
CPU time 189.36 seconds
Started Apr 18 12:47:54 PM PDT 24
Finished Apr 18 12:51:05 PM PDT 24
Peak memory 202336 kb
Host smart-68d7da51-a6fd-4116-b1bf-1a22c8d227a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756809817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2756809817
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3963693295
Short name T216
Test name
Test status
Simulation time 487266749525 ps
CPU time 567.42 seconds
Started Apr 18 12:47:52 PM PDT 24
Finished Apr 18 12:57:20 PM PDT 24
Peak memory 202336 kb
Host smart-4d2afabe-f6bb-46e4-8ac3-a86c27fb1f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963693295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3963693295
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.98330092
Short name T769
Test name
Test status
Simulation time 327561191020 ps
CPU time 195.43 seconds
Started Apr 18 12:47:56 PM PDT 24
Finished Apr 18 12:51:14 PM PDT 24
Peak memory 202300 kb
Host smart-cc78ddb9-548b-4f84-8853-a40a51fa10e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=98330092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt
_fixed.98330092
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3935296124
Short name T319
Test name
Test status
Simulation time 324151484839 ps
CPU time 785.93 seconds
Started Apr 18 12:47:58 PM PDT 24
Finished Apr 18 01:01:05 PM PDT 24
Peak memory 202288 kb
Host smart-8d11ea46-a326-4fe5-ae0f-c947464a7929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935296124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3935296124
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3602029778
Short name T640
Test name
Test status
Simulation time 330283068964 ps
CPU time 822.95 seconds
Started Apr 18 12:47:55 PM PDT 24
Finished Apr 18 01:01:39 PM PDT 24
Peak memory 202220 kb
Host smart-6ce1991d-4094-484e-9860-a4596570a731
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602029778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3602029778
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2024561141
Short name T163
Test name
Test status
Simulation time 574117963609 ps
CPU time 162.27 seconds
Started Apr 18 12:47:52 PM PDT 24
Finished Apr 18 12:50:36 PM PDT 24
Peak memory 202100 kb
Host smart-28e5d29f-4fd6-496f-90dd-8c57200bbcfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024561141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2024561141
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4194053354
Short name T731
Test name
Test status
Simulation time 203940953653 ps
CPU time 120.67 seconds
Started Apr 18 12:47:53 PM PDT 24
Finished Apr 18 12:49:55 PM PDT 24
Peak memory 202148 kb
Host smart-ccedb4eb-ab61-4c79-bc79-ba91beb3a360
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194053354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4194053354
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2921743488
Short name T229
Test name
Test status
Simulation time 122112040200 ps
CPU time 634.29 seconds
Started Apr 18 12:47:52 PM PDT 24
Finished Apr 18 12:58:27 PM PDT 24
Peak memory 202548 kb
Host smart-f2622357-9545-4ee3-8fe5-80dbd841f6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921743488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2921743488
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3308007328
Short name T467
Test name
Test status
Simulation time 27296983572 ps
CPU time 68.96 seconds
Started Apr 18 12:47:54 PM PDT 24
Finished Apr 18 12:49:04 PM PDT 24
Peak memory 202276 kb
Host smart-0a5c476f-a66c-40de-9bc6-4c60a67ace16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308007328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3308007328
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.4126139021
Short name T786
Test name
Test status
Simulation time 4345807264 ps
CPU time 3.46 seconds
Started Apr 18 12:47:56 PM PDT 24
Finished Apr 18 12:48:02 PM PDT 24
Peak memory 202064 kb
Host smart-19c17769-b1b6-491f-8beb-9735896cd892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126139021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4126139021
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3945929401
Short name T382
Test name
Test status
Simulation time 6094551868 ps
CPU time 7.66 seconds
Started Apr 18 12:47:46 PM PDT 24
Finished Apr 18 12:47:54 PM PDT 24
Peak memory 201984 kb
Host smart-96afebb1-cc66-4805-9931-efcfb5e6c593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945929401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3945929401
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1137887368
Short name T556
Test name
Test status
Simulation time 106179778060 ps
CPU time 289.23 seconds
Started Apr 18 12:47:52 PM PDT 24
Finished Apr 18 12:52:42 PM PDT 24
Peak memory 210748 kb
Host smart-3f298400-f932-4986-89b7-e12abdd7682e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137887368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1137887368
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4133764545
Short name T271
Test name
Test status
Simulation time 14445146580 ps
CPU time 32.13 seconds
Started Apr 18 12:47:54 PM PDT 24
Finished Apr 18 12:48:27 PM PDT 24
Peak memory 202236 kb
Host smart-baa4d668-2db3-4ef8-9c0a-b394c6c1a386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133764545 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4133764545
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1822288551
Short name T501
Test name
Test status
Simulation time 334519543 ps
CPU time 1.32 seconds
Started Apr 18 12:47:59 PM PDT 24
Finished Apr 18 12:48:01 PM PDT 24
Peak memory 201932 kb
Host smart-4b12dbaf-2f26-49b4-9482-6369711804f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822288551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1822288551
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1330298221
Short name T343
Test name
Test status
Simulation time 380997375848 ps
CPU time 134.78 seconds
Started Apr 18 12:47:58 PM PDT 24
Finished Apr 18 12:50:14 PM PDT 24
Peak memory 202220 kb
Host smart-0a06a03f-0f33-4581-8624-fad559b50fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330298221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1330298221
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3440872757
Short name T205
Test name
Test status
Simulation time 328406599193 ps
CPU time 189.91 seconds
Started Apr 18 12:47:55 PM PDT 24
Finished Apr 18 12:51:06 PM PDT 24
Peak memory 202244 kb
Host smart-4afbe904-698f-49db-91b4-83c601607548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440872757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3440872757
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2618311938
Short name T438
Test name
Test status
Simulation time 500389956880 ps
CPU time 249.7 seconds
Started Apr 18 12:47:53 PM PDT 24
Finished Apr 18 12:52:05 PM PDT 24
Peak memory 202408 kb
Host smart-3b70303e-1e60-4782-86f6-3ca0c225ee42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618311938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2618311938
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2643461557
Short name T663
Test name
Test status
Simulation time 325778767177 ps
CPU time 807.56 seconds
Started Apr 18 12:47:55 PM PDT 24
Finished Apr 18 01:01:24 PM PDT 24
Peak memory 202288 kb
Host smart-1df71209-37e0-45d3-a4c5-d357da40eacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643461557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2643461557
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.847028694
Short name T9
Test name
Test status
Simulation time 162407208594 ps
CPU time 95.36 seconds
Started Apr 18 12:47:55 PM PDT 24
Finished Apr 18 12:49:31 PM PDT 24
Peak memory 202188 kb
Host smart-0f51c169-eba0-4f1b-80d5-94edbb9469e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=847028694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.847028694
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.406332683
Short name T145
Test name
Test status
Simulation time 539601265828 ps
CPU time 345.7 seconds
Started Apr 18 12:48:06 PM PDT 24
Finished Apr 18 12:53:53 PM PDT 24
Peak memory 202200 kb
Host smart-d5f23af1-ce77-4233-8689-6f48b6872b32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406332683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.406332683
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2741137341
Short name T518
Test name
Test status
Simulation time 196727361515 ps
CPU time 103.05 seconds
Started Apr 18 12:48:01 PM PDT 24
Finished Apr 18 12:49:44 PM PDT 24
Peak memory 202200 kb
Host smart-c233269d-0402-48c7-b29f-a433aadd2ebf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741137341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2741137341
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3001345073
Short name T665
Test name
Test status
Simulation time 29383095204 ps
CPU time 11.43 seconds
Started Apr 18 12:47:58 PM PDT 24
Finished Apr 18 12:48:10 PM PDT 24
Peak memory 202056 kb
Host smart-26981f48-614a-4a11-93eb-32b83656d631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001345073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3001345073
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1391630610
Short name T499
Test name
Test status
Simulation time 2936064643 ps
CPU time 6.96 seconds
Started Apr 18 12:47:59 PM PDT 24
Finished Apr 18 12:48:06 PM PDT 24
Peak memory 202064 kb
Host smart-08630f53-5fab-40e1-8023-60f593884bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391630610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1391630610
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3864389544
Short name T664
Test name
Test status
Simulation time 5669790156 ps
CPU time 3.11 seconds
Started Apr 18 12:47:54 PM PDT 24
Finished Apr 18 12:47:59 PM PDT 24
Peak memory 202064 kb
Host smart-a3262ffa-bf6b-4010-bb07-9f0fab738d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864389544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3864389544
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2761878916
Short name T604
Test name
Test status
Simulation time 136781450898 ps
CPU time 613.72 seconds
Started Apr 18 12:47:57 PM PDT 24
Finished Apr 18 12:58:12 PM PDT 24
Peak memory 211172 kb
Host smart-a417be26-4672-4969-9e99-cee37fed8a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761878916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2761878916
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3548013554
Short name T109
Test name
Test status
Simulation time 35383402353 ps
CPU time 124.38 seconds
Started Apr 18 12:47:57 PM PDT 24
Finished Apr 18 12:50:03 PM PDT 24
Peak memory 210808 kb
Host smart-c0e2e7c4-ed29-469e-a777-1e4224771472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548013554 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3548013554
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.570007127
Short name T443
Test name
Test status
Simulation time 328079257 ps
CPU time 0.79 seconds
Started Apr 18 12:48:05 PM PDT 24
Finished Apr 18 12:48:07 PM PDT 24
Peak memory 201952 kb
Host smart-be0d03d2-0ca9-45a8-97ba-7b391ff3d18f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570007127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.570007127
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.4124858131
Short name T579
Test name
Test status
Simulation time 164608114508 ps
CPU time 384.1 seconds
Started Apr 18 12:47:57 PM PDT 24
Finished Apr 18 12:54:23 PM PDT 24
Peak memory 202324 kb
Host smart-9d17b668-4831-4622-a404-2da1838bded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124858131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4124858131
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1749591117
Short name T406
Test name
Test status
Simulation time 329337685460 ps
CPU time 395.78 seconds
Started Apr 18 12:48:00 PM PDT 24
Finished Apr 18 12:54:37 PM PDT 24
Peak memory 202312 kb
Host smart-c403e15e-f796-4a19-b8f7-9305e409d869
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749591117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1749591117
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3122038169
Short name T179
Test name
Test status
Simulation time 161450095880 ps
CPU time 95.79 seconds
Started Apr 18 12:47:57 PM PDT 24
Finished Apr 18 12:49:34 PM PDT 24
Peak memory 202268 kb
Host smart-711f191d-51f0-41b9-8368-e0c2cf4b73bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122038169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3122038169
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2180946478
Short name T626
Test name
Test status
Simulation time 497799890575 ps
CPU time 1034.89 seconds
Started Apr 18 12:47:56 PM PDT 24
Finished Apr 18 01:05:13 PM PDT 24
Peak memory 202308 kb
Host smart-23209788-c546-424c-bcd3-822f75395ab0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180946478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2180946478
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3140314692
Short name T671
Test name
Test status
Simulation time 406596663164 ps
CPU time 237.11 seconds
Started Apr 18 12:47:57 PM PDT 24
Finished Apr 18 12:51:56 PM PDT 24
Peak memory 202144 kb
Host smart-c9671b59-d10e-4ffa-bc7c-cabf787da5f5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140314692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3140314692
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1318661023
Short name T525
Test name
Test status
Simulation time 22295473070 ps
CPU time 14.4 seconds
Started Apr 18 12:48:03 PM PDT 24
Finished Apr 18 12:48:18 PM PDT 24
Peak memory 201968 kb
Host smart-07270019-f159-49cc-a541-c02884900216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318661023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1318661023
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.751047764
Short name T102
Test name
Test status
Simulation time 4702809222 ps
CPU time 3.46 seconds
Started Apr 18 12:48:04 PM PDT 24
Finished Apr 18 12:48:09 PM PDT 24
Peak memory 202056 kb
Host smart-864b6448-0607-47e1-afbe-784263814959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751047764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.751047764
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1284478794
Short name T543
Test name
Test status
Simulation time 6039317501 ps
CPU time 4.13 seconds
Started Apr 18 12:47:57 PM PDT 24
Finished Apr 18 12:48:03 PM PDT 24
Peak memory 202068 kb
Host smart-05d9e09c-13a2-4d13-847a-9b399cbf7c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284478794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1284478794
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3761433981
Short name T590
Test name
Test status
Simulation time 388809657 ps
CPU time 1.44 seconds
Started Apr 18 12:48:12 PM PDT 24
Finished Apr 18 12:48:15 PM PDT 24
Peak memory 201972 kb
Host smart-8b74b2d4-7b79-4588-8c79-cd3af91545ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761433981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3761433981
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2304124010
Short name T261
Test name
Test status
Simulation time 348585113660 ps
CPU time 413.5 seconds
Started Apr 18 12:48:09 PM PDT 24
Finished Apr 18 12:55:03 PM PDT 24
Peak memory 202192 kb
Host smart-7f9ae794-ccce-40b8-b6ff-08f4c1614e20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304124010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2304124010
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3804905866
Short name T741
Test name
Test status
Simulation time 162016470817 ps
CPU time 189.18 seconds
Started Apr 18 12:48:10 PM PDT 24
Finished Apr 18 12:51:20 PM PDT 24
Peak memory 202236 kb
Host smart-67217b67-7a19-4b7f-89f1-278accff9d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804905866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3804905866
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3109109987
Short name T576
Test name
Test status
Simulation time 165844813775 ps
CPU time 135.66 seconds
Started Apr 18 12:48:10 PM PDT 24
Finished Apr 18 12:50:26 PM PDT 24
Peak memory 202236 kb
Host smart-5499c151-0364-4057-bfbb-fd8f2d1a32a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109109987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3109109987
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3455942604
Short name T359
Test name
Test status
Simulation time 328275131054 ps
CPU time 725.78 seconds
Started Apr 18 12:48:06 PM PDT 24
Finished Apr 18 01:00:13 PM PDT 24
Peak memory 202256 kb
Host smart-43ff5af5-b445-4228-880e-5e15ee763bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455942604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3455942604
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1362604618
Short name T752
Test name
Test status
Simulation time 331887114970 ps
CPU time 747.71 seconds
Started Apr 18 12:48:05 PM PDT 24
Finished Apr 18 01:00:34 PM PDT 24
Peak memory 202128 kb
Host smart-1277e217-e0ec-4662-a92e-1ce8c01da30a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362604618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1362604618
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1974266695
Short name T788
Test name
Test status
Simulation time 608359191549 ps
CPU time 325.17 seconds
Started Apr 18 12:48:08 PM PDT 24
Finished Apr 18 12:53:34 PM PDT 24
Peak memory 202256 kb
Host smart-a2a30282-be7d-4e8b-8a11-7d92a56a5e46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974266695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1974266695
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.900390490
Short name T638
Test name
Test status
Simulation time 111743596034 ps
CPU time 600.38 seconds
Started Apr 18 12:48:09 PM PDT 24
Finished Apr 18 12:58:10 PM PDT 24
Peak memory 202508 kb
Host smart-d9204fe3-a6a7-4eea-a888-4e1238a21339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900390490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.900390490
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2294867636
Short name T649
Test name
Test status
Simulation time 23640335108 ps
CPU time 32.78 seconds
Started Apr 18 12:48:08 PM PDT 24
Finished Apr 18 12:48:42 PM PDT 24
Peak memory 202008 kb
Host smart-32986390-7307-46a2-8e50-66a9e61c54f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294867636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2294867636
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1897864146
Short name T552
Test name
Test status
Simulation time 4318841717 ps
CPU time 10.34 seconds
Started Apr 18 12:48:11 PM PDT 24
Finished Apr 18 12:48:22 PM PDT 24
Peak memory 202064 kb
Host smart-026d0c22-e230-4815-a317-5d1e0a3c780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897864146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1897864146
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.422556413
Short name T2
Test name
Test status
Simulation time 5732224086 ps
CPU time 3.95 seconds
Started Apr 18 12:48:09 PM PDT 24
Finished Apr 18 12:48:14 PM PDT 24
Peak memory 202072 kb
Host smart-3dbeaf9e-ceb1-4f3e-87c8-b968e76b2173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422556413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.422556413
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3774150426
Short name T647
Test name
Test status
Simulation time 182527847510 ps
CPU time 366.77 seconds
Started Apr 18 12:48:13 PM PDT 24
Finished Apr 18 12:54:21 PM PDT 24
Peak memory 202240 kb
Host smart-68811506-5071-4b6f-b30b-ebd759352d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774150426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3774150426
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1758463894
Short name T471
Test name
Test status
Simulation time 554540541 ps
CPU time 0.86 seconds
Started Apr 18 12:48:19 PM PDT 24
Finished Apr 18 12:48:21 PM PDT 24
Peak memory 202172 kb
Host smart-f64a8a1c-b29e-4689-8e4d-a40b384f71ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758463894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1758463894
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3947240054
Short name T783
Test name
Test status
Simulation time 160681447029 ps
CPU time 153.19 seconds
Started Apr 18 12:48:15 PM PDT 24
Finished Apr 18 12:50:49 PM PDT 24
Peak memory 202248 kb
Host smart-15b4284e-e07a-4cce-8b43-ad485d7f1f99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947240054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3947240054
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3968173625
Short name T164
Test name
Test status
Simulation time 491395914695 ps
CPU time 303.28 seconds
Started Apr 18 12:48:14 PM PDT 24
Finished Apr 18 12:53:19 PM PDT 24
Peak memory 202112 kb
Host smart-27cc05ec-41ad-43a2-87e1-e4b38d4ac563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968173625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3968173625
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1861314719
Short name T749
Test name
Test status
Simulation time 486359625915 ps
CPU time 227.13 seconds
Started Apr 18 12:48:13 PM PDT 24
Finished Apr 18 12:52:01 PM PDT 24
Peak memory 202100 kb
Host smart-872dcec8-3b27-4dc0-8fcf-0db87de97324
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861314719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1861314719
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2169882271
Short name T33
Test name
Test status
Simulation time 492529081084 ps
CPU time 1110.8 seconds
Started Apr 18 12:48:13 PM PDT 24
Finished Apr 18 01:06:45 PM PDT 24
Peak memory 202220 kb
Host smart-f82bc509-a360-4a56-b5e1-7d3a597fc397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169882271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2169882271
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1859819023
Short name T388
Test name
Test status
Simulation time 333455734356 ps
CPU time 751.83 seconds
Started Apr 18 12:48:15 PM PDT 24
Finished Apr 18 01:00:48 PM PDT 24
Peak memory 202292 kb
Host smart-44e8bc55-80ab-477e-839e-3f7045afd4d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859819023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1859819023
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1730108259
Short name T184
Test name
Test status
Simulation time 349641958165 ps
CPU time 200.74 seconds
Started Apr 18 12:48:13 PM PDT 24
Finished Apr 18 12:51:35 PM PDT 24
Peak memory 202300 kb
Host smart-e7a9e2df-d87d-4020-a03a-6ca4f54404fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730108259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1730108259
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.28527984
Short name T700
Test name
Test status
Simulation time 204443621234 ps
CPU time 106.5 seconds
Started Apr 18 12:48:15 PM PDT 24
Finished Apr 18 12:50:02 PM PDT 24
Peak memory 202092 kb
Host smart-3579dac2-5909-446c-a8c7-1a191d2b9869
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28527984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.a
dc_ctrl_filters_wakeup_fixed.28527984
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.30446482
Short name T381
Test name
Test status
Simulation time 115450265456 ps
CPU time 388.64 seconds
Started Apr 18 12:48:20 PM PDT 24
Finished Apr 18 12:54:49 PM PDT 24
Peak memory 202464 kb
Host smart-5ff1ee74-71a9-4830-84e9-fd40ea48da09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30446482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.30446482
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.4199526832
Short name T619
Test name
Test status
Simulation time 38022960243 ps
CPU time 24.13 seconds
Started Apr 18 12:48:20 PM PDT 24
Finished Apr 18 12:48:45 PM PDT 24
Peak memory 202088 kb
Host smart-86001b9b-8262-45bc-8c88-1f3460f53bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199526832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.4199526832
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1515483792
Short name T401
Test name
Test status
Simulation time 5391190015 ps
CPU time 4.15 seconds
Started Apr 18 12:48:15 PM PDT 24
Finished Apr 18 12:48:20 PM PDT 24
Peak memory 202052 kb
Host smart-a7d712c6-b737-45e3-a396-ea4ff658eebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515483792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1515483792
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2751950239
Short name T601
Test name
Test status
Simulation time 6161738222 ps
CPU time 2.75 seconds
Started Apr 18 12:48:14 PM PDT 24
Finished Apr 18 12:48:18 PM PDT 24
Peak memory 201988 kb
Host smart-abc7c5fe-3339-45ea-8da8-4d257334bda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751950239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2751950239
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2411196513
Short name T657
Test name
Test status
Simulation time 41637061198 ps
CPU time 97.66 seconds
Started Apr 18 12:48:23 PM PDT 24
Finished Apr 18 12:50:02 PM PDT 24
Peak memory 202332 kb
Host smart-1f5a1007-1be1-48c9-9cef-747efa9e3414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411196513 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2411196513
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1671263177
Short name T464
Test name
Test status
Simulation time 354817988 ps
CPU time 1.39 seconds
Started Apr 18 12:48:31 PM PDT 24
Finished Apr 18 12:48:33 PM PDT 24
Peak memory 201868 kb
Host smart-0fee5a65-9bda-4eaa-8e34-6a1771f4550f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671263177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1671263177
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3431310035
Short name T285
Test name
Test status
Simulation time 166365114135 ps
CPU time 192.87 seconds
Started Apr 18 12:48:26 PM PDT 24
Finished Apr 18 12:51:39 PM PDT 24
Peak memory 202296 kb
Host smart-2df86f6c-fcd7-4c25-a0b9-e53d42f97bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431310035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3431310035
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.64972766
Short name T168
Test name
Test status
Simulation time 164587295950 ps
CPU time 398.32 seconds
Started Apr 18 12:48:20 PM PDT 24
Finished Apr 18 12:54:59 PM PDT 24
Peak memory 202308 kb
Host smart-9bb6cdf2-080f-41f0-930f-c96d7d8aa45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64972766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.64972766
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1551295447
Short name T110
Test name
Test status
Simulation time 488400911692 ps
CPU time 1125.17 seconds
Started Apr 18 12:48:26 PM PDT 24
Finished Apr 18 01:07:12 PM PDT 24
Peak memory 202116 kb
Host smart-c646608f-4c2c-4985-b415-dfc7c06deacd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551295447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1551295447
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1505318118
Short name T141
Test name
Test status
Simulation time 158573223000 ps
CPU time 95.82 seconds
Started Apr 18 12:48:18 PM PDT 24
Finished Apr 18 12:49:55 PM PDT 24
Peak memory 202204 kb
Host smart-d6367063-d344-4b0c-98c2-db1653585a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505318118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1505318118
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2196730185
Short name T509
Test name
Test status
Simulation time 165655282793 ps
CPU time 83.87 seconds
Started Apr 18 12:48:21 PM PDT 24
Finished Apr 18 12:49:45 PM PDT 24
Peak memory 202208 kb
Host smart-3324f18e-985b-4247-87ab-6802e93b2caf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196730185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2196730185
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2232548363
Short name T162
Test name
Test status
Simulation time 351773465076 ps
CPU time 301.74 seconds
Started Apr 18 12:48:26 PM PDT 24
Finished Apr 18 12:53:28 PM PDT 24
Peak memory 202228 kb
Host smart-b1790bf5-ffd3-4179-8c7c-f4b62125585f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232548363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2232548363
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.639311796
Short name T218
Test name
Test status
Simulation time 200813193004 ps
CPU time 229.57 seconds
Started Apr 18 12:48:27 PM PDT 24
Finished Apr 18 12:52:17 PM PDT 24
Peak memory 202148 kb
Host smart-2b5e3c9f-622c-4571-a250-85162264039f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639311796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.639311796
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3720566317
Short name T53
Test name
Test status
Simulation time 88759200299 ps
CPU time 258.24 seconds
Started Apr 18 12:48:27 PM PDT 24
Finished Apr 18 12:52:45 PM PDT 24
Peak memory 202592 kb
Host smart-53d80ed2-1c8b-4b39-8821-9c3afa646fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720566317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3720566317
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2107191838
Short name T407
Test name
Test status
Simulation time 25923344774 ps
CPU time 57.85 seconds
Started Apr 18 12:48:25 PM PDT 24
Finished Apr 18 12:49:24 PM PDT 24
Peak memory 202080 kb
Host smart-0e2c5c7a-bb79-4fb7-8fc9-d65f6f4bb433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107191838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2107191838
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.4164638505
Short name T441
Test name
Test status
Simulation time 4965961041 ps
CPU time 8.05 seconds
Started Apr 18 12:48:25 PM PDT 24
Finished Apr 18 12:48:34 PM PDT 24
Peak memory 201956 kb
Host smart-72aed12d-5e0e-4ee4-a64a-5a8bfd3f801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164638505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4164638505
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2865259879
Short name T496
Test name
Test status
Simulation time 5871602574 ps
CPU time 7.74 seconds
Started Apr 18 12:48:22 PM PDT 24
Finished Apr 18 12:48:30 PM PDT 24
Peak memory 202016 kb
Host smart-acddd9cc-2054-4a00-ac2c-463f70dc1cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865259879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2865259879
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2071461500
Short name T656
Test name
Test status
Simulation time 174863214305 ps
CPU time 408.33 seconds
Started Apr 18 12:48:27 PM PDT 24
Finished Apr 18 12:55:16 PM PDT 24
Peak memory 202540 kb
Host smart-117b7f0a-0ca3-4940-ab9f-ab9f5905df23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071461500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2071461500
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2550316031
Short name T529
Test name
Test status
Simulation time 75151675960 ps
CPU time 93.9 seconds
Started Apr 18 12:48:24 PM PDT 24
Finished Apr 18 12:49:59 PM PDT 24
Peak memory 210968 kb
Host smart-73148e53-38fa-4897-ba81-57c4e0bef048
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550316031 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2550316031
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2318937275
Short name T27
Test name
Test status
Simulation time 309145109 ps
CPU time 0.87 seconds
Started Apr 18 12:48:40 PM PDT 24
Finished Apr 18 12:48:41 PM PDT 24
Peak memory 201892 kb
Host smart-7db72262-e279-47f5-b98f-de1a863c1327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318937275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2318937275
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1125971046
Short name T79
Test name
Test status
Simulation time 461017135351 ps
CPU time 492.58 seconds
Started Apr 18 12:48:33 PM PDT 24
Finished Apr 18 12:56:47 PM PDT 24
Peak memory 202316 kb
Host smart-8beba128-90bb-4357-9d67-c1768963d367
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125971046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1125971046
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3925820901
Short name T213
Test name
Test status
Simulation time 165525309077 ps
CPU time 371.6 seconds
Started Apr 18 12:48:31 PM PDT 24
Finished Apr 18 12:54:43 PM PDT 24
Peak memory 202164 kb
Host smart-83f9e015-b8af-4018-aa41-dda0f1f6d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925820901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3925820901
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.276574529
Short name T445
Test name
Test status
Simulation time 330802851474 ps
CPU time 389.03 seconds
Started Apr 18 12:48:32 PM PDT 24
Finished Apr 18 12:55:03 PM PDT 24
Peak memory 202200 kb
Host smart-147aec68-ea73-4ad9-a6f7-3b33a0dfb1a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=276574529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.276574529
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3248129713
Short name T195
Test name
Test status
Simulation time 484371510698 ps
CPU time 66.24 seconds
Started Apr 18 12:48:33 PM PDT 24
Finished Apr 18 12:49:40 PM PDT 24
Peak memory 202156 kb
Host smart-c2868932-6410-444d-827a-514f3ac09975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248129713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3248129713
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.68841795
Short name T450
Test name
Test status
Simulation time 163553389454 ps
CPU time 98.63 seconds
Started Apr 18 12:48:32 PM PDT 24
Finished Apr 18 12:50:12 PM PDT 24
Peak memory 202184 kb
Host smart-c3a331fc-a1a5-42b9-ae04-b7e50190e272
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=68841795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixed
.68841795
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1243391569
Short name T623
Test name
Test status
Simulation time 190321391279 ps
CPU time 104.04 seconds
Started Apr 18 12:48:32 PM PDT 24
Finished Apr 18 12:50:17 PM PDT 24
Peak memory 202252 kb
Host smart-0a037460-1d0f-419c-a496-933d9545fcfc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243391569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1243391569
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1290468194
Short name T719
Test name
Test status
Simulation time 115291443671 ps
CPU time 373.47 seconds
Started Apr 18 12:48:39 PM PDT 24
Finished Apr 18 12:54:53 PM PDT 24
Peak memory 202544 kb
Host smart-7182fbe1-e74d-41f4-b17b-eabfe4c6f9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290468194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1290468194
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1754181745
Short name T713
Test name
Test status
Simulation time 25135174559 ps
CPU time 7.13 seconds
Started Apr 18 12:48:32 PM PDT 24
Finished Apr 18 12:48:41 PM PDT 24
Peak memory 201964 kb
Host smart-7d065b6b-b0fb-4e2b-bfd2-aff055f912ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754181745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1754181745
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2255615003
Short name T487
Test name
Test status
Simulation time 3022038718 ps
CPU time 7.21 seconds
Started Apr 18 12:48:32 PM PDT 24
Finished Apr 18 12:48:40 PM PDT 24
Peak memory 201944 kb
Host smart-b7986346-0e8b-41a0-a5f4-c05b0e20c673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255615003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2255615003
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1856259999
Short name T439
Test name
Test status
Simulation time 5776016379 ps
CPU time 2.47 seconds
Started Apr 18 12:48:33 PM PDT 24
Finished Apr 18 12:48:36 PM PDT 24
Peak memory 202088 kb
Host smart-257b1d00-3ebb-42ea-9f34-069075d533ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856259999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1856259999
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2719785099
Short name T342
Test name
Test status
Simulation time 142819297618 ps
CPU time 149.32 seconds
Started Apr 18 12:48:38 PM PDT 24
Finished Apr 18 12:51:08 PM PDT 24
Peak memory 218580 kb
Host smart-d845fe85-70b7-4bff-a5d6-2014796ad9fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719785099 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2719785099
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2160836586
Short name T695
Test name
Test status
Simulation time 354385241 ps
CPU time 0.8 seconds
Started Apr 18 12:48:49 PM PDT 24
Finished Apr 18 12:48:50 PM PDT 24
Peak memory 201968 kb
Host smart-076c1356-7b31-41d8-b358-f9931364a237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160836586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2160836586
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1602513953
Short name T768
Test name
Test status
Simulation time 384047553026 ps
CPU time 413.64 seconds
Started Apr 18 12:48:45 PM PDT 24
Finished Apr 18 12:55:40 PM PDT 24
Peak memory 202232 kb
Host smart-eeea324a-fa0f-4f15-a504-d034253339d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602513953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1602513953
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.711975347
Short name T508
Test name
Test status
Simulation time 171161704866 ps
CPU time 52.5 seconds
Started Apr 18 12:48:46 PM PDT 24
Finished Apr 18 12:49:39 PM PDT 24
Peak memory 202280 kb
Host smart-b8287056-ea43-4cb2-bd00-776c204c1a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711975347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.711975347
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3156394542
Short name T781
Test name
Test status
Simulation time 326098267027 ps
CPU time 752.36 seconds
Started Apr 18 12:48:42 PM PDT 24
Finished Apr 18 01:01:16 PM PDT 24
Peak memory 202300 kb
Host smart-5206572f-381f-47f8-8716-ebde43bbd6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156394542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3156394542
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3505071670
Short name T94
Test name
Test status
Simulation time 164542353946 ps
CPU time 371.4 seconds
Started Apr 18 12:48:42 PM PDT 24
Finished Apr 18 12:54:55 PM PDT 24
Peak memory 202208 kb
Host smart-d08f14b5-7a40-4621-b853-598dcea4e3e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505071670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3505071670
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.468937120
Short name T512
Test name
Test status
Simulation time 489159010646 ps
CPU time 283.2 seconds
Started Apr 18 12:48:38 PM PDT 24
Finished Apr 18 12:53:22 PM PDT 24
Peak memory 202248 kb
Host smart-5b92800f-9780-4d28-966a-7060d359437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468937120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.468937120
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3003010807
Short name T488
Test name
Test status
Simulation time 330082798113 ps
CPU time 773.96 seconds
Started Apr 18 12:48:37 PM PDT 24
Finished Apr 18 01:01:32 PM PDT 24
Peak memory 202132 kb
Host smart-d9550f47-1274-4fb8-b7ee-2334377821a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003010807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3003010807
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.500583936
Short name T453
Test name
Test status
Simulation time 401022666517 ps
CPU time 359.88 seconds
Started Apr 18 12:48:42 PM PDT 24
Finished Apr 18 12:54:43 PM PDT 24
Peak memory 202232 kb
Host smart-9ac44652-ea0b-417c-8cb4-f3cf226655eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500583936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.500583936
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3215274621
Short name T247
Test name
Test status
Simulation time 111516187999 ps
CPU time 387.68 seconds
Started Apr 18 12:48:43 PM PDT 24
Finished Apr 18 12:55:11 PM PDT 24
Peak memory 202648 kb
Host smart-ec2d5637-8db0-483b-8cca-83e0e86277f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215274621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3215274621
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3073566297
Short name T732
Test name
Test status
Simulation time 23792362372 ps
CPU time 14.11 seconds
Started Apr 18 12:48:44 PM PDT 24
Finished Apr 18 12:48:58 PM PDT 24
Peak memory 202056 kb
Host smart-4ce80e0e-65a4-486c-b7f9-7a853922db5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073566297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3073566297
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.693569235
Short name T557
Test name
Test status
Simulation time 4352792787 ps
CPU time 2 seconds
Started Apr 18 12:48:44 PM PDT 24
Finished Apr 18 12:48:46 PM PDT 24
Peak memory 202052 kb
Host smart-a602b6f4-0bfe-4143-a6d4-7d59d052818d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693569235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.693569235
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1784464629
Short name T386
Test name
Test status
Simulation time 5948662715 ps
CPU time 8.5 seconds
Started Apr 18 12:48:39 PM PDT 24
Finished Apr 18 12:48:48 PM PDT 24
Peak memory 201956 kb
Host smart-a5b08c46-ea0d-4cd5-9a2b-b383ba000d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784464629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1784464629
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1444275919
Short name T345
Test name
Test status
Simulation time 706269397166 ps
CPU time 1175.78 seconds
Started Apr 18 12:48:50 PM PDT 24
Finished Apr 18 01:08:26 PM PDT 24
Peak memory 210776 kb
Host smart-87e567d4-264e-4f6b-9943-863241677113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444275919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1444275919
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1229186374
Short name T44
Test name
Test status
Simulation time 321415004820 ps
CPU time 412.28 seconds
Started Apr 18 12:48:49 PM PDT 24
Finished Apr 18 12:55:41 PM PDT 24
Peak memory 210968 kb
Host smart-44829e07-d6c9-42ec-aad6-cc4515969307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229186374 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1229186374
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.645819643
Short name T169
Test name
Test status
Simulation time 341164993 ps
CPU time 0.98 seconds
Started Apr 18 12:48:55 PM PDT 24
Finished Apr 18 12:48:57 PM PDT 24
Peak memory 201936 kb
Host smart-6eae8b55-96e7-49a2-8f5e-f429c6dbb4a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645819643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.645819643
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3799149033
Short name T214
Test name
Test status
Simulation time 618759048169 ps
CPU time 568.71 seconds
Started Apr 18 12:48:56 PM PDT 24
Finished Apr 18 12:58:25 PM PDT 24
Peak memory 202256 kb
Host smart-3e349f23-362a-4495-9150-e7d27b55e93b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799149033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3799149033
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.546075363
Short name T331
Test name
Test status
Simulation time 538723325032 ps
CPU time 1150.2 seconds
Started Apr 18 12:48:56 PM PDT 24
Finished Apr 18 01:08:08 PM PDT 24
Peak memory 202256 kb
Host smart-d99afaa7-eb7d-4750-b264-26b001d3e2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546075363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.546075363
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1213244174
Short name T137
Test name
Test status
Simulation time 492273583597 ps
CPU time 1240.83 seconds
Started Apr 18 12:48:51 PM PDT 24
Finished Apr 18 01:09:33 PM PDT 24
Peak memory 202308 kb
Host smart-d9994b97-987c-4582-90c6-49706044987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213244174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1213244174
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1815817510
Short name T507
Test name
Test status
Simulation time 163201342096 ps
CPU time 93.01 seconds
Started Apr 18 12:48:50 PM PDT 24
Finished Apr 18 12:50:24 PM PDT 24
Peak memory 202268 kb
Host smart-de2d2a50-b4bc-41a4-8170-14ef3a499479
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815817510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1815817510
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2232391359
Short name T620
Test name
Test status
Simulation time 496504445388 ps
CPU time 1117.44 seconds
Started Apr 18 12:48:50 PM PDT 24
Finished Apr 18 01:07:28 PM PDT 24
Peak memory 202280 kb
Host smart-ca55269d-b58a-4028-b646-651d62954f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232391359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2232391359
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2977390200
Short name T6
Test name
Test status
Simulation time 492034969790 ps
CPU time 557.39 seconds
Started Apr 18 12:48:49 PM PDT 24
Finished Apr 18 12:58:07 PM PDT 24
Peak memory 202272 kb
Host smart-63715e6b-5a8a-49bb-8255-9656c55b6006
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977390200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2977390200
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.724086807
Short name T472
Test name
Test status
Simulation time 194485344918 ps
CPU time 57.01 seconds
Started Apr 18 12:48:57 PM PDT 24
Finished Apr 18 12:49:55 PM PDT 24
Peak memory 202240 kb
Host smart-a119ce64-2194-40c0-9a2e-f4fbe948d648
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724086807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.724086807
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1198882054
Short name T500
Test name
Test status
Simulation time 612403545815 ps
CPU time 1336.8 seconds
Started Apr 18 12:49:00 PM PDT 24
Finished Apr 18 01:11:17 PM PDT 24
Peak memory 202228 kb
Host smart-fceebf25-6aab-4a94-9a37-f633e905d5ed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198882054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1198882054
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2570546317
Short name T238
Test name
Test status
Simulation time 79870102066 ps
CPU time 462.99 seconds
Started Apr 18 12:48:57 PM PDT 24
Finished Apr 18 12:56:41 PM PDT 24
Peak memory 202440 kb
Host smart-7902c694-047f-4166-8100-024cfc1b46a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570546317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2570546317
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1558454798
Short name T171
Test name
Test status
Simulation time 26910216703 ps
CPU time 15.88 seconds
Started Apr 18 12:48:57 PM PDT 24
Finished Apr 18 12:49:13 PM PDT 24
Peak memory 202044 kb
Host smart-417625e3-26a1-4f35-a096-fb1c7a264e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558454798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1558454798
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3354107448
Short name T669
Test name
Test status
Simulation time 2821650652 ps
CPU time 2.02 seconds
Started Apr 18 12:48:55 PM PDT 24
Finished Apr 18 12:48:58 PM PDT 24
Peak memory 202056 kb
Host smart-e9b9b4de-a4d5-4535-9533-06aa02f94fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354107448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3354107448
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3766179990
Short name T101
Test name
Test status
Simulation time 6063565320 ps
CPU time 5.88 seconds
Started Apr 18 12:48:50 PM PDT 24
Finished Apr 18 12:48:56 PM PDT 24
Peak memory 202072 kb
Host smart-787287ac-8778-4969-8f9c-cda6cd95468e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766179990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3766179990
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1651927740
Short name T106
Test name
Test status
Simulation time 332109694407 ps
CPU time 729.03 seconds
Started Apr 18 12:49:01 PM PDT 24
Finished Apr 18 01:01:10 PM PDT 24
Peak memory 202320 kb
Host smart-fe6d97b9-75c0-40a6-92f0-2435a74af809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651927740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1651927740
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1703732103
Short name T203
Test name
Test status
Simulation time 547426754311 ps
CPU time 209.06 seconds
Started Apr 18 12:47:06 PM PDT 24
Finished Apr 18 12:50:37 PM PDT 24
Peak memory 202160 kb
Host smart-29d57f8d-58db-4f2a-9e00-d47a1486edc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703732103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1703732103
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2978672629
Short name T367
Test name
Test status
Simulation time 324374490862 ps
CPU time 754.81 seconds
Started Apr 18 12:47:01 PM PDT 24
Finished Apr 18 12:59:37 PM PDT 24
Peak memory 202248 kb
Host smart-78ea2b8e-b753-4adf-b1b5-110f74433e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978672629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2978672629
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3542526231
Short name T480
Test name
Test status
Simulation time 500082921005 ps
CPU time 297.63 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:52:02 PM PDT 24
Peak memory 202068 kb
Host smart-3c7f4d0e-f546-4c60-968c-261837d0159b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542526231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3542526231
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3666554460
Short name T146
Test name
Test status
Simulation time 482583773122 ps
CPU time 121.87 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:49:06 PM PDT 24
Peak memory 202152 kb
Host smart-6acbff23-8f4e-491f-adc3-ab0c7f26c92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666554460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3666554460
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1189420037
Short name T148
Test name
Test status
Simulation time 500055287515 ps
CPU time 571.95 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:56:36 PM PDT 24
Peak memory 202320 kb
Host smart-92b29e19-17c5-4297-862e-3e44e751fb18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189420037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1189420037
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2139926291
Short name T48
Test name
Test status
Simulation time 605257077374 ps
CPU time 1307.79 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 01:08:52 PM PDT 24
Peak memory 202120 kb
Host smart-754b3e31-e911-45fd-9a8a-4f779caadc43
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139926291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2139926291
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1598085990
Short name T778
Test name
Test status
Simulation time 96820261982 ps
CPU time 319.69 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 12:52:23 PM PDT 24
Peak memory 202480 kb
Host smart-3d7c7fcb-1e3d-4494-893d-6f26d821bbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598085990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1598085990
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3516730396
Short name T780
Test name
Test status
Simulation time 25281095542 ps
CPU time 61.66 seconds
Started Apr 18 12:47:03 PM PDT 24
Finished Apr 18 12:48:06 PM PDT 24
Peak memory 202060 kb
Host smart-e43e63fa-616b-40a8-914e-a79f8b1e3a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516730396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3516730396
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.108745662
Short name T411
Test name
Test status
Simulation time 5050016795 ps
CPU time 3.43 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 12:47:07 PM PDT 24
Peak memory 201960 kb
Host smart-15942c38-ba05-4b03-8aa2-a6db9dea201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108745662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.108745662
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2036553022
Short name T74
Test name
Test status
Simulation time 7757171571 ps
CPU time 9.37 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 12:47:12 PM PDT 24
Peak memory 218724 kb
Host smart-e3b5dd21-4fa5-4341-986d-4779fdad1664
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036553022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2036553022
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2257760109
Short name T526
Test name
Test status
Simulation time 5748165691 ps
CPU time 14.34 seconds
Started Apr 18 12:47:05 PM PDT 24
Finished Apr 18 12:47:20 PM PDT 24
Peak memory 202292 kb
Host smart-6f6d5fb2-57e6-4667-8a8a-280d9c5009ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257760109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2257760109
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2061029466
Short name T565
Test name
Test status
Simulation time 131108613550 ps
CPU time 556.46 seconds
Started Apr 18 12:47:02 PM PDT 24
Finished Apr 18 12:56:19 PM PDT 24
Peak memory 202556 kb
Host smart-737de904-6fb9-44dd-992e-61d1c9e85bad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061029466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2061029466
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1930777721
Short name T535
Test name
Test status
Simulation time 437467324 ps
CPU time 1.6 seconds
Started Apr 18 12:49:16 PM PDT 24
Finished Apr 18 12:49:18 PM PDT 24
Peak memory 201852 kb
Host smart-257eed57-4c93-4fd6-808a-14eb418971a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930777721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1930777721
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.781860437
Short name T516
Test name
Test status
Simulation time 421000346444 ps
CPU time 237.98 seconds
Started Apr 18 12:49:08 PM PDT 24
Finished Apr 18 12:53:07 PM PDT 24
Peak memory 202152 kb
Host smart-0fd2b8ae-6ae0-4ff4-9391-48b68319337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781860437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.781860437
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3559443843
Short name T440
Test name
Test status
Simulation time 488424009593 ps
CPU time 307.92 seconds
Started Apr 18 12:49:00 PM PDT 24
Finished Apr 18 12:54:09 PM PDT 24
Peak memory 202216 kb
Host smart-dded2ac8-7a79-4664-83ec-ee7ff94936d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559443843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3559443843
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.98049135
Short name T495
Test name
Test status
Simulation time 323209163097 ps
CPU time 337.5 seconds
Started Apr 18 12:49:01 PM PDT 24
Finished Apr 18 12:54:39 PM PDT 24
Peak memory 202560 kb
Host smart-64ecaca8-346e-49cc-8cb7-782417ba7d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98049135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.98049135
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3376455915
Short name T705
Test name
Test status
Simulation time 160393885938 ps
CPU time 32.47 seconds
Started Apr 18 12:49:02 PM PDT 24
Finished Apr 18 12:49:35 PM PDT 24
Peak memory 202312 kb
Host smart-62736440-05d7-446b-8d02-05afd75c669f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376455915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3376455915
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1083039314
Short name T793
Test name
Test status
Simulation time 524118151384 ps
CPU time 314.43 seconds
Started Apr 18 12:49:02 PM PDT 24
Finished Apr 18 12:54:18 PM PDT 24
Peak memory 202252 kb
Host smart-50e05710-11e7-49c8-84de-0db97d48e9f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083039314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1083039314
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2287467364
Short name T534
Test name
Test status
Simulation time 634233530939 ps
CPU time 201 seconds
Started Apr 18 12:49:06 PM PDT 24
Finished Apr 18 12:52:28 PM PDT 24
Peak memory 202080 kb
Host smart-a84088f3-48fe-426e-8e57-5a77a98d59c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287467364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2287467364
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.4057259348
Short name T200
Test name
Test status
Simulation time 36141066115 ps
CPU time 79.75 seconds
Started Apr 18 12:49:07 PM PDT 24
Finished Apr 18 12:50:27 PM PDT 24
Peak memory 202032 kb
Host smart-56dfe882-251e-46c2-9f79-bd6293ccf750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057259348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.4057259348
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1225563399
Short name T726
Test name
Test status
Simulation time 2598954951 ps
CPU time 7.03 seconds
Started Apr 18 12:49:07 PM PDT 24
Finished Apr 18 12:49:15 PM PDT 24
Peak memory 201948 kb
Host smart-15c7c047-ac42-49f9-a87a-27422ceac074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225563399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1225563399
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1259512796
Short name T421
Test name
Test status
Simulation time 6022389554 ps
CPU time 4.12 seconds
Started Apr 18 12:49:01 PM PDT 24
Finished Apr 18 12:49:06 PM PDT 24
Peak memory 202032 kb
Host smart-a2b5e4f9-c08a-4cc7-83d7-89b621271d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259512796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1259512796
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1158486405
Short name T310
Test name
Test status
Simulation time 342747128092 ps
CPU time 757.53 seconds
Started Apr 18 12:49:17 PM PDT 24
Finished Apr 18 01:01:56 PM PDT 24
Peak memory 202212 kb
Host smart-d7e668b4-3e1d-47f0-80c9-04869989524e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158486405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1158486405
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2788427486
Short name T782
Test name
Test status
Simulation time 230734805504 ps
CPU time 212.11 seconds
Started Apr 18 12:49:08 PM PDT 24
Finished Apr 18 12:52:41 PM PDT 24
Peak memory 210804 kb
Host smart-5c4bf69a-6576-48b1-82f3-649858873373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788427486 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2788427486
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3316981876
Short name T402
Test name
Test status
Simulation time 336701991 ps
CPU time 0.75 seconds
Started Apr 18 12:49:26 PM PDT 24
Finished Apr 18 12:49:27 PM PDT 24
Peak memory 201872 kb
Host smart-217d7b9d-ec60-40f8-80ab-90ff82a2fc11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316981876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3316981876
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3492801238
Short name T262
Test name
Test status
Simulation time 515014300718 ps
CPU time 435.39 seconds
Started Apr 18 12:49:17 PM PDT 24
Finished Apr 18 12:56:33 PM PDT 24
Peak memory 202324 kb
Host smart-6993fe82-3d67-43ea-8cd0-5aa02e379586
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492801238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3492801238
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.530726009
Short name T730
Test name
Test status
Simulation time 332665793752 ps
CPU time 201.6 seconds
Started Apr 18 12:49:18 PM PDT 24
Finished Apr 18 12:52:40 PM PDT 24
Peak memory 202292 kb
Host smart-91698763-657e-4eee-9af3-f73b46758bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530726009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.530726009
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4117357511
Short name T99
Test name
Test status
Simulation time 328544979709 ps
CPU time 754.86 seconds
Started Apr 18 12:49:23 PM PDT 24
Finished Apr 18 01:01:59 PM PDT 24
Peak memory 202204 kb
Host smart-698131cf-d1bf-46ba-b898-4329102efb31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117357511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4117357511
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.362267809
Short name T196
Test name
Test status
Simulation time 159017560579 ps
CPU time 344.39 seconds
Started Apr 18 12:49:20 PM PDT 24
Finished Apr 18 12:55:05 PM PDT 24
Peak memory 202248 kb
Host smart-64fa9b92-494b-4542-960a-429744637694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362267809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.362267809
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2627063028
Short name T586
Test name
Test status
Simulation time 493138659656 ps
CPU time 499.72 seconds
Started Apr 18 12:49:15 PM PDT 24
Finished Apr 18 12:57:36 PM PDT 24
Peak memory 202128 kb
Host smart-f67c93da-6b47-423c-901c-0fec0346a19c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627063028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2627063028
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2565950265
Short name T502
Test name
Test status
Simulation time 539988418500 ps
CPU time 1233.93 seconds
Started Apr 18 12:49:19 PM PDT 24
Finished Apr 18 01:09:54 PM PDT 24
Peak memory 202336 kb
Host smart-42eab125-5f1c-423c-b88d-0e3a84458079
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565950265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2565950265
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.702495905
Short name T170
Test name
Test status
Simulation time 398134662618 ps
CPU time 152.1 seconds
Started Apr 18 12:49:18 PM PDT 24
Finished Apr 18 12:51:51 PM PDT 24
Peak memory 202208 kb
Host smart-c7820e82-b071-4e47-9fe2-ed1aa464a180
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702495905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.702495905
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.989676124
Short name T377
Test name
Test status
Simulation time 98506930089 ps
CPU time 418.74 seconds
Started Apr 18 12:49:20 PM PDT 24
Finished Apr 18 12:56:20 PM PDT 24
Peak memory 202572 kb
Host smart-15cc2e41-807c-4943-a308-fbf4d6c2af10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989676124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.989676124
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2374182909
Short name T392
Test name
Test status
Simulation time 27928860393 ps
CPU time 11.05 seconds
Started Apr 18 12:49:26 PM PDT 24
Finished Apr 18 12:49:37 PM PDT 24
Peak memory 202104 kb
Host smart-e18e19fc-cf48-452d-93ad-107593a0daa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374182909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2374182909
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.8060972
Short name T562
Test name
Test status
Simulation time 5310915166 ps
CPU time 2.28 seconds
Started Apr 18 12:49:18 PM PDT 24
Finished Apr 18 12:49:21 PM PDT 24
Peak memory 202072 kb
Host smart-82ef155c-6a4c-4574-a66f-e9ea22356192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8060972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.8060972
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1741627749
Short name T698
Test name
Test status
Simulation time 5891273114 ps
CPU time 7.55 seconds
Started Apr 18 12:49:17 PM PDT 24
Finished Apr 18 12:49:25 PM PDT 24
Peak memory 202032 kb
Host smart-8f915f7a-3ce2-42b3-b2fb-28374b594cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741627749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1741627749
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1781637181
Short name T233
Test name
Test status
Simulation time 436242109101 ps
CPU time 1352.28 seconds
Started Apr 18 12:49:20 PM PDT 24
Finished Apr 18 01:11:53 PM PDT 24
Peak memory 210872 kb
Host smart-d22a86fd-0dde-46df-910d-b7b7f95a9542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781637181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1781637181
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1592470093
Short name T5
Test name
Test status
Simulation time 36464375910 ps
CPU time 41.87 seconds
Started Apr 18 12:49:21 PM PDT 24
Finished Apr 18 12:50:04 PM PDT 24
Peak memory 210548 kb
Host smart-c0078e52-5059-4397-a785-d32c115a97b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592470093 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1592470093
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2146624997
Short name T420
Test name
Test status
Simulation time 526318984 ps
CPU time 0.95 seconds
Started Apr 18 12:49:25 PM PDT 24
Finished Apr 18 12:49:27 PM PDT 24
Peak memory 201864 kb
Host smart-ed244042-9775-41c4-8437-2567a2b2e8c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146624997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2146624997
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2910264666
Short name T253
Test name
Test status
Simulation time 327436153143 ps
CPU time 199.48 seconds
Started Apr 18 12:49:19 PM PDT 24
Finished Apr 18 12:52:40 PM PDT 24
Peak memory 202156 kb
Host smart-244e83ed-37cb-432c-9fa5-96e807aae8a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910264666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2910264666
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3720559849
Short name T158
Test name
Test status
Simulation time 501201946434 ps
CPU time 285.49 seconds
Started Apr 18 12:49:29 PM PDT 24
Finished Apr 18 12:54:15 PM PDT 24
Peak memory 202252 kb
Host smart-af09ecb2-c103-4892-a760-1589e450e679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720559849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3720559849
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3465046862
Short name T249
Test name
Test status
Simulation time 495765504523 ps
CPU time 1215.15 seconds
Started Apr 18 12:49:20 PM PDT 24
Finished Apr 18 01:09:37 PM PDT 24
Peak memory 202240 kb
Host smart-0f10aff2-c934-44bc-a6f7-42cc00364809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465046862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3465046862
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2092534556
Short name T417
Test name
Test status
Simulation time 489825408535 ps
CPU time 555.7 seconds
Started Apr 18 12:49:21 PM PDT 24
Finished Apr 18 12:58:38 PM PDT 24
Peak memory 202116 kb
Host smart-afcb7ffe-754b-48be-baf3-f058d2e78be5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092534556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2092534556
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1771820987
Short name T254
Test name
Test status
Simulation time 496184102350 ps
CPU time 315.21 seconds
Started Apr 18 12:49:22 PM PDT 24
Finished Apr 18 12:54:38 PM PDT 24
Peak memory 202320 kb
Host smart-1479895c-11ad-4183-a828-449486bb68b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771820987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1771820987
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2475755689
Short name T723
Test name
Test status
Simulation time 496745664348 ps
CPU time 1195.62 seconds
Started Apr 18 12:49:19 PM PDT 24
Finished Apr 18 01:09:15 PM PDT 24
Peak memory 202212 kb
Host smart-06c7adbb-3ec6-4693-b32f-cc4280a7627a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475755689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2475755689
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2694883114
Short name T515
Test name
Test status
Simulation time 596524211135 ps
CPU time 741.19 seconds
Started Apr 18 12:49:20 PM PDT 24
Finished Apr 18 01:01:43 PM PDT 24
Peak memory 202160 kb
Host smart-9e464a95-c6d7-47cf-a90b-f490a2c8ed77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694883114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2694883114
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2343367072
Short name T47
Test name
Test status
Simulation time 199374361006 ps
CPU time 224.66 seconds
Started Apr 18 12:49:21 PM PDT 24
Finished Apr 18 12:53:06 PM PDT 24
Peak memory 202180 kb
Host smart-6a392654-d910-451b-91f9-d35cce0c5d56
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343367072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2343367072
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4130758685
Short name T236
Test name
Test status
Simulation time 87278013857 ps
CPU time 342.58 seconds
Started Apr 18 12:49:29 PM PDT 24
Finished Apr 18 12:55:12 PM PDT 24
Peak memory 202592 kb
Host smart-252e4440-fd47-426e-83e3-3f15559ba34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130758685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4130758685
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2307790937
Short name T611
Test name
Test status
Simulation time 45823138131 ps
CPU time 108.22 seconds
Started Apr 18 12:49:24 PM PDT 24
Finished Apr 18 12:51:12 PM PDT 24
Peak memory 201976 kb
Host smart-c5921cdd-df42-4d39-ab8b-36fec1ebd918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307790937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2307790937
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2272437979
Short name T490
Test name
Test status
Simulation time 3953634025 ps
CPU time 5.21 seconds
Started Apr 18 12:49:25 PM PDT 24
Finished Apr 18 12:49:30 PM PDT 24
Peak memory 202084 kb
Host smart-3f2bee52-8708-41cf-8fee-8386a7dd6c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272437979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2272437979
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2515014595
Short name T403
Test name
Test status
Simulation time 5774147159 ps
CPU time 14.31 seconds
Started Apr 18 12:49:19 PM PDT 24
Finished Apr 18 12:49:34 PM PDT 24
Peak memory 201988 kb
Host smart-dda1b1bc-fb1f-46dc-9f45-0de5081c514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515014595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2515014595
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3256951443
Short name T459
Test name
Test status
Simulation time 158578198584 ps
CPU time 120.83 seconds
Started Apr 18 12:49:25 PM PDT 24
Finished Apr 18 12:51:27 PM PDT 24
Peak memory 202260 kb
Host smart-36efc0c2-737f-4735-8f1b-bc85c0b99ef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256951443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3256951443
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2021721029
Short name T21
Test name
Test status
Simulation time 135860395183 ps
CPU time 299.57 seconds
Started Apr 18 12:49:24 PM PDT 24
Finished Apr 18 12:54:24 PM PDT 24
Peak memory 210924 kb
Host smart-78fc50e7-c99e-40cf-8c74-7503971089aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021721029 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2021721029
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2882380137
Short name T547
Test name
Test status
Simulation time 322762084 ps
CPU time 0.78 seconds
Started Apr 18 12:49:32 PM PDT 24
Finished Apr 18 12:49:34 PM PDT 24
Peak memory 201964 kb
Host smart-c3844795-9aad-4ead-9ed3-a1b2e1ac6ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882380137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2882380137
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4202015452
Short name T295
Test name
Test status
Simulation time 579049327593 ps
CPU time 1273.79 seconds
Started Apr 18 12:49:35 PM PDT 24
Finished Apr 18 01:10:49 PM PDT 24
Peak memory 202220 kb
Host smart-24ab9311-e34a-484d-b1aa-15aec354f22b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202015452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4202015452
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.94724564
Short name T307
Test name
Test status
Simulation time 520053773395 ps
CPU time 579.58 seconds
Started Apr 18 12:49:33 PM PDT 24
Finished Apr 18 12:59:13 PM PDT 24
Peak memory 202200 kb
Host smart-6d53f1f5-81c3-4dc2-9d00-7878e19465bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94724564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.94724564
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1835998303
Short name T221
Test name
Test status
Simulation time 498584482343 ps
CPU time 290.46 seconds
Started Apr 18 12:49:31 PM PDT 24
Finished Apr 18 12:54:22 PM PDT 24
Peak memory 202288 kb
Host smart-6a7a4d41-a627-471e-8ae0-b7fa3a92545c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835998303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1835998303
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4082281829
Short name T263
Test name
Test status
Simulation time 328500147483 ps
CPU time 351.85 seconds
Started Apr 18 12:49:26 PM PDT 24
Finished Apr 18 12:55:18 PM PDT 24
Peak memory 202240 kb
Host smart-6023d3dd-3c1c-4d85-9a03-87b5d13a8f04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082281829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.4082281829
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.4024447202
Short name T252
Test name
Test status
Simulation time 491711409164 ps
CPU time 274.16 seconds
Started Apr 18 12:49:29 PM PDT 24
Finished Apr 18 12:54:04 PM PDT 24
Peak memory 202324 kb
Host smart-60434b51-24c2-40fa-9b94-2ca1b5749575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024447202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.4024447202
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1189811644
Short name T451
Test name
Test status
Simulation time 166350727413 ps
CPU time 402.28 seconds
Started Apr 18 12:49:26 PM PDT 24
Finished Apr 18 12:56:09 PM PDT 24
Peak memory 202208 kb
Host smart-df3a8f68-f0e9-4897-8622-2f6fff37a14c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189811644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1189811644
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1223420094
Short name T527
Test name
Test status
Simulation time 358903306866 ps
CPU time 726.31 seconds
Started Apr 18 12:49:32 PM PDT 24
Finished Apr 18 01:01:39 PM PDT 24
Peak memory 202280 kb
Host smart-2f6ba4f1-1afd-49be-87ff-83079e5113c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223420094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1223420094
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1837850754
Short name T186
Test name
Test status
Simulation time 404043743917 ps
CPU time 129.99 seconds
Started Apr 18 12:49:32 PM PDT 24
Finished Apr 18 12:51:43 PM PDT 24
Peak memory 202228 kb
Host smart-2a849e90-d8d4-4dba-ab88-c5bff51d7180
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837850754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1837850754
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2759536376
Short name T687
Test name
Test status
Simulation time 120291598650 ps
CPU time 607.01 seconds
Started Apr 18 12:49:31 PM PDT 24
Finished Apr 18 12:59:39 PM PDT 24
Peak memory 202548 kb
Host smart-a806988e-91ce-473f-8ba9-6b431c08851c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759536376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2759536376
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2342306470
Short name T457
Test name
Test status
Simulation time 29134531004 ps
CPU time 48.99 seconds
Started Apr 18 12:49:33 PM PDT 24
Finished Apr 18 12:50:23 PM PDT 24
Peak memory 202028 kb
Host smart-3d5b240d-34e0-44d3-88c3-d23b8c536beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342306470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2342306470
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3217625564
Short name T412
Test name
Test status
Simulation time 5435376538 ps
CPU time 6.42 seconds
Started Apr 18 12:49:31 PM PDT 24
Finished Apr 18 12:49:38 PM PDT 24
Peak memory 202048 kb
Host smart-7a7cd67a-e067-401a-ad2d-0fcaf48ac305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217625564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3217625564
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1541489692
Short name T404
Test name
Test status
Simulation time 5815895837 ps
CPU time 8.15 seconds
Started Apr 18 12:49:25 PM PDT 24
Finished Apr 18 12:49:34 PM PDT 24
Peak memory 202068 kb
Host smart-e73cac1d-a418-47b2-81d3-1cb1634bae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541489692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1541489692
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.4034111859
Short name T606
Test name
Test status
Simulation time 218099515027 ps
CPU time 492.97 seconds
Started Apr 18 12:49:34 PM PDT 24
Finished Apr 18 12:57:48 PM PDT 24
Peak memory 202232 kb
Host smart-e26d9d52-53b0-4ad3-916c-eb35d4bdb631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034111859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.4034111859
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4285637274
Short name T43
Test name
Test status
Simulation time 169151400460 ps
CPU time 207.81 seconds
Started Apr 18 12:49:30 PM PDT 24
Finished Apr 18 12:52:58 PM PDT 24
Peak memory 211016 kb
Host smart-0490c647-7139-46b0-a6b0-735c31baefcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285637274 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4285637274
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.675275507
Short name T187
Test name
Test status
Simulation time 387765764 ps
CPU time 1.59 seconds
Started Apr 18 12:49:51 PM PDT 24
Finished Apr 18 12:49:54 PM PDT 24
Peak memory 201936 kb
Host smart-ff500083-4f03-49c0-9502-f0eafdc5f9d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675275507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.675275507
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1240038883
Short name T155
Test name
Test status
Simulation time 160897268239 ps
CPU time 82.73 seconds
Started Apr 18 12:49:37 PM PDT 24
Finished Apr 18 12:51:00 PM PDT 24
Peak memory 202248 kb
Host smart-2260a764-707e-4e49-8d15-2f29aba69f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240038883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1240038883
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.608919486
Short name T174
Test name
Test status
Simulation time 331972041689 ps
CPU time 425.37 seconds
Started Apr 18 12:49:38 PM PDT 24
Finished Apr 18 12:56:43 PM PDT 24
Peak memory 202096 kb
Host smart-db3c0741-5de5-4a24-a828-84340d55c4f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=608919486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.608919486
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.673703545
Short name T4
Test name
Test status
Simulation time 160706878323 ps
CPU time 83.21 seconds
Started Apr 18 12:49:32 PM PDT 24
Finished Apr 18 12:50:56 PM PDT 24
Peak memory 202236 kb
Host smart-a5511f57-9433-4183-9af6-c220244aab87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673703545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.673703545
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2957791599
Short name T574
Test name
Test status
Simulation time 160927534345 ps
CPU time 398.19 seconds
Started Apr 18 12:49:37 PM PDT 24
Finished Apr 18 12:56:15 PM PDT 24
Peak memory 202224 kb
Host smart-45196fcf-63f1-42d4-ab59-934c6114da5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957791599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2957791599
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3838673804
Short name T201
Test name
Test status
Simulation time 176463555278 ps
CPU time 100.82 seconds
Started Apr 18 12:49:39 PM PDT 24
Finished Apr 18 12:51:20 PM PDT 24
Peak memory 202208 kb
Host smart-376bceae-dc2a-4c34-ab48-5e72b5489424
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838673804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3838673804
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.517579842
Short name T475
Test name
Test status
Simulation time 407436607041 ps
CPU time 241.78 seconds
Started Apr 18 12:49:45 PM PDT 24
Finished Apr 18 12:53:47 PM PDT 24
Peak memory 202148 kb
Host smart-f67414c2-6132-4999-9b5e-e6f65325a6b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517579842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.517579842
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3772282015
Short name T237
Test name
Test status
Simulation time 95306171878 ps
CPU time 390.73 seconds
Started Apr 18 12:49:43 PM PDT 24
Finished Apr 18 12:56:15 PM PDT 24
Peak memory 202844 kb
Host smart-5b953f73-31b9-4813-a09c-7dd64d9de078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772282015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3772282015
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2942959715
Short name T477
Test name
Test status
Simulation time 32651713435 ps
CPU time 49.09 seconds
Started Apr 18 12:49:45 PM PDT 24
Finished Apr 18 12:50:34 PM PDT 24
Peak memory 201944 kb
Host smart-ab55f93b-784d-4b73-b261-1f3f8cd4ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942959715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2942959715
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1135405280
Short name T720
Test name
Test status
Simulation time 3732083576 ps
CPU time 8.63 seconds
Started Apr 18 12:49:43 PM PDT 24
Finished Apr 18 12:49:52 PM PDT 24
Peak memory 201972 kb
Host smart-a371c40d-335d-4291-a221-eaffa24107ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135405280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1135405280
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3688681436
Short name T690
Test name
Test status
Simulation time 6040681877 ps
CPU time 9.41 seconds
Started Apr 18 12:49:31 PM PDT 24
Finished Apr 18 12:49:40 PM PDT 24
Peak memory 202072 kb
Host smart-3035a714-49b5-4bbe-8b53-6437f0e93b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688681436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3688681436
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3110944643
Short name T243
Test name
Test status
Simulation time 282775008297 ps
CPU time 816.18 seconds
Started Apr 18 12:49:50 PM PDT 24
Finished Apr 18 01:03:27 PM PDT 24
Peak memory 210692 kb
Host smart-ad9fc910-cf61-4e83-9fc7-c0a98898513a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110944643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3110944643
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3934505399
Short name T210
Test name
Test status
Simulation time 372863434 ps
CPU time 0.82 seconds
Started Apr 18 12:50:09 PM PDT 24
Finished Apr 18 12:50:10 PM PDT 24
Peak memory 201932 kb
Host smart-4c37cdee-2550-49ef-8cb6-c68b6939201c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934505399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3934505399
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.4043875643
Short name T315
Test name
Test status
Simulation time 420938990440 ps
CPU time 963.6 seconds
Started Apr 18 12:49:55 PM PDT 24
Finished Apr 18 01:06:00 PM PDT 24
Peak memory 202248 kb
Host smart-3b079047-3035-48e9-a797-7ea6b13db510
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043875643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.4043875643
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3715292892
Short name T755
Test name
Test status
Simulation time 180730420739 ps
CPU time 153.3 seconds
Started Apr 18 12:49:53 PM PDT 24
Finished Apr 18 12:52:27 PM PDT 24
Peak memory 202132 kb
Host smart-c8859b10-1f3f-4058-aed1-730be908d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715292892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3715292892
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1497441929
Short name T181
Test name
Test status
Simulation time 498917392360 ps
CPU time 178.33 seconds
Started Apr 18 12:49:57 PM PDT 24
Finished Apr 18 12:52:56 PM PDT 24
Peak memory 202292 kb
Host smart-6fd0fa01-a6fe-48fc-b0cc-c71fc87cee89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497441929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1497441929
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2174177790
Short name T742
Test name
Test status
Simulation time 330859616291 ps
CPU time 747.7 seconds
Started Apr 18 12:49:53 PM PDT 24
Finished Apr 18 01:02:22 PM PDT 24
Peak memory 202100 kb
Host smart-396b1d20-54a0-487d-8d00-16072403ac5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174177790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2174177790
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.555461816
Short name T773
Test name
Test status
Simulation time 329575652449 ps
CPU time 193.16 seconds
Started Apr 18 12:49:50 PM PDT 24
Finished Apr 18 12:53:04 PM PDT 24
Peak memory 202188 kb
Host smart-5ebcd794-31df-43c6-af1b-57978a678112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555461816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.555461816
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2305500213
Short name T383
Test name
Test status
Simulation time 327979148167 ps
CPU time 706.6 seconds
Started Apr 18 12:49:54 PM PDT 24
Finished Apr 18 01:01:41 PM PDT 24
Peak memory 202208 kb
Host smart-63a0cbe9-27e9-4205-94ff-0f0057059282
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305500213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2305500213
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.4127168013
Short name T513
Test name
Test status
Simulation time 172748132795 ps
CPU time 423 seconds
Started Apr 18 12:49:55 PM PDT 24
Finished Apr 18 12:56:59 PM PDT 24
Peak memory 202276 kb
Host smart-94340cad-6164-4fd7-9c6c-225cf7b8b0c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127168013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.4127168013
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.724780438
Short name T194
Test name
Test status
Simulation time 590562374751 ps
CPU time 326.17 seconds
Started Apr 18 12:49:56 PM PDT 24
Finished Apr 18 12:55:24 PM PDT 24
Peak memory 202096 kb
Host smart-9eee6f75-e463-48aa-9f22-9caf2e2cd6a7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724780438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.724780438
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.4036192877
Short name T14
Test name
Test status
Simulation time 113150719553 ps
CPU time 461.92 seconds
Started Apr 18 12:50:00 PM PDT 24
Finished Apr 18 12:57:43 PM PDT 24
Peak memory 202604 kb
Host smart-e7640a8b-e0e0-45c7-b781-1d810f22bef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036192877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.4036192877
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.896514930
Short name T193
Test name
Test status
Simulation time 44849425208 ps
CPU time 94.86 seconds
Started Apr 18 12:50:01 PM PDT 24
Finished Apr 18 12:51:36 PM PDT 24
Peak memory 202016 kb
Host smart-6b6db377-8f98-4c08-83b2-7c0a52f9251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896514930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.896514930
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.972127182
Short name T1
Test name
Test status
Simulation time 2826835057 ps
CPU time 1.01 seconds
Started Apr 18 12:50:00 PM PDT 24
Finished Apr 18 12:50:02 PM PDT 24
Peak memory 202000 kb
Host smart-070be711-dc2d-4675-83bf-bfa360fe365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972127182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.972127182
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1909075267
Short name T537
Test name
Test status
Simulation time 5877283374 ps
CPU time 14.63 seconds
Started Apr 18 12:49:49 PM PDT 24
Finished Apr 18 12:50:04 PM PDT 24
Peak memory 202068 kb
Host smart-0f603be5-6114-4da3-96a1-169438e15055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909075267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1909075267
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3048556720
Short name T745
Test name
Test status
Simulation time 211143010166 ps
CPU time 514.8 seconds
Started Apr 18 12:50:01 PM PDT 24
Finished Apr 18 12:58:37 PM PDT 24
Peak memory 202332 kb
Host smart-69c73ad1-8a4c-4d29-9735-03db2a3a5bab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048556720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3048556720
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1038923876
Short name T22
Test name
Test status
Simulation time 23135071602 ps
CPU time 78.48 seconds
Started Apr 18 12:49:59 PM PDT 24
Finished Apr 18 12:51:18 PM PDT 24
Peak memory 210880 kb
Host smart-c9e8c876-1a36-440c-934f-18039ff6e031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038923876 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1038923876
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2594874447
Short name T503
Test name
Test status
Simulation time 491857025 ps
CPU time 1.68 seconds
Started Apr 18 12:50:13 PM PDT 24
Finished Apr 18 12:50:15 PM PDT 24
Peak memory 201964 kb
Host smart-8bfd3a4a-d191-46fe-a67f-c56fa89d58ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594874447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2594874447
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1025740015
Short name T520
Test name
Test status
Simulation time 349583801354 ps
CPU time 704.67 seconds
Started Apr 18 12:50:12 PM PDT 24
Finished Apr 18 01:01:57 PM PDT 24
Peak memory 202256 kb
Host smart-557bc04d-7367-48ed-bb01-3d49c25c4714
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025740015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1025740015
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3659725399
Short name T371
Test name
Test status
Simulation time 161028912614 ps
CPU time 345.74 seconds
Started Apr 18 12:50:05 PM PDT 24
Finished Apr 18 12:55:52 PM PDT 24
Peak memory 202236 kb
Host smart-5b51102e-4e7a-469e-8dd6-c91c39764cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659725399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3659725399
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3445106497
Short name T393
Test name
Test status
Simulation time 332885685946 ps
CPU time 757.67 seconds
Started Apr 18 12:50:06 PM PDT 24
Finished Apr 18 01:02:44 PM PDT 24
Peak memory 202144 kb
Host smart-afd18457-b45c-4ef9-8591-09c8a82be88a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445106497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3445106497
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.681029431
Short name T569
Test name
Test status
Simulation time 326569763793 ps
CPU time 578.23 seconds
Started Apr 18 12:50:06 PM PDT 24
Finished Apr 18 12:59:45 PM PDT 24
Peak memory 202324 kb
Host smart-8fb38c40-619f-4111-b832-ee2265a7941f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681029431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.681029431
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3486424206
Short name T577
Test name
Test status
Simulation time 162568212368 ps
CPU time 95.84 seconds
Started Apr 18 12:50:07 PM PDT 24
Finished Apr 18 12:51:43 PM PDT 24
Peak memory 202188 kb
Host smart-89c026c3-6def-4aec-82b9-7befb7746f69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486424206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3486424206
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2643974252
Short name T28
Test name
Test status
Simulation time 405364987832 ps
CPU time 363.31 seconds
Started Apr 18 12:50:10 PM PDT 24
Finished Apr 18 12:56:14 PM PDT 24
Peak memory 202200 kb
Host smart-90778622-1276-4297-8b76-4f2c63db2537
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643974252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2643974252
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.489828445
Short name T542
Test name
Test status
Simulation time 89941264842 ps
CPU time 513.09 seconds
Started Apr 18 12:50:13 PM PDT 24
Finished Apr 18 12:58:47 PM PDT 24
Peak memory 202432 kb
Host smart-0f77a49c-6bab-426c-94dc-14b948e7b853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489828445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.489828445
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2803446901
Short name T485
Test name
Test status
Simulation time 29612026177 ps
CPU time 66.15 seconds
Started Apr 18 12:50:13 PM PDT 24
Finished Apr 18 12:51:20 PM PDT 24
Peak memory 202080 kb
Host smart-0b7e608d-96b4-4180-810b-d1fe01451d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803446901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2803446901
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.253565380
Short name T670
Test name
Test status
Simulation time 4013037814 ps
CPU time 2.91 seconds
Started Apr 18 12:50:13 PM PDT 24
Finished Apr 18 12:50:17 PM PDT 24
Peak memory 202056 kb
Host smart-015f2a5c-d9ea-430e-8033-1a1493955f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253565380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.253565380
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1812442821
Short name T785
Test name
Test status
Simulation time 6210496358 ps
CPU time 2.51 seconds
Started Apr 18 12:50:07 PM PDT 24
Finished Apr 18 12:50:10 PM PDT 24
Peak memory 202032 kb
Host smart-50f7ab2e-5605-42ff-803c-03d329b4f10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812442821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1812442821
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.4098204114
Short name T583
Test name
Test status
Simulation time 170359202933 ps
CPU time 387.65 seconds
Started Apr 18 12:50:13 PM PDT 24
Finished Apr 18 12:56:42 PM PDT 24
Peak memory 202160 kb
Host smart-30292287-855f-47df-8ef8-f84e8f4069a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098204114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.4098204114
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1416731240
Short name T311
Test name
Test status
Simulation time 385396443074 ps
CPU time 69.3 seconds
Started Apr 18 12:50:12 PM PDT 24
Finished Apr 18 12:51:21 PM PDT 24
Peak memory 202392 kb
Host smart-1250bdba-bbbb-484f-89fd-d5e3510386fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416731240 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1416731240
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3436334280
Short name T416
Test name
Test status
Simulation time 413724840 ps
CPU time 1.08 seconds
Started Apr 18 12:50:28 PM PDT 24
Finished Apr 18 12:50:30 PM PDT 24
Peak memory 201972 kb
Host smart-7702d06d-ac4e-40c0-b808-46bbf900058d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436334280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3436334280
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1271220151
Short name T250
Test name
Test status
Simulation time 162078386020 ps
CPU time 171.52 seconds
Started Apr 18 12:50:22 PM PDT 24
Finished Apr 18 12:53:14 PM PDT 24
Peak memory 202236 kb
Host smart-5d51ba02-408c-4f26-9bf7-37d4a7e4829d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271220151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1271220151
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2291556474
Short name T105
Test name
Test status
Simulation time 166269106364 ps
CPU time 191.49 seconds
Started Apr 18 12:50:22 PM PDT 24
Finished Apr 18 12:53:34 PM PDT 24
Peak memory 202212 kb
Host smart-b0b25d3e-5ad8-4661-83fd-d27ca956d698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291556474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2291556474
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3985752867
Short name T327
Test name
Test status
Simulation time 488644774168 ps
CPU time 455.64 seconds
Started Apr 18 12:50:17 PM PDT 24
Finished Apr 18 12:57:53 PM PDT 24
Peak memory 202316 kb
Host smart-9d0b66f8-b731-407f-b280-b24c8062b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985752867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3985752867
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1817266677
Short name T389
Test name
Test status
Simulation time 165406132943 ps
CPU time 103.02 seconds
Started Apr 18 12:50:16 PM PDT 24
Finished Apr 18 12:52:00 PM PDT 24
Peak memory 202240 kb
Host smart-dbce2349-c6a3-4264-ab2b-53b2d0d92083
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817266677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1817266677
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3315937291
Short name T474
Test name
Test status
Simulation time 321762729359 ps
CPU time 352.27 seconds
Started Apr 18 12:50:14 PM PDT 24
Finished Apr 18 12:56:07 PM PDT 24
Peak memory 202236 kb
Host smart-c271cdc0-1432-4106-b07b-a9b5303abb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315937291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3315937291
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2855969487
Short name T734
Test name
Test status
Simulation time 490820308230 ps
CPU time 236.41 seconds
Started Apr 18 12:50:17 PM PDT 24
Finished Apr 18 12:54:14 PM PDT 24
Peak memory 202232 kb
Host smart-165c9d64-e178-4abb-81d4-62997a97157c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855969487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2855969487
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1008997233
Short name T593
Test name
Test status
Simulation time 360454652807 ps
CPU time 197.15 seconds
Started Apr 18 12:50:20 PM PDT 24
Finished Apr 18 12:53:38 PM PDT 24
Peak memory 202296 kb
Host smart-b5b7fc80-23c5-4e3c-9635-de22fff66326
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008997233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1008997233
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3343123960
Short name T454
Test name
Test status
Simulation time 210022649855 ps
CPU time 123.22 seconds
Started Apr 18 12:50:16 PM PDT 24
Finished Apr 18 12:52:20 PM PDT 24
Peak memory 202132 kb
Host smart-628b1386-0861-4d85-b95f-97372c912627
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343123960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3343123960
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.981031613
Short name T616
Test name
Test status
Simulation time 137958647543 ps
CPU time 684.84 seconds
Started Apr 18 12:50:21 PM PDT 24
Finished Apr 18 01:01:47 PM PDT 24
Peak memory 202544 kb
Host smart-66f0634b-6c53-497a-9c56-13faa9beee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981031613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.981031613
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1542704072
Short name T538
Test name
Test status
Simulation time 35155666229 ps
CPU time 20.72 seconds
Started Apr 18 12:50:21 PM PDT 24
Finished Apr 18 12:50:42 PM PDT 24
Peak memory 202080 kb
Host smart-beb24652-5cbb-4854-b216-afdd6ba80be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542704072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1542704072
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2370421686
Short name T387
Test name
Test status
Simulation time 5165632189 ps
CPU time 12.87 seconds
Started Apr 18 12:50:23 PM PDT 24
Finished Apr 18 12:50:37 PM PDT 24
Peak memory 201952 kb
Host smart-91682a84-4af2-4a81-bf12-535e117fdcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370421686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2370421686
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3600507805
Short name T134
Test name
Test status
Simulation time 6015413043 ps
CPU time 4.32 seconds
Started Apr 18 12:50:14 PM PDT 24
Finished Apr 18 12:50:19 PM PDT 24
Peak memory 202052 kb
Host smart-af3b7300-d3f0-42da-aae1-7c88f751eadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600507805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3600507805
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3827806879
Short name T787
Test name
Test status
Simulation time 15445397024 ps
CPU time 40.84 seconds
Started Apr 18 12:50:27 PM PDT 24
Finished Apr 18 12:51:09 PM PDT 24
Peak memory 202052 kb
Host smart-9c235f7a-c645-496f-8ec1-0f0eeb2db573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827806879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3827806879
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2899954862
Short name T627
Test name
Test status
Simulation time 402308070977 ps
CPU time 206.65 seconds
Started Apr 18 12:50:30 PM PDT 24
Finished Apr 18 12:53:57 PM PDT 24
Peak memory 210520 kb
Host smart-3b5bdef7-3a25-4be0-8590-7fdea7f77db6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899954862 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2899954862
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.772384644
Short name T748
Test name
Test status
Simulation time 472482311 ps
CPU time 1.51 seconds
Started Apr 18 12:50:42 PM PDT 24
Finished Apr 18 12:50:44 PM PDT 24
Peak memory 201908 kb
Host smart-87b85b30-4728-4b0e-bef5-f2c5426fe5e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772384644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.772384644
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.209718348
Short name T273
Test name
Test status
Simulation time 335372171860 ps
CPU time 215.6 seconds
Started Apr 18 12:50:37 PM PDT 24
Finished Apr 18 12:54:13 PM PDT 24
Peak memory 202272 kb
Host smart-d1441f9d-f4c7-40b2-8666-fa10cd004958
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209718348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.209718348
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3125762514
Short name T166
Test name
Test status
Simulation time 518334467189 ps
CPU time 1180.72 seconds
Started Apr 18 12:50:35 PM PDT 24
Finished Apr 18 01:10:17 PM PDT 24
Peak memory 202216 kb
Host smart-2bfaa47e-f4c4-4201-953e-2411a6866ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125762514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3125762514
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2045381388
Short name T93
Test name
Test status
Simulation time 165957203157 ps
CPU time 101.06 seconds
Started Apr 18 12:50:38 PM PDT 24
Finished Apr 18 12:52:20 PM PDT 24
Peak memory 202132 kb
Host smart-03c58ad1-4681-4eb3-803c-230e44bfc954
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045381388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2045381388
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3085967544
Short name T759
Test name
Test status
Simulation time 326157734248 ps
CPU time 728.99 seconds
Started Apr 18 12:50:29 PM PDT 24
Finished Apr 18 01:02:39 PM PDT 24
Peak memory 202168 kb
Host smart-6903a21e-81a6-48cb-b284-58d836ab8aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085967544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3085967544
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2390622169
Short name T523
Test name
Test status
Simulation time 166538652517 ps
CPU time 348.37 seconds
Started Apr 18 12:50:28 PM PDT 24
Finished Apr 18 12:56:17 PM PDT 24
Peak memory 202204 kb
Host smart-eced824b-8d9e-42c2-b917-68dd185b5a31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390622169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2390622169
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.374267976
Short name T318
Test name
Test status
Simulation time 182658525609 ps
CPU time 408.95 seconds
Started Apr 18 12:50:35 PM PDT 24
Finished Apr 18 12:57:25 PM PDT 24
Peak memory 202296 kb
Host smart-6a684af0-d4c0-4ebd-8d9f-3fa09e0f1353
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374267976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.374267976
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.650160346
Short name T727
Test name
Test status
Simulation time 585537269971 ps
CPU time 1329.1 seconds
Started Apr 18 12:50:34 PM PDT 24
Finished Apr 18 01:12:44 PM PDT 24
Peak memory 202144 kb
Host smart-f2885bb6-9a81-4948-b3d8-85d9b0855dfa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650160346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.650160346
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.303103024
Short name T613
Test name
Test status
Simulation time 114110524166 ps
CPU time 439.75 seconds
Started Apr 18 12:50:43 PM PDT 24
Finished Apr 18 12:58:04 PM PDT 24
Peak memory 202556 kb
Host smart-e4998246-ce7c-453d-8026-0316a48990d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303103024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.303103024
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.180527203
Short name T447
Test name
Test status
Simulation time 32776650355 ps
CPU time 18.61 seconds
Started Apr 18 12:50:42 PM PDT 24
Finished Apr 18 12:51:01 PM PDT 24
Peak memory 201968 kb
Host smart-fdb52ef5-6edb-4618-8bc0-935e4fa11fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180527203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.180527203
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3098956930
Short name T188
Test name
Test status
Simulation time 5063194620 ps
CPU time 12.66 seconds
Started Apr 18 12:50:36 PM PDT 24
Finished Apr 18 12:50:49 PM PDT 24
Peak memory 201920 kb
Host smart-ac310118-7b24-4893-8c55-ba0cd0529e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098956930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3098956930
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.311830817
Short name T688
Test name
Test status
Simulation time 6012123298 ps
CPU time 15.54 seconds
Started Apr 18 12:50:29 PM PDT 24
Finished Apr 18 12:50:45 PM PDT 24
Peak memory 201984 kb
Host smart-bb2eb036-222a-4618-8fc4-0507f1fd4c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311830817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.311830817
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3849331483
Short name T37
Test name
Test status
Simulation time 320655682502 ps
CPU time 1021.13 seconds
Started Apr 18 12:50:43 PM PDT 24
Finished Apr 18 01:07:45 PM PDT 24
Peak memory 210732 kb
Host smart-3f258cc3-d6d1-4381-a42c-435ed1364af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849331483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3849331483
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2839630511
Short name T15
Test name
Test status
Simulation time 420359316 ps
CPU time 1.47 seconds
Started Apr 18 12:50:54 PM PDT 24
Finished Apr 18 12:50:56 PM PDT 24
Peak memory 202168 kb
Host smart-a90fae74-2f64-49d2-8deb-b2ed9ffb9974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839630511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2839630511
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1801996042
Short name T160
Test name
Test status
Simulation time 366823305815 ps
CPU time 476.04 seconds
Started Apr 18 12:50:51 PM PDT 24
Finished Apr 18 12:58:47 PM PDT 24
Peak memory 202100 kb
Host smart-0cc36f9a-c563-4e15-b61b-1f19aa353607
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801996042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1801996042
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3954776154
Short name T287
Test name
Test status
Simulation time 162015159662 ps
CPU time 394.15 seconds
Started Apr 18 12:50:52 PM PDT 24
Finished Apr 18 12:57:27 PM PDT 24
Peak memory 202096 kb
Host smart-1469fb0a-188e-4a17-8b64-baac211f94a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954776154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3954776154
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3276274381
Short name T735
Test name
Test status
Simulation time 160130913237 ps
CPU time 123.04 seconds
Started Apr 18 12:50:52 PM PDT 24
Finished Apr 18 12:52:56 PM PDT 24
Peak memory 202124 kb
Host smart-f94d662f-ca38-4abe-b402-3a2970a3dd13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276274381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3276274381
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2395183661
Short name T693
Test name
Test status
Simulation time 324091173189 ps
CPU time 422.25 seconds
Started Apr 18 12:50:43 PM PDT 24
Finished Apr 18 12:57:46 PM PDT 24
Peak memory 202276 kb
Host smart-c2b7eec0-3b86-4e8c-a7bc-0f07669435a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395183661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2395183661
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1727805006
Short name T519
Test name
Test status
Simulation time 332486306890 ps
CPU time 168.37 seconds
Started Apr 18 12:50:44 PM PDT 24
Finished Apr 18 12:53:33 PM PDT 24
Peak memory 202224 kb
Host smart-33311943-269f-4212-8659-86d7f4256400
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727805006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1727805006
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3602756039
Short name T751
Test name
Test status
Simulation time 183938164533 ps
CPU time 77.75 seconds
Started Apr 18 12:50:48 PM PDT 24
Finished Apr 18 12:52:07 PM PDT 24
Peak memory 202116 kb
Host smart-246a530e-82cb-4d59-a46a-72a33cea1901
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602756039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3602756039
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3102968435
Short name T764
Test name
Test status
Simulation time 195569853778 ps
CPU time 465.61 seconds
Started Apr 18 12:50:47 PM PDT 24
Finished Apr 18 12:58:34 PM PDT 24
Peak memory 202120 kb
Host smart-d6d10d45-5e57-409a-b903-e980494f984e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102968435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3102968435
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.90344397
Short name T375
Test name
Test status
Simulation time 79082800309 ps
CPU time 245.19 seconds
Started Apr 18 12:50:52 PM PDT 24
Finished Apr 18 12:54:58 PM PDT 24
Peak memory 202460 kb
Host smart-744442de-f149-407f-82cc-8c5f5b34ed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90344397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.90344397
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1296101156
Short name T517
Test name
Test status
Simulation time 25850616639 ps
CPU time 14.46 seconds
Started Apr 18 12:50:47 PM PDT 24
Finished Apr 18 12:51:02 PM PDT 24
Peak memory 202028 kb
Host smart-d4cfd5f9-133d-49e5-8221-949d9b9b3d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296101156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1296101156
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1332133353
Short name T209
Test name
Test status
Simulation time 3431799782 ps
CPU time 1.42 seconds
Started Apr 18 12:50:47 PM PDT 24
Finished Apr 18 12:50:49 PM PDT 24
Peak memory 202024 kb
Host smart-6c348463-7026-4f3d-9407-bb01546add73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332133353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1332133353
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3189262850
Short name T398
Test name
Test status
Simulation time 5838723467 ps
CPU time 8.24 seconds
Started Apr 18 12:50:41 PM PDT 24
Finished Apr 18 12:50:50 PM PDT 24
Peak memory 202068 kb
Host smart-00455928-0fed-4ad0-8af0-5d3a1a222afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189262850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3189262850
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.854423273
Short name T660
Test name
Test status
Simulation time 1285330843 ps
CPU time 1.39 seconds
Started Apr 18 12:50:53 PM PDT 24
Finished Apr 18 12:50:55 PM PDT 24
Peak memory 201860 kb
Host smart-96b3e20f-7eed-4709-a08c-624bbb18e199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854423273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
854423273
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3123385601
Short name T316
Test name
Test status
Simulation time 11864099284 ps
CPU time 19.84 seconds
Started Apr 18 12:50:48 PM PDT 24
Finished Apr 18 12:51:09 PM PDT 24
Peak memory 202396 kb
Host smart-b1c4d255-15a2-45f7-ac6a-b66ddf882d6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123385601 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3123385601
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.719423018
Short name T505
Test name
Test status
Simulation time 407630631 ps
CPU time 0.86 seconds
Started Apr 18 12:47:06 PM PDT 24
Finished Apr 18 12:47:08 PM PDT 24
Peak memory 201884 kb
Host smart-1c8460bb-84b6-43c6-8858-62073a61bd3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719423018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.719423018
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.646600663
Short name T364
Test name
Test status
Simulation time 365844647003 ps
CPU time 437.76 seconds
Started Apr 18 12:47:16 PM PDT 24
Finished Apr 18 12:54:35 PM PDT 24
Peak memory 202280 kb
Host smart-08017541-43ca-4b8a-b1e0-257084afb29a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646600663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.646600663
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.366947013
Short name T291
Test name
Test status
Simulation time 548908901707 ps
CPU time 1124.2 seconds
Started Apr 18 12:47:06 PM PDT 24
Finished Apr 18 01:05:51 PM PDT 24
Peak memory 202232 kb
Host smart-dce4dec4-d109-4616-8702-9439f23d19bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366947013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.366947013
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2619721279
Short name T532
Test name
Test status
Simulation time 159571703642 ps
CPU time 366.9 seconds
Started Apr 18 12:47:07 PM PDT 24
Finished Apr 18 12:53:15 PM PDT 24
Peak memory 202240 kb
Host smart-6de8059c-4e8d-4d2e-b25d-2c09726dfc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619721279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2619721279
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3831666289
Short name T762
Test name
Test status
Simulation time 163430015154 ps
CPU time 179.71 seconds
Started Apr 18 12:47:12 PM PDT 24
Finished Apr 18 12:50:13 PM PDT 24
Peak memory 202196 kb
Host smart-c38cbfe6-2ff9-43cf-bd44-3284426e3147
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831666289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3831666289
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.11543628
Short name T293
Test name
Test status
Simulation time 329731189384 ps
CPU time 395.22 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:53:52 PM PDT 24
Peak memory 202240 kb
Host smart-5c612674-60ac-477e-89f8-aef65554e0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11543628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.11543628
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.912548624
Short name T654
Test name
Test status
Simulation time 165541553942 ps
CPU time 100.89 seconds
Started Apr 18 12:47:12 PM PDT 24
Finished Apr 18 12:48:54 PM PDT 24
Peak memory 202264 kb
Host smart-a1044cac-e2ba-47fd-99ad-43373c7da477
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=912548624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.912548624
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3309106571
Short name T591
Test name
Test status
Simulation time 668561418125 ps
CPU time 1561.18 seconds
Started Apr 18 12:47:16 PM PDT 24
Finished Apr 18 01:13:18 PM PDT 24
Peak memory 202252 kb
Host smart-0531ac3f-4117-4356-9f83-a741c52dfa1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309106571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3309106571
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3275551812
Short name T615
Test name
Test status
Simulation time 609724941492 ps
CPU time 218.57 seconds
Started Apr 18 12:47:06 PM PDT 24
Finished Apr 18 12:50:46 PM PDT 24
Peak memory 202232 kb
Host smart-4e2557bb-a449-4d42-b826-1dbb48ee3238
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275551812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3275551812
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3170731124
Short name T240
Test name
Test status
Simulation time 90894928795 ps
CPU time 371.34 seconds
Started Apr 18 12:47:07 PM PDT 24
Finished Apr 18 12:53:19 PM PDT 24
Peak memory 202568 kb
Host smart-7bdddedc-3915-42da-bf55-3e2ce32635c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170731124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3170731124
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2319471220
Short name T772
Test name
Test status
Simulation time 33472784303 ps
CPU time 38.98 seconds
Started Apr 18 12:47:06 PM PDT 24
Finished Apr 18 12:47:47 PM PDT 24
Peak memory 202056 kb
Host smart-37c35045-8433-425e-8b2b-9179dd03f605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319471220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2319471220
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3457841543
Short name T418
Test name
Test status
Simulation time 4777720291 ps
CPU time 12.02 seconds
Started Apr 18 12:47:05 PM PDT 24
Finished Apr 18 12:47:18 PM PDT 24
Peak memory 201992 kb
Host smart-94ad0c6a-0a8e-4ffa-a194-22a4847e9bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457841543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3457841543
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1469022638
Short name T65
Test name
Test status
Simulation time 7748139544 ps
CPU time 8.98 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:47:25 PM PDT 24
Peak memory 217816 kb
Host smart-b4ad7b8c-4c58-4b1c-ad25-5a03ed4a8b75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469022638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1469022638
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.989342691
Short name T136
Test name
Test status
Simulation time 5984443975 ps
CPU time 6.97 seconds
Started Apr 18 12:47:05 PM PDT 24
Finished Apr 18 12:47:13 PM PDT 24
Peak memory 201992 kb
Host smart-6164cbc5-46dc-44a1-9a92-70d91abff7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989342691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.989342691
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2040492033
Short name T775
Test name
Test status
Simulation time 28602742374 ps
CPU time 18.74 seconds
Started Apr 18 12:47:11 PM PDT 24
Finished Apr 18 12:47:31 PM PDT 24
Peak memory 210516 kb
Host smart-a8b5cce6-da75-4ff4-95c3-0498a5669bd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040492033 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2040492033
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1748350884
Short name T733
Test name
Test status
Simulation time 462364511 ps
CPU time 1.54 seconds
Started Apr 18 12:51:04 PM PDT 24
Finished Apr 18 12:51:07 PM PDT 24
Peak memory 201976 kb
Host smart-52cab871-6760-4085-94df-57ad2ebb16d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748350884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1748350884
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1109261395
Short name T361
Test name
Test status
Simulation time 164748060564 ps
CPU time 365.8 seconds
Started Apr 18 12:51:02 PM PDT 24
Finished Apr 18 12:57:09 PM PDT 24
Peak memory 202104 kb
Host smart-90bc4c55-a92a-4e79-9237-1a2b6a885515
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109261395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1109261395
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2032063285
Short name T587
Test name
Test status
Simulation time 329650139905 ps
CPU time 476.95 seconds
Started Apr 18 12:50:53 PM PDT 24
Finished Apr 18 12:58:51 PM PDT 24
Peak memory 202332 kb
Host smart-3ff48488-9605-4785-bbf1-e76cebf44626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032063285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2032063285
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.4292767268
Short name T686
Test name
Test status
Simulation time 163825608755 ps
CPU time 180.5 seconds
Started Apr 18 12:50:53 PM PDT 24
Finished Apr 18 12:53:54 PM PDT 24
Peak memory 202156 kb
Host smart-5e6fc936-4d52-4bc4-a1d6-04db40c92104
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292767268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.4292767268
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2166327840
Short name T558
Test name
Test status
Simulation time 329334126627 ps
CPU time 797.94 seconds
Started Apr 18 12:50:54 PM PDT 24
Finished Apr 18 01:04:13 PM PDT 24
Peak memory 202180 kb
Host smart-41578d10-9125-469b-a1b7-1af6a0cb25fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166327840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2166327840
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2614013795
Short name T694
Test name
Test status
Simulation time 476279200051 ps
CPU time 277.61 seconds
Started Apr 18 12:50:53 PM PDT 24
Finished Apr 18 12:55:32 PM PDT 24
Peak memory 202284 kb
Host smart-07b86b7d-8965-4df7-8d31-9d423d7f4ecd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614013795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2614013795
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2455562399
Short name T308
Test name
Test status
Simulation time 335085547308 ps
CPU time 702.06 seconds
Started Apr 18 12:51:02 PM PDT 24
Finished Apr 18 01:02:45 PM PDT 24
Peak memory 202304 kb
Host smart-451ba749-6d35-490c-b3b1-c2ba8d98cb23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455562399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2455562399
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3014394517
Short name T410
Test name
Test status
Simulation time 197655324573 ps
CPU time 462 seconds
Started Apr 18 12:50:58 PM PDT 24
Finished Apr 18 12:58:41 PM PDT 24
Peak memory 202192 kb
Host smart-eebda1f8-cd24-4b65-b92c-c0da8c1a321a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014394517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3014394517
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.539866516
Short name T244
Test name
Test status
Simulation time 127680412011 ps
CPU time 506.24 seconds
Started Apr 18 12:50:59 PM PDT 24
Finished Apr 18 12:59:26 PM PDT 24
Peak memory 202520 kb
Host smart-c9fc4fb9-8a48-4e76-b2ab-92474db592fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539866516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.539866516
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3074244006
Short name T707
Test name
Test status
Simulation time 29628453383 ps
CPU time 17.29 seconds
Started Apr 18 12:50:59 PM PDT 24
Finished Apr 18 12:51:16 PM PDT 24
Peak memory 201960 kb
Host smart-5e991e0a-35e6-44ec-a8e7-0b36452b44be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074244006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3074244006
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3715911258
Short name T462
Test name
Test status
Simulation time 2705782926 ps
CPU time 6.73 seconds
Started Apr 18 12:51:02 PM PDT 24
Finished Apr 18 12:51:10 PM PDT 24
Peak memory 202020 kb
Host smart-7fbeb112-9a23-4565-accd-52956c731b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715911258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3715911258
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1837219157
Short name T135
Test name
Test status
Simulation time 5919099712 ps
CPU time 3.14 seconds
Started Apr 18 12:50:54 PM PDT 24
Finished Apr 18 12:50:58 PM PDT 24
Peak memory 202016 kb
Host smart-24bb8103-fb92-4106-8d1e-1614fb800d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837219157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1837219157
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.838928278
Short name T23
Test name
Test status
Simulation time 80002581386 ps
CPU time 164.89 seconds
Started Apr 18 12:51:09 PM PDT 24
Finished Apr 18 12:53:54 PM PDT 24
Peak memory 210740 kb
Host smart-340b1032-fdbd-46f0-962c-ecb0306faeac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838928278 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.838928278
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.686862054
Short name T709
Test name
Test status
Simulation time 430884360 ps
CPU time 0.83 seconds
Started Apr 18 12:51:26 PM PDT 24
Finished Apr 18 12:51:27 PM PDT 24
Peak memory 201888 kb
Host smart-60387fdf-8ad0-4306-b4c3-68d1e6a825c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686862054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.686862054
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.798077510
Short name T667
Test name
Test status
Simulation time 365407401771 ps
CPU time 104.14 seconds
Started Apr 18 12:51:11 PM PDT 24
Finished Apr 18 12:52:57 PM PDT 24
Peak memory 202184 kb
Host smart-8f62ef3d-08d7-4b1b-908a-098939c8be6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798077510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.798077510
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.855919112
Short name T185
Test name
Test status
Simulation time 518010999162 ps
CPU time 245.81 seconds
Started Apr 18 12:51:10 PM PDT 24
Finished Apr 18 12:55:17 PM PDT 24
Peak memory 202228 kb
Host smart-bac4205d-0c62-4ce8-8901-685ecb04a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855919112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.855919112
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.945585794
Short name T296
Test name
Test status
Simulation time 483681803912 ps
CPU time 680.88 seconds
Started Apr 18 12:51:13 PM PDT 24
Finished Apr 18 01:02:35 PM PDT 24
Peak memory 201668 kb
Host smart-e648e950-8116-4e22-b935-a298afb8b091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945585794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.945585794
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1831031518
Short name T597
Test name
Test status
Simulation time 328764328424 ps
CPU time 201.64 seconds
Started Apr 18 12:51:11 PM PDT 24
Finished Apr 18 12:54:34 PM PDT 24
Peak memory 202144 kb
Host smart-2cacbb8c-40df-4637-a688-a605ceabe7eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831031518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1831031518
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3675690113
Short name T559
Test name
Test status
Simulation time 173527997589 ps
CPU time 395.6 seconds
Started Apr 18 12:51:06 PM PDT 24
Finished Apr 18 12:57:42 PM PDT 24
Peak memory 202144 kb
Host smart-d90cd4cd-ae81-4985-8c06-758cff1023b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675690113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3675690113
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1862662792
Short name T103
Test name
Test status
Simulation time 496896336858 ps
CPU time 1060.92 seconds
Started Apr 18 12:51:10 PM PDT 24
Finished Apr 18 01:08:53 PM PDT 24
Peak memory 202208 kb
Host smart-28226200-8c26-4554-97ec-66c0fa97eb40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862662792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1862662792
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2872685381
Short name T288
Test name
Test status
Simulation time 174122752035 ps
CPU time 56.84 seconds
Started Apr 18 12:51:13 PM PDT 24
Finished Apr 18 12:52:11 PM PDT 24
Peak memory 201596 kb
Host smart-70be5d93-a921-40af-9285-b7a12ac5fb36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872685381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2872685381
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1920051965
Short name T46
Test name
Test status
Simulation time 205542795901 ps
CPU time 475.18 seconds
Started Apr 18 12:51:11 PM PDT 24
Finished Apr 18 12:59:08 PM PDT 24
Peak memory 202048 kb
Host smart-acf1c076-090d-44d2-bb82-2108a20c6f75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920051965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1920051965
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.714704302
Short name T789
Test name
Test status
Simulation time 94303777877 ps
CPU time 329.91 seconds
Started Apr 18 12:51:13 PM PDT 24
Finished Apr 18 12:56:44 PM PDT 24
Peak memory 202548 kb
Host smart-904171f3-6edd-47c0-9a08-fb0aa21fedb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714704302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.714704302
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1624681269
Short name T624
Test name
Test status
Simulation time 41531326952 ps
CPU time 94.86 seconds
Started Apr 18 12:51:11 PM PDT 24
Finished Apr 18 12:52:47 PM PDT 24
Peak memory 201948 kb
Host smart-0cfeac0f-c85c-43f4-9193-2e893f49678d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624681269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1624681269
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2775158705
Short name T530
Test name
Test status
Simulation time 3251942657 ps
CPU time 2.22 seconds
Started Apr 18 12:51:11 PM PDT 24
Finished Apr 18 12:51:15 PM PDT 24
Peak memory 202020 kb
Host smart-185de8f1-7dc2-42ee-a1a3-b9e7e50eaafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775158705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2775158705
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.721706686
Short name T571
Test name
Test status
Simulation time 5872369100 ps
CPU time 4.25 seconds
Started Apr 18 12:51:09 PM PDT 24
Finished Apr 18 12:51:14 PM PDT 24
Peak memory 202072 kb
Host smart-afb299c0-8978-4c53-b6af-ab0b5d5fed57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721706686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.721706686
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2841870175
Short name T51
Test name
Test status
Simulation time 453050837969 ps
CPU time 598.77 seconds
Started Apr 18 12:51:16 PM PDT 24
Finished Apr 18 01:01:15 PM PDT 24
Peak memory 202400 kb
Host smart-850d47ba-6072-4e51-bbc0-cc37975630cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841870175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2841870175
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1976234180
Short name T541
Test name
Test status
Simulation time 81287756176 ps
CPU time 190.06 seconds
Started Apr 18 12:51:15 PM PDT 24
Finished Apr 18 12:54:26 PM PDT 24
Peak memory 210460 kb
Host smart-e2a73b2c-91ba-4df4-a399-9e1a6b7f3964
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976234180 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1976234180
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2980809068
Short name T701
Test name
Test status
Simulation time 341727958 ps
CPU time 1.35 seconds
Started Apr 18 12:51:22 PM PDT 24
Finished Apr 18 12:51:24 PM PDT 24
Peak memory 201988 kb
Host smart-ba4eee01-6932-4922-b3ee-2b7d45b0bb3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980809068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2980809068
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3498165712
Short name T679
Test name
Test status
Simulation time 492097950411 ps
CPU time 566.51 seconds
Started Apr 18 12:51:24 PM PDT 24
Finished Apr 18 01:00:51 PM PDT 24
Peak memory 202252 kb
Host smart-a71119f8-02de-46d7-b465-51c354302ebf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498165712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3498165712
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.183301723
Short name T354
Test name
Test status
Simulation time 533468923499 ps
CPU time 1238.62 seconds
Started Apr 18 12:51:23 PM PDT 24
Finished Apr 18 01:12:02 PM PDT 24
Peak memory 202148 kb
Host smart-a5060e78-cba1-4cd9-b18a-c497cf1f53bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183301723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.183301723
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.217957298
Short name T368
Test name
Test status
Simulation time 329704172388 ps
CPU time 757.43 seconds
Started Apr 18 12:51:24 PM PDT 24
Finished Apr 18 01:04:03 PM PDT 24
Peak memory 202156 kb
Host smart-5db60b85-c197-46da-baba-0c66617ea9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217957298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.217957298
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3278812253
Short name T435
Test name
Test status
Simulation time 158197941429 ps
CPU time 90.04 seconds
Started Apr 18 12:51:25 PM PDT 24
Finished Apr 18 12:52:56 PM PDT 24
Peak memory 202236 kb
Host smart-3d343664-73dc-4622-87b1-0e07579dcf05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278812253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3278812253
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.106532389
Short name T582
Test name
Test status
Simulation time 327313857781 ps
CPU time 196.52 seconds
Started Apr 18 12:51:22 PM PDT 24
Finished Apr 18 12:54:39 PM PDT 24
Peak memory 202304 kb
Host smart-d2053d92-cef1-481a-aa32-9a9ffc4f3c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106532389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.106532389
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2438717374
Short name T437
Test name
Test status
Simulation time 327451033407 ps
CPU time 750.99 seconds
Started Apr 18 12:51:26 PM PDT 24
Finished Apr 18 01:03:57 PM PDT 24
Peak memory 202124 kb
Host smart-270ba33e-dcae-4347-a5fe-4ce9fc198a40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438717374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2438717374
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3962252632
Short name T357
Test name
Test status
Simulation time 612739583249 ps
CPU time 1035.58 seconds
Started Apr 18 12:51:23 PM PDT 24
Finished Apr 18 01:08:39 PM PDT 24
Peak memory 202284 kb
Host smart-5f487443-93d6-41e8-8e1e-a644bde45dde
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962252632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3962252632
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.232206393
Short name T608
Test name
Test status
Simulation time 199240475078 ps
CPU time 440.81 seconds
Started Apr 18 12:51:24 PM PDT 24
Finished Apr 18 12:58:45 PM PDT 24
Peak memory 202156 kb
Host smart-7330ef4e-26d2-4cfe-8071-a03c9f1b1454
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232206393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.232206393
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2543445929
Short name T722
Test name
Test status
Simulation time 100025765355 ps
CPU time 524.75 seconds
Started Apr 18 12:51:24 PM PDT 24
Finished Apr 18 01:00:10 PM PDT 24
Peak memory 202480 kb
Host smart-7f8912a2-df41-4120-8b0a-ad34160a0792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543445929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2543445929
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2246766915
Short name T618
Test name
Test status
Simulation time 41146741769 ps
CPU time 25.99 seconds
Started Apr 18 12:51:24 PM PDT 24
Finished Apr 18 12:51:50 PM PDT 24
Peak memory 202088 kb
Host smart-e3288e30-31d5-4f47-845d-0d8fb903a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246766915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2246766915
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.4055027487
Short name T419
Test name
Test status
Simulation time 3034517154 ps
CPU time 2.41 seconds
Started Apr 18 12:51:23 PM PDT 24
Finished Apr 18 12:51:26 PM PDT 24
Peak memory 202048 kb
Host smart-a07c9601-d0fd-4d71-8ad4-97fb739f7d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055027487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4055027487
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3146149093
Short name T96
Test name
Test status
Simulation time 5938809356 ps
CPU time 13.8 seconds
Started Apr 18 12:51:24 PM PDT 24
Finished Apr 18 12:51:38 PM PDT 24
Peak memory 201948 kb
Host smart-977a560a-7878-4745-b6ab-9771fdd2215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146149093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3146149093
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3512209170
Short name T165
Test name
Test status
Simulation time 256828781844 ps
CPU time 821.11 seconds
Started Apr 18 12:51:24 PM PDT 24
Finished Apr 18 01:05:06 PM PDT 24
Peak memory 202576 kb
Host smart-ebec1b8c-1343-4339-aaed-2b20c773bb77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512209170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3512209170
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3835882878
Short name T378
Test name
Test status
Simulation time 129611270478 ps
CPU time 83.09 seconds
Started Apr 18 12:51:23 PM PDT 24
Finished Apr 18 12:52:47 PM PDT 24
Peak memory 210892 kb
Host smart-5f511648-be1b-46b8-b41b-fe34bde1c4e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835882878 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3835882878
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1529744468
Short name T466
Test name
Test status
Simulation time 429936080 ps
CPU time 0.75 seconds
Started Apr 18 12:51:35 PM PDT 24
Finished Apr 18 12:51:37 PM PDT 24
Peak memory 201864 kb
Host smart-9207134b-0f92-41e1-b86a-aaa6d453ad0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529744468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1529744468
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.101382602
Short name T34
Test name
Test status
Simulation time 173513583325 ps
CPU time 106.26 seconds
Started Apr 18 12:51:33 PM PDT 24
Finished Apr 18 12:53:21 PM PDT 24
Peak memory 202272 kb
Host smart-a4fefdfa-3061-4a06-bcfb-f955bcaba9a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101382602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.101382602
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2167786753
Short name T257
Test name
Test status
Simulation time 495479872472 ps
CPU time 261.28 seconds
Started Apr 18 12:51:35 PM PDT 24
Finished Apr 18 12:55:58 PM PDT 24
Peak memory 202244 kb
Host smart-c6cb55ed-36c9-48f1-892d-7a3fe44ae7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167786753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2167786753
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1267305167
Short name T448
Test name
Test status
Simulation time 330908347299 ps
CPU time 204.78 seconds
Started Apr 18 12:51:29 PM PDT 24
Finished Apr 18 12:54:54 PM PDT 24
Peak memory 202296 kb
Host smart-ae2cb238-cef5-41d1-9099-895905093486
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267305167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1267305167
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1247812424
Short name T648
Test name
Test status
Simulation time 490300036197 ps
CPU time 1174.17 seconds
Started Apr 18 12:51:29 PM PDT 24
Finished Apr 18 01:11:04 PM PDT 24
Peak memory 202160 kb
Host smart-d697f14e-56df-4f48-8701-61c9333bdcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247812424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1247812424
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2494131559
Short name T568
Test name
Test status
Simulation time 330189189161 ps
CPU time 41.17 seconds
Started Apr 18 12:51:29 PM PDT 24
Finished Apr 18 12:52:11 PM PDT 24
Peak memory 202156 kb
Host smart-b6c0903c-49cf-43b4-9ff5-39af6a73f741
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494131559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2494131559
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3472721685
Short name T272
Test name
Test status
Simulation time 564091470092 ps
CPU time 1206.11 seconds
Started Apr 18 12:51:28 PM PDT 24
Finished Apr 18 01:11:35 PM PDT 24
Peak memory 202256 kb
Host smart-318bb2e8-bec8-486e-9c4f-a792401e2359
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472721685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3472721685
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.4050752101
Short name T655
Test name
Test status
Simulation time 395655684537 ps
CPU time 886.29 seconds
Started Apr 18 12:51:34 PM PDT 24
Finished Apr 18 01:06:22 PM PDT 24
Peak memory 202240 kb
Host smart-c6c7743d-6d28-4baf-8600-019dc23fda69
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050752101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.4050752101
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.571463084
Short name T675
Test name
Test status
Simulation time 32428032455 ps
CPU time 19.92 seconds
Started Apr 18 12:51:33 PM PDT 24
Finished Apr 18 12:51:54 PM PDT 24
Peak memory 202004 kb
Host smart-59199479-1ca3-45b8-ba96-8988aecf4210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571463084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.571463084
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1198416134
Short name T553
Test name
Test status
Simulation time 3293421174 ps
CPU time 3.33 seconds
Started Apr 18 12:51:34 PM PDT 24
Finished Apr 18 12:51:38 PM PDT 24
Peak memory 202052 kb
Host smart-51221e28-7fa9-4462-8e27-a18deace4485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198416134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1198416134
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2177499571
Short name T610
Test name
Test status
Simulation time 5940416051 ps
CPU time 15.31 seconds
Started Apr 18 12:51:28 PM PDT 24
Finished Apr 18 12:51:44 PM PDT 24
Peak memory 201960 kb
Host smart-77cd3e72-97fb-4e3f-961d-c5301dee8d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177499571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2177499571
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3013707936
Short name T36
Test name
Test status
Simulation time 368163478817 ps
CPU time 230.32 seconds
Started Apr 18 12:51:34 PM PDT 24
Finished Apr 18 12:55:25 PM PDT 24
Peak memory 202464 kb
Host smart-d0a39f3a-b60f-4e95-996d-d7d4d4670be8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013707936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3013707936
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.960420069
Short name T246
Test name
Test status
Simulation time 3608477201497 ps
CPU time 509.56 seconds
Started Apr 18 12:51:32 PM PDT 24
Finished Apr 18 01:00:02 PM PDT 24
Peak memory 210876 kb
Host smart-07b22a92-ee86-43de-8edb-6add04d38a3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960420069 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.960420069
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1840232685
Short name T633
Test name
Test status
Simulation time 376369794 ps
CPU time 0.83 seconds
Started Apr 18 12:51:46 PM PDT 24
Finished Apr 18 12:51:48 PM PDT 24
Peak memory 201952 kb
Host smart-aff29d27-8cb1-4be5-b69d-947112770ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840232685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1840232685
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1412255739
Short name T761
Test name
Test status
Simulation time 495139737974 ps
CPU time 1121.71 seconds
Started Apr 18 12:51:40 PM PDT 24
Finished Apr 18 01:10:23 PM PDT 24
Peak memory 202132 kb
Host smart-ff6502d3-a2c3-42c4-b159-504dba51b11a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412255739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1412255739
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1337202143
Short name T614
Test name
Test status
Simulation time 489741212758 ps
CPU time 296.92 seconds
Started Apr 18 12:51:38 PM PDT 24
Finished Apr 18 12:56:36 PM PDT 24
Peak memory 202256 kb
Host smart-5b0ab391-d13b-4337-882c-fe5ef6912ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337202143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1337202143
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3692591008
Short name T585
Test name
Test status
Simulation time 167875983824 ps
CPU time 90.19 seconds
Started Apr 18 12:51:40 PM PDT 24
Finished Apr 18 12:53:11 PM PDT 24
Peak memory 202216 kb
Host smart-284b0038-864d-4d6e-a539-afcaf7eddb3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692591008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3692591008
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1042499369
Short name T192
Test name
Test status
Simulation time 295882805939 ps
CPU time 734.7 seconds
Started Apr 18 12:51:40 PM PDT 24
Finished Apr 18 01:03:55 PM PDT 24
Peak memory 202216 kb
Host smart-2b9645d8-a34d-4ac3-8a42-ce12b2a56278
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042499369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1042499369
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3523109190
Short name T575
Test name
Test status
Simulation time 199369974497 ps
CPU time 229.66 seconds
Started Apr 18 12:51:38 PM PDT 24
Finished Apr 18 12:55:29 PM PDT 24
Peak memory 202124 kb
Host smart-e7511a94-e68d-437b-8011-e007e878f555
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523109190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3523109190
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.897349192
Short name T605
Test name
Test status
Simulation time 111820991537 ps
CPU time 372.49 seconds
Started Apr 18 12:51:44 PM PDT 24
Finished Apr 18 12:57:57 PM PDT 24
Peak memory 202552 kb
Host smart-98104bab-dada-4a45-9dc2-ed50a8aea78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897349192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.897349192
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1533349702
Short name T636
Test name
Test status
Simulation time 44652035609 ps
CPU time 83.09 seconds
Started Apr 18 12:51:44 PM PDT 24
Finished Apr 18 12:53:08 PM PDT 24
Peak memory 202012 kb
Host smart-9a979cc8-db1c-4117-a3cb-f5eee78f8223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533349702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1533349702
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.911863421
Short name T607
Test name
Test status
Simulation time 4547822690 ps
CPU time 8.53 seconds
Started Apr 18 12:51:38 PM PDT 24
Finished Apr 18 12:51:47 PM PDT 24
Peak memory 202060 kb
Host smart-89a01f89-8fb8-41c3-b0d9-da2bdd859e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911863421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.911863421
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1497957150
Short name T549
Test name
Test status
Simulation time 5887066184 ps
CPU time 4.42 seconds
Started Apr 18 12:51:33 PM PDT 24
Finished Apr 18 12:51:39 PM PDT 24
Peak memory 201936 kb
Host smart-574b0aba-2438-48d5-b54d-42f67cd48cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497957150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1497957150
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.317595978
Short name T566
Test name
Test status
Simulation time 1132257265970 ps
CPU time 694.61 seconds
Started Apr 18 12:51:43 PM PDT 24
Finished Apr 18 01:03:19 PM PDT 24
Peak memory 212956 kb
Host smart-d9ed79d6-e104-4063-89cb-f7d1c17995d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317595978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
317595978
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.4016401673
Short name T524
Test name
Test status
Simulation time 102939473103 ps
CPU time 226.84 seconds
Started Apr 18 12:51:44 PM PDT 24
Finished Apr 18 12:55:32 PM PDT 24
Peak memory 211124 kb
Host smart-fec4a9ed-9232-4d28-a900-d0d2fa4a78f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016401673 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.4016401673
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1621013071
Short name T414
Test name
Test status
Simulation time 351770357 ps
CPU time 0.84 seconds
Started Apr 18 12:51:56 PM PDT 24
Finished Apr 18 12:51:57 PM PDT 24
Peak memory 201972 kb
Host smart-b886f006-034e-490d-ad69-8da081c0079d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621013071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1621013071
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.643650166
Short name T365
Test name
Test status
Simulation time 165765148151 ps
CPU time 352.88 seconds
Started Apr 18 12:51:50 PM PDT 24
Finished Apr 18 12:57:44 PM PDT 24
Peak memory 202160 kb
Host smart-ca75acf3-26f7-4918-aa5b-5d3c1684d455
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643650166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.643650166
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.953742001
Short name T159
Test name
Test status
Simulation time 372022775417 ps
CPU time 238.36 seconds
Started Apr 18 12:51:55 PM PDT 24
Finished Apr 18 12:55:54 PM PDT 24
Peak memory 202240 kb
Host smart-86c7a1fd-9ed2-4709-8fc3-752c082c6877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953742001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.953742001
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2659166107
Short name T31
Test name
Test status
Simulation time 163933503622 ps
CPU time 137.43 seconds
Started Apr 18 12:51:50 PM PDT 24
Finished Apr 18 12:54:08 PM PDT 24
Peak memory 202220 kb
Host smart-eb60c85a-cf62-4004-b034-142f001b5211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659166107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2659166107
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.667568063
Short name T625
Test name
Test status
Simulation time 322150103387 ps
CPU time 728.52 seconds
Started Apr 18 12:51:52 PM PDT 24
Finished Apr 18 01:04:01 PM PDT 24
Peak memory 202180 kb
Host smart-f2cb7d1d-2e03-44d5-90cc-ecce08e5f029
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=667568063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.667568063
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.690968923
Short name T482
Test name
Test status
Simulation time 164140803242 ps
CPU time 357.37 seconds
Started Apr 18 12:51:47 PM PDT 24
Finished Apr 18 12:57:45 PM PDT 24
Peak memory 202296 kb
Host smart-8d2f1c01-af85-462a-a5ad-e6ff93b6a820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690968923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.690968923
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.225572202
Short name T491
Test name
Test status
Simulation time 333582493092 ps
CPU time 767.43 seconds
Started Apr 18 12:51:51 PM PDT 24
Finished Apr 18 01:04:39 PM PDT 24
Peak memory 202112 kb
Host smart-52aa77d3-4028-4301-a789-aa4dc301864e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=225572202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.225572202
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2490235805
Short name T644
Test name
Test status
Simulation time 404056281959 ps
CPU time 781.81 seconds
Started Apr 18 12:51:54 PM PDT 24
Finished Apr 18 01:04:56 PM PDT 24
Peak memory 202136 kb
Host smart-e0945fa8-e556-4946-a52a-c1cd35adb95f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490235805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2490235805
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2564137745
Short name T531
Test name
Test status
Simulation time 135965376443 ps
CPU time 730.52 seconds
Started Apr 18 12:51:59 PM PDT 24
Finished Apr 18 01:04:10 PM PDT 24
Peak memory 202564 kb
Host smart-7f2b2bdb-cf85-4c3e-9e6c-1e0c1c686696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564137745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2564137745
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3627018898
Short name T739
Test name
Test status
Simulation time 46348997830 ps
CPU time 53.99 seconds
Started Apr 18 12:51:56 PM PDT 24
Finished Apr 18 12:52:51 PM PDT 24
Peak memory 202104 kb
Host smart-3d9cd1a7-8c4f-40d4-aebb-974e636f20c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627018898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3627018898
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3762238025
Short name T434
Test name
Test status
Simulation time 5396230813 ps
CPU time 12.74 seconds
Started Apr 18 12:51:57 PM PDT 24
Finished Apr 18 12:52:10 PM PDT 24
Peak memory 201896 kb
Host smart-46c93090-d3dd-46f5-92ee-ecc98de68871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762238025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3762238025
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1007458756
Short name T415
Test name
Test status
Simulation time 6042083938 ps
CPU time 3.71 seconds
Started Apr 18 12:51:45 PM PDT 24
Finished Apr 18 12:51:49 PM PDT 24
Peak memory 202052 kb
Host smart-083a9ee8-26e2-43da-9aab-31287b1d73ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007458756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1007458756
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1041094848
Short name T69
Test name
Test status
Simulation time 36685897667 ps
CPU time 39.87 seconds
Started Apr 18 12:51:59 PM PDT 24
Finished Apr 18 12:52:39 PM PDT 24
Peak memory 202056 kb
Host smart-bb42b826-ed34-45df-9a2b-1af728a55faa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041094848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1041094848
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1391673034
Short name T376
Test name
Test status
Simulation time 70129727787 ps
CPU time 61.66 seconds
Started Apr 18 12:51:58 PM PDT 24
Finished Apr 18 12:53:00 PM PDT 24
Peak memory 210780 kb
Host smart-77c2223c-801e-4051-b7cf-90f774440d07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391673034 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1391673034
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.775057055
Short name T594
Test name
Test status
Simulation time 383808334 ps
CPU time 0.76 seconds
Started Apr 18 12:52:09 PM PDT 24
Finished Apr 18 12:52:10 PM PDT 24
Peak memory 201864 kb
Host smart-6737c8a7-e942-4c3e-a05d-a70ab8a61fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775057055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.775057055
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.366627089
Short name T198
Test name
Test status
Simulation time 574672878670 ps
CPU time 87.85 seconds
Started Apr 18 12:52:03 PM PDT 24
Finished Apr 18 12:53:31 PM PDT 24
Peak memory 202172 kb
Host smart-001d7263-c7a4-4afa-b2aa-38ca1379ac00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366627089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.366627089
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3466810389
Short name T540
Test name
Test status
Simulation time 165703033480 ps
CPU time 103.92 seconds
Started Apr 18 12:52:02 PM PDT 24
Finished Apr 18 12:53:46 PM PDT 24
Peak memory 202336 kb
Host smart-fc64f4c0-ba8c-40f6-9da1-e1aa026f8f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466810389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3466810389
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2293628110
Short name T584
Test name
Test status
Simulation time 491784995938 ps
CPU time 1082.46 seconds
Started Apr 18 12:52:01 PM PDT 24
Finished Apr 18 01:10:04 PM PDT 24
Peak memory 202108 kb
Host smart-d2c487c6-16f4-461f-b7d2-692a235e82a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293628110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2293628110
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2722157731
Short name T97
Test name
Test status
Simulation time 493484874194 ps
CPU time 155.76 seconds
Started Apr 18 12:51:56 PM PDT 24
Finished Apr 18 12:54:33 PM PDT 24
Peak memory 202136 kb
Host smart-d07ad187-1284-45c3-a557-05eaceb03d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722157731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2722157731
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2959968407
Short name T774
Test name
Test status
Simulation time 329492816701 ps
CPU time 167.71 seconds
Started Apr 18 12:51:57 PM PDT 24
Finished Apr 18 12:54:45 PM PDT 24
Peak memory 202172 kb
Host smart-1f945aa0-b27f-4ebf-9e38-c4a177fba9ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959968407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2959968407
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.10952217
Short name T274
Test name
Test status
Simulation time 524834364311 ps
CPU time 1163.78 seconds
Started Apr 18 12:52:02 PM PDT 24
Finished Apr 18 01:11:27 PM PDT 24
Peak memory 202232 kb
Host smart-79d1288d-e2d7-4faf-8ba5-8abdbfcb7b9b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10952217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_w
akeup.10952217
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2626634017
Short name T8
Test name
Test status
Simulation time 199165533366 ps
CPU time 113.62 seconds
Started Apr 18 12:52:01 PM PDT 24
Finished Apr 18 12:53:56 PM PDT 24
Peak memory 202236 kb
Host smart-12dc50a0-015a-49b8-8eb6-93a97ec1f816
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626634017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2626634017
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1445335376
Short name T228
Test name
Test status
Simulation time 109645609865 ps
CPU time 416.86 seconds
Started Apr 18 12:52:09 PM PDT 24
Finished Apr 18 12:59:07 PM PDT 24
Peak memory 202560 kb
Host smart-ccebd35f-3a46-4c83-8a43-51fe96479ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445335376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1445335376
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.523730680
Short name T548
Test name
Test status
Simulation time 22386293644 ps
CPU time 11.35 seconds
Started Apr 18 12:52:01 PM PDT 24
Finished Apr 18 12:52:14 PM PDT 24
Peak memory 202056 kb
Host smart-dc39b1e6-db7f-4039-a184-be3f25a53150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523730680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.523730680
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1314722558
Short name T703
Test name
Test status
Simulation time 4387754877 ps
CPU time 10.27 seconds
Started Apr 18 12:52:01 PM PDT 24
Finished Apr 18 12:52:12 PM PDT 24
Peak memory 202068 kb
Host smart-acc5813f-1e79-41c8-b1e0-047620ba2b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314722558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1314722558
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1571734507
Short name T551
Test name
Test status
Simulation time 5947575427 ps
CPU time 3.96 seconds
Started Apr 18 12:51:56 PM PDT 24
Finished Apr 18 12:52:01 PM PDT 24
Peak memory 201972 kb
Host smart-1e2ad68c-f3bc-4610-afe7-e1ed677a1ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571734507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1571734507
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2062845165
Short name T463
Test name
Test status
Simulation time 56918944660 ps
CPU time 139.58 seconds
Started Apr 18 12:52:08 PM PDT 24
Finished Apr 18 12:54:29 PM PDT 24
Peak memory 202104 kb
Host smart-517cdf73-0cf4-4987-b823-8e25b426b1c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062845165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2062845165
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2938294426
Short name T533
Test name
Test status
Simulation time 314954212 ps
CPU time 0.94 seconds
Started Apr 18 12:52:26 PM PDT 24
Finished Apr 18 12:52:27 PM PDT 24
Peak memory 201840 kb
Host smart-5fd0d7c9-2f38-4d0d-8c73-fe84569e54ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938294426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2938294426
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.415346920
Short name T522
Test name
Test status
Simulation time 198414958315 ps
CPU time 163.58 seconds
Started Apr 18 12:52:15 PM PDT 24
Finished Apr 18 12:54:59 PM PDT 24
Peak memory 202256 kb
Host smart-c0299efe-a2b4-4e1f-9e26-fe3ca242e4ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415346920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.415346920
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1876632804
Short name T175
Test name
Test status
Simulation time 343838856779 ps
CPU time 207.24 seconds
Started Apr 18 12:52:15 PM PDT 24
Finished Apr 18 12:55:43 PM PDT 24
Peak memory 202228 kb
Host smart-920368f0-c823-4cf4-b99c-1772564a164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876632804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1876632804
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3862992508
Short name T301
Test name
Test status
Simulation time 495356423072 ps
CPU time 547.81 seconds
Started Apr 18 12:52:13 PM PDT 24
Finished Apr 18 01:01:22 PM PDT 24
Peak memory 202204 kb
Host smart-977ce0c8-77f0-4404-8267-7b4a0a33bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862992508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3862992508
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2639264629
Short name T217
Test name
Test status
Simulation time 332543820637 ps
CPU time 752.99 seconds
Started Apr 18 12:52:47 PM PDT 24
Finished Apr 18 01:05:20 PM PDT 24
Peak memory 202128 kb
Host smart-7b11764e-5edf-4eaf-8fbd-d6e02fdefdbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639264629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2639264629
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2376370818
Short name T325
Test name
Test status
Simulation time 159656574515 ps
CPU time 81.68 seconds
Started Apr 18 12:52:13 PM PDT 24
Finished Apr 18 12:53:36 PM PDT 24
Peak memory 202264 kb
Host smart-1d738449-2c84-4eef-a82e-7df56e12cd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376370818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2376370818
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2449396220
Short name T144
Test name
Test status
Simulation time 160424131058 ps
CPU time 22.32 seconds
Started Apr 18 12:52:15 PM PDT 24
Finished Apr 18 12:52:38 PM PDT 24
Peak memory 202140 kb
Host smart-badb3bba-5eb5-4fdc-9916-e226c363e4b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449396220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2449396220
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.812008746
Short name T346
Test name
Test status
Simulation time 365006194516 ps
CPU time 447.78 seconds
Started Apr 18 12:52:15 PM PDT 24
Finished Apr 18 12:59:43 PM PDT 24
Peak memory 201420 kb
Host smart-629be8fe-df62-4642-b847-7847f1ff9f6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812008746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.812008746
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2530004127
Short name T639
Test name
Test status
Simulation time 402040895623 ps
CPU time 252.83 seconds
Started Apr 18 12:52:14 PM PDT 24
Finished Apr 18 12:56:28 PM PDT 24
Peak memory 202200 kb
Host smart-34cba021-86c9-4464-acff-df2bdee2bc06
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530004127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2530004127
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2657043689
Short name T235
Test name
Test status
Simulation time 101402167565 ps
CPU time 526.04 seconds
Started Apr 18 12:52:19 PM PDT 24
Finished Apr 18 01:01:06 PM PDT 24
Peak memory 202516 kb
Host smart-1f69fbbe-ae22-4d13-b610-f30fbc66baac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657043689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2657043689
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1465198566
Short name T692
Test name
Test status
Simulation time 36928066708 ps
CPU time 79.17 seconds
Started Apr 18 12:52:19 PM PDT 24
Finished Apr 18 12:53:39 PM PDT 24
Peak memory 202000 kb
Host smart-9b176612-d00a-4872-ba88-1d4f13c78a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465198566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1465198566
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1660873676
Short name T52
Test name
Test status
Simulation time 3098133368 ps
CPU time 2.6 seconds
Started Apr 18 12:52:15 PM PDT 24
Finished Apr 18 12:52:19 PM PDT 24
Peak memory 201992 kb
Host smart-77c79db6-9293-4a22-88e2-1fb0d1f0e766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660873676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1660873676
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1966263124
Short name T637
Test name
Test status
Simulation time 6208832300 ps
CPU time 15.45 seconds
Started Apr 18 12:52:08 PM PDT 24
Finished Apr 18 12:52:24 PM PDT 24
Peak memory 202012 kb
Host smart-5a42761f-995b-43d7-96f2-c85e8b4ec9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966263124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1966263124
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2498330522
Short name T650
Test name
Test status
Simulation time 9716382644 ps
CPU time 9.16 seconds
Started Apr 18 12:52:19 PM PDT 24
Finished Apr 18 12:52:29 PM PDT 24
Peak memory 202052 kb
Host smart-b1bf67f9-5d8e-4885-aa36-9415ee1101f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498330522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2498330522
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2161880728
Short name T600
Test name
Test status
Simulation time 77487925526 ps
CPU time 92.74 seconds
Started Apr 18 12:52:18 PM PDT 24
Finished Apr 18 12:53:52 PM PDT 24
Peak memory 210524 kb
Host smart-c2c8a921-8260-4fb5-9863-f14260ecce0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161880728 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2161880728
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.731509015
Short name T70
Test name
Test status
Simulation time 521641950 ps
CPU time 1.69 seconds
Started Apr 18 12:52:37 PM PDT 24
Finished Apr 18 12:52:39 PM PDT 24
Peak memory 201996 kb
Host smart-db82688b-2cb8-40b9-8b0f-3a89b3babd9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731509015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.731509015
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.4138079090
Short name T286
Test name
Test status
Simulation time 540369204134 ps
CPU time 379.45 seconds
Started Apr 18 12:52:31 PM PDT 24
Finished Apr 18 12:58:51 PM PDT 24
Peak memory 202212 kb
Host smart-d1627ada-2697-48a3-9a0a-848fdaa8c798
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138079090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.4138079090
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.4123895979
Short name T337
Test name
Test status
Simulation time 190337858858 ps
CPU time 130.29 seconds
Started Apr 18 12:52:31 PM PDT 24
Finished Apr 18 12:54:41 PM PDT 24
Peak memory 202188 kb
Host smart-f4db7da8-de07-4d39-a625-37a4b8b7bd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123895979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.4123895979
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3210321536
Short name T309
Test name
Test status
Simulation time 486584063217 ps
CPU time 150.84 seconds
Started Apr 18 12:52:30 PM PDT 24
Finished Apr 18 12:55:01 PM PDT 24
Peak memory 202248 kb
Host smart-05127cd7-ad8c-48db-9ea6-6cfef47c2390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210321536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3210321536
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3135334952
Short name T711
Test name
Test status
Simulation time 325042889185 ps
CPU time 308.85 seconds
Started Apr 18 12:52:27 PM PDT 24
Finished Apr 18 12:57:37 PM PDT 24
Peak memory 202200 kb
Host smart-55d42041-7481-4c36-8c2c-f185f029267e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135334952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3135334952
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1492369244
Short name T336
Test name
Test status
Simulation time 332181427775 ps
CPU time 373.97 seconds
Started Apr 18 12:52:24 PM PDT 24
Finished Apr 18 12:58:39 PM PDT 24
Peak memory 202324 kb
Host smart-601f39a1-a8ef-4305-84cb-901075e69565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492369244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1492369244
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2791939303
Short name T427
Test name
Test status
Simulation time 324534426808 ps
CPU time 370.5 seconds
Started Apr 18 12:52:27 PM PDT 24
Finished Apr 18 12:58:38 PM PDT 24
Peak memory 202208 kb
Host smart-23342e0f-e54f-4b4a-adf2-7a9eac9b22da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791939303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2791939303
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.8186626
Short name T465
Test name
Test status
Simulation time 578909515750 ps
CPU time 594.17 seconds
Started Apr 18 12:52:30 PM PDT 24
Finished Apr 18 01:02:25 PM PDT 24
Peak memory 202200 kb
Host smart-1a64c676-aa22-4435-b1be-6fe25b9e2ab0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8186626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.ad
c_ctrl_filters_wakeup_fixed.8186626
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3887185096
Short name T767
Test name
Test status
Simulation time 79630562609 ps
CPU time 269.38 seconds
Started Apr 18 12:52:31 PM PDT 24
Finished Apr 18 12:57:01 PM PDT 24
Peak memory 202544 kb
Host smart-03e9a645-13e0-46bd-99e3-426f6ee09b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887185096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3887185096
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2738226224
Short name T461
Test name
Test status
Simulation time 42409739930 ps
CPU time 73.86 seconds
Started Apr 18 12:52:32 PM PDT 24
Finished Apr 18 12:53:46 PM PDT 24
Peak memory 202000 kb
Host smart-08c5a273-0334-4e48-9d78-bf83c7e3ea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738226224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2738226224
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1675719909
Short name T629
Test name
Test status
Simulation time 3051760561 ps
CPU time 7.25 seconds
Started Apr 18 12:52:29 PM PDT 24
Finished Apr 18 12:52:37 PM PDT 24
Peak memory 202012 kb
Host smart-3af70f22-4d4e-49e9-88e6-94024f2d4f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675719909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1675719909
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3431853713
Short name T689
Test name
Test status
Simulation time 5898312458 ps
CPU time 4.09 seconds
Started Apr 18 12:52:25 PM PDT 24
Finished Apr 18 12:52:30 PM PDT 24
Peak memory 202072 kb
Host smart-f4006a41-3cbd-4671-9bac-de7b02245458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431853713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3431853713
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2057042694
Short name T202
Test name
Test status
Simulation time 311650099470 ps
CPU time 470.25 seconds
Started Apr 18 12:52:33 PM PDT 24
Finished Apr 18 01:00:24 PM PDT 24
Peak memory 210644 kb
Host smart-ee1de189-93ac-4b2d-9f04-a76b105f32cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057042694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2057042694
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1069109758
Short name T456
Test name
Test status
Simulation time 375167982 ps
CPU time 1.35 seconds
Started Apr 18 12:52:49 PM PDT 24
Finished Apr 18 12:52:51 PM PDT 24
Peak memory 201888 kb
Host smart-36984be2-8a3a-4dbb-8d15-0064436488e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069109758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1069109758
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1157455154
Short name T157
Test name
Test status
Simulation time 197844591828 ps
CPU time 112.14 seconds
Started Apr 18 12:52:43 PM PDT 24
Finished Apr 18 12:54:36 PM PDT 24
Peak memory 202272 kb
Host smart-2cfb402f-d34c-4960-9736-1d1ce62f3b87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157455154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1157455154
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2987919217
Short name T177
Test name
Test status
Simulation time 179807032399 ps
CPU time 101.76 seconds
Started Apr 18 12:52:43 PM PDT 24
Finished Apr 18 12:54:25 PM PDT 24
Peak memory 202120 kb
Host smart-4d86625f-61a9-4d39-b98f-c05f5885fdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987919217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2987919217
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2530490619
Short name T470
Test name
Test status
Simulation time 491421639467 ps
CPU time 570.82 seconds
Started Apr 18 12:52:43 PM PDT 24
Finished Apr 18 01:02:14 PM PDT 24
Peak memory 202532 kb
Host smart-465813ad-978f-4763-b05e-4a80613e8090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530490619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2530490619
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3140367481
Short name T612
Test name
Test status
Simulation time 337905573237 ps
CPU time 816.44 seconds
Started Apr 18 12:52:42 PM PDT 24
Finished Apr 18 01:06:19 PM PDT 24
Peak memory 202240 kb
Host smart-9b45629b-65a5-4c3a-adca-7bb8a3bae51e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140367481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3140367481
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.346552652
Short name T673
Test name
Test status
Simulation time 160756341645 ps
CPU time 179.46 seconds
Started Apr 18 12:52:35 PM PDT 24
Finished Apr 18 12:55:35 PM PDT 24
Peak memory 202088 kb
Host smart-efd55818-5f92-4311-b4a3-77d25fc2d2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346552652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.346552652
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3560974024
Short name T595
Test name
Test status
Simulation time 164295419979 ps
CPU time 87.15 seconds
Started Apr 18 12:52:39 PM PDT 24
Finished Apr 18 12:54:07 PM PDT 24
Peak memory 202208 kb
Host smart-ff77a025-b226-4e3c-aeb2-7b95c9226be4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560974024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3560974024
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.191906337
Short name T622
Test name
Test status
Simulation time 373696446440 ps
CPU time 799.39 seconds
Started Apr 18 12:52:43 PM PDT 24
Finished Apr 18 01:06:03 PM PDT 24
Peak memory 202216 kb
Host smart-7da68556-57ec-4a32-b118-d68c7f3056e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191906337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.191906337
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.410367307
Short name T436
Test name
Test status
Simulation time 207449498417 ps
CPU time 484.69 seconds
Started Apr 18 12:52:45 PM PDT 24
Finished Apr 18 01:00:50 PM PDT 24
Peak memory 202136 kb
Host smart-4a3338ba-3865-43fb-9f19-d67dc6ae6cde
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410367307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.410367307
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4089051194
Short name T659
Test name
Test status
Simulation time 108083342554 ps
CPU time 359.4 seconds
Started Apr 18 12:52:42 PM PDT 24
Finished Apr 18 12:58:42 PM PDT 24
Peak memory 202648 kb
Host smart-22dd79a0-8dc4-43f5-b9f0-3c1329129f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089051194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4089051194
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3496935221
Short name T422
Test name
Test status
Simulation time 27465733011 ps
CPU time 65.22 seconds
Started Apr 18 12:52:43 PM PDT 24
Finished Apr 18 12:53:49 PM PDT 24
Peak memory 201980 kb
Host smart-a1b49179-77bf-4f65-8857-c3dd8fdcc58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496935221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3496935221
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2714831487
Short name T521
Test name
Test status
Simulation time 3751719042 ps
CPU time 2.66 seconds
Started Apr 18 12:52:45 PM PDT 24
Finished Apr 18 12:52:48 PM PDT 24
Peak memory 202000 kb
Host smart-89b54bf4-9e83-4f45-9c22-1ed8c7ab8f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714831487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2714831487
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4260925423
Short name T697
Test name
Test status
Simulation time 5813436998 ps
CPU time 13.81 seconds
Started Apr 18 12:52:36 PM PDT 24
Finished Apr 18 12:52:51 PM PDT 24
Peak memory 201988 kb
Host smart-e8bfae02-66f3-4c0e-bc4c-6c09bbcab1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260925423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4260925423
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1760586405
Short name T603
Test name
Test status
Simulation time 308001987449 ps
CPU time 797.55 seconds
Started Apr 18 12:52:44 PM PDT 24
Finished Apr 18 01:06:03 PM PDT 24
Peak memory 210720 kb
Host smart-ea3987f5-a605-4dd9-8a8a-912dc2e4f12c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760586405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1760586405
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3120034174
Short name T431
Test name
Test status
Simulation time 486545660 ps
CPU time 1.02 seconds
Started Apr 18 12:47:06 PM PDT 24
Finished Apr 18 12:47:09 PM PDT 24
Peak memory 202172 kb
Host smart-4c14bd03-a196-4c8e-8e7f-b2a037d309a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120034174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3120034174
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3217082231
Short name T682
Test name
Test status
Simulation time 176925356743 ps
CPU time 113.35 seconds
Started Apr 18 12:47:11 PM PDT 24
Finished Apr 18 12:49:05 PM PDT 24
Peak memory 202108 kb
Host smart-d7b8c701-17ce-4e2b-bc5a-6800050d3a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217082231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3217082231
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2623306358
Short name T206
Test name
Test status
Simulation time 324277935526 ps
CPU time 353.34 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:53:10 PM PDT 24
Peak memory 202204 kb
Host smart-69c514fe-819c-4426-982b-7e54cf812362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623306358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2623306358
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.286639411
Short name T111
Test name
Test status
Simulation time 491666676739 ps
CPU time 1036.13 seconds
Started Apr 18 12:47:12 PM PDT 24
Finished Apr 18 01:04:29 PM PDT 24
Peak memory 202276 kb
Host smart-fd88e934-62c5-4526-bd04-3c89ffc002b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=286639411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt
_fixed.286639411
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3508132829
Short name T197
Test name
Test status
Simulation time 502165794665 ps
CPU time 293.43 seconds
Started Apr 18 12:47:05 PM PDT 24
Finished Apr 18 12:51:59 PM PDT 24
Peak memory 202272 kb
Host smart-6e3ffbc8-3a0f-422f-a58a-2bc867c5e708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508132829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3508132829
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1152233661
Short name T176
Test name
Test status
Simulation time 330736072926 ps
CPU time 168.71 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:50:06 PM PDT 24
Peak memory 202196 kb
Host smart-f5374165-b5cf-42ff-ac7d-1b725f44db49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152233661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1152233661
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2530229016
Short name T642
Test name
Test status
Simulation time 199260878260 ps
CPU time 120.65 seconds
Started Apr 18 12:47:19 PM PDT 24
Finished Apr 18 12:49:21 PM PDT 24
Peak memory 202324 kb
Host smart-4f10fc02-2371-4208-9e3a-d3071bda0b7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530229016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2530229016
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1862071231
Short name T76
Test name
Test status
Simulation time 411005699804 ps
CPU time 945.14 seconds
Started Apr 18 12:47:09 PM PDT 24
Finished Apr 18 01:02:55 PM PDT 24
Peak memory 202148 kb
Host smart-92f7a854-9921-46a2-b2f0-01fb23360617
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862071231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1862071231
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2068153063
Short name T760
Test name
Test status
Simulation time 96365580334 ps
CPU time 347.37 seconds
Started Apr 18 12:47:10 PM PDT 24
Finished Apr 18 12:52:58 PM PDT 24
Peak memory 202608 kb
Host smart-49259a39-1c0e-4446-ae1b-67fac28452b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068153063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2068153063
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2633644341
Short name T384
Test name
Test status
Simulation time 44086429880 ps
CPU time 19.11 seconds
Started Apr 18 12:47:19 PM PDT 24
Finished Apr 18 12:47:39 PM PDT 24
Peak memory 202048 kb
Host smart-02f426bf-97bc-4316-ad21-0f3f6bd171d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633644341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2633644341
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2346703822
Short name T469
Test name
Test status
Simulation time 3318953495 ps
CPU time 8.13 seconds
Started Apr 18 12:47:14 PM PDT 24
Finished Apr 18 12:47:23 PM PDT 24
Peak memory 202052 kb
Host smart-b85339e5-e7a2-4fa0-91ea-346b8ba8eac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346703822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2346703822
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3790055806
Short name T746
Test name
Test status
Simulation time 5642310750 ps
CPU time 14.39 seconds
Started Apr 18 12:47:13 PM PDT 24
Finished Apr 18 12:47:29 PM PDT 24
Peak memory 201964 kb
Host smart-e673596d-e4a0-4c02-9eaf-d7deb22091a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790055806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3790055806
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3018566496
Short name T321
Test name
Test status
Simulation time 525675170118 ps
CPU time 1161.66 seconds
Started Apr 18 12:47:19 PM PDT 24
Finished Apr 18 01:06:42 PM PDT 24
Peak memory 202292 kb
Host smart-0a65a2d3-bafc-4d67-b86a-17692bc0b475
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018566496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3018566496
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2039383591
Short name T567
Test name
Test status
Simulation time 392550604488 ps
CPU time 255.64 seconds
Started Apr 18 12:47:07 PM PDT 24
Finished Apr 18 12:51:24 PM PDT 24
Peak memory 210768 kb
Host smart-ee443867-d6be-4ffe-8cbc-7a19dbddbf77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039383591 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2039383591
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2593204111
Short name T790
Test name
Test status
Simulation time 383256448 ps
CPU time 1.03 seconds
Started Apr 18 12:47:12 PM PDT 24
Finished Apr 18 12:47:14 PM PDT 24
Peak memory 201920 kb
Host smart-c6d60b94-a870-4a83-bb96-aab226ffdf83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593204111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2593204111
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3572211287
Short name T29
Test name
Test status
Simulation time 164301373118 ps
CPU time 67.43 seconds
Started Apr 18 12:47:07 PM PDT 24
Finished Apr 18 12:48:16 PM PDT 24
Peak memory 202348 kb
Host smart-df3e807c-75ea-4590-b704-c1d415a40554
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572211287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3572211287
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1757567411
Short name T363
Test name
Test status
Simulation time 493580184279 ps
CPU time 1105.66 seconds
Started Apr 18 12:47:14 PM PDT 24
Finished Apr 18 01:05:41 PM PDT 24
Peak memory 202224 kb
Host smart-7d0d1575-66d1-4085-9846-660475488d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757567411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1757567411
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2368340744
Short name T91
Test name
Test status
Simulation time 483938452166 ps
CPU time 122.47 seconds
Started Apr 18 12:47:08 PM PDT 24
Finished Apr 18 12:49:11 PM PDT 24
Peak memory 202176 kb
Host smart-dd2ed3e1-1927-424c-b4f8-2a63f94e8218
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368340744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2368340744
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3756721945
Short name T140
Test name
Test status
Simulation time 333305252064 ps
CPU time 768.54 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 01:00:05 PM PDT 24
Peak memory 202328 kb
Host smart-13667d7b-e815-43e4-a1b0-69044d7b96f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756721945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3756721945
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3774471773
Short name T539
Test name
Test status
Simulation time 160606419122 ps
CPU time 192.4 seconds
Started Apr 18 12:47:13 PM PDT 24
Finished Apr 18 12:50:26 PM PDT 24
Peak memory 201476 kb
Host smart-f6a92875-a50a-4445-86d3-b15fab350fc6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774471773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3774471773
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2199807174
Short name T204
Test name
Test status
Simulation time 565349789012 ps
CPU time 641.83 seconds
Started Apr 18 12:47:11 PM PDT 24
Finished Apr 18 12:57:53 PM PDT 24
Peak memory 202220 kb
Host smart-233a2f2f-74a4-4a41-86df-f89d9944ad8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199807174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2199807174
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4151028691
Short name T504
Test name
Test status
Simulation time 412131426385 ps
CPU time 994.64 seconds
Started Apr 18 12:47:07 PM PDT 24
Finished Apr 18 01:03:43 PM PDT 24
Peak memory 202212 kb
Host smart-2131f7bf-3416-4a8e-a267-4a3f7af79665
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151028691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4151028691
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2250211617
Short name T708
Test name
Test status
Simulation time 98074042677 ps
CPU time 370.8 seconds
Started Apr 18 12:47:06 PM PDT 24
Finished Apr 18 12:53:18 PM PDT 24
Peak memory 202556 kb
Host smart-1c5012e0-634c-47fb-a8e6-264f97362382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250211617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2250211617
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3786195776
Short name T405
Test name
Test status
Simulation time 25912286032 ps
CPU time 29.35 seconds
Started Apr 18 12:47:05 PM PDT 24
Finished Apr 18 12:47:35 PM PDT 24
Peak memory 201936 kb
Host smart-f898a63e-53bd-49b1-8ac4-1d34854d17d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786195776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3786195776
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2313744098
Short name T83
Test name
Test status
Simulation time 5501172168 ps
CPU time 15.14 seconds
Started Apr 18 12:47:07 PM PDT 24
Finished Apr 18 12:47:23 PM PDT 24
Peak memory 202024 kb
Host smart-65bd04e1-e8c2-4400-b4bb-9abae5fd9e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313744098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2313744098
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3807086175
Short name T564
Test name
Test status
Simulation time 5603786983 ps
CPU time 2.24 seconds
Started Apr 18 12:47:14 PM PDT 24
Finished Apr 18 12:47:17 PM PDT 24
Peak memory 202072 kb
Host smart-9cfed99b-f2f2-4b02-a764-5234f9e86b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807086175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3807086175
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1100833697
Short name T747
Test name
Test status
Simulation time 138237703119 ps
CPU time 302.41 seconds
Started Apr 18 12:47:07 PM PDT 24
Finished Apr 18 12:52:10 PM PDT 24
Peak memory 213216 kb
Host smart-720002b7-74b0-4566-8e1a-b252a26b1e08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100833697 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1100833697
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.103807995
Short name T391
Test name
Test status
Simulation time 348729263 ps
CPU time 0.99 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:47:19 PM PDT 24
Peak memory 201944 kb
Host smart-80e5ab0e-ce2f-4fa0-9d75-bb01cd8dd311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103807995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.103807995
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.336279406
Short name T260
Test name
Test status
Simulation time 320055689030 ps
CPU time 101.56 seconds
Started Apr 18 12:47:14 PM PDT 24
Finished Apr 18 12:48:56 PM PDT 24
Peak memory 202296 kb
Host smart-7989a45a-1e28-4ed4-b26e-64af666309d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336279406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.336279406
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3432341284
Short name T172
Test name
Test status
Simulation time 178285832307 ps
CPU time 91.86 seconds
Started Apr 18 12:47:19 PM PDT 24
Finished Apr 18 12:48:52 PM PDT 24
Peak memory 202236 kb
Host smart-6a403569-1e8d-4984-b19e-79c0b2edc8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432341284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3432341284
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3950863539
Short name T282
Test name
Test status
Simulation time 494495742719 ps
CPU time 319.12 seconds
Started Apr 18 12:47:07 PM PDT 24
Finished Apr 18 12:52:27 PM PDT 24
Peak memory 202284 kb
Host smart-bf2d675d-743f-4a40-bb01-5a090acf6526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950863539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3950863539
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3147614553
Short name T609
Test name
Test status
Simulation time 324350979189 ps
CPU time 163.85 seconds
Started Apr 18 12:47:12 PM PDT 24
Finished Apr 18 12:49:57 PM PDT 24
Peak memory 202200 kb
Host smart-47918bed-76dc-41c2-be91-0e00d63e473d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147614553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3147614553
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3557799139
Short name T251
Test name
Test status
Simulation time 332629348069 ps
CPU time 787.61 seconds
Started Apr 18 12:47:11 PM PDT 24
Finished Apr 18 01:00:20 PM PDT 24
Peak memory 202096 kb
Host smart-45bdd2d6-ea33-484c-b3cf-28bd2b8ac501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557799139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3557799139
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2628710176
Short name T592
Test name
Test status
Simulation time 165144618056 ps
CPU time 99.58 seconds
Started Apr 18 12:47:13 PM PDT 24
Finished Apr 18 12:48:54 PM PDT 24
Peak memory 202272 kb
Host smart-567e3de7-9cf5-4b66-b27c-d761567cd379
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628710176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2628710176
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1169816742
Short name T276
Test name
Test status
Simulation time 177868355121 ps
CPU time 425.53 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:54:22 PM PDT 24
Peak memory 202456 kb
Host smart-d6c1b232-ab51-4cd0-b899-d272cb5f03e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169816742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1169816742
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.254778789
Short name T385
Test name
Test status
Simulation time 398980763486 ps
CPU time 966.4 seconds
Started Apr 18 12:47:16 PM PDT 24
Finished Apr 18 01:03:28 PM PDT 24
Peak memory 202236 kb
Host smart-d63796b7-0c51-46fb-9c80-4e528f1b98af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254778789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.254778789
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3218724763
Short name T226
Test name
Test status
Simulation time 116764610691 ps
CPU time 465.56 seconds
Started Apr 18 12:47:19 PM PDT 24
Finished Apr 18 12:55:06 PM PDT 24
Peak memory 202452 kb
Host smart-11b937ef-f463-456d-8dfb-5f66b225b659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218724763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3218724763
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.979338073
Short name T211
Test name
Test status
Simulation time 37140335363 ps
CPU time 23.1 seconds
Started Apr 18 12:47:16 PM PDT 24
Finished Apr 18 12:47:41 PM PDT 24
Peak memory 202060 kb
Host smart-e79bbb39-c836-46d7-9dee-e15596dfe438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979338073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.979338073
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3378662501
Short name T750
Test name
Test status
Simulation time 4949467964 ps
CPU time 5.09 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:47:24 PM PDT 24
Peak memory 202064 kb
Host smart-51a70305-13a8-4f1f-9af2-b357bd936b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378662501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3378662501
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.201702319
Short name T26
Test name
Test status
Simulation time 5642283939 ps
CPU time 6.62 seconds
Started Apr 18 12:47:09 PM PDT 24
Finished Apr 18 12:47:16 PM PDT 24
Peak memory 202072 kb
Host smart-cd5b352d-9aab-4835-826f-550f3f01f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201702319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.201702319
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1114371563
Short name T680
Test name
Test status
Simulation time 419913540689 ps
CPU time 1008.4 seconds
Started Apr 18 12:47:19 PM PDT 24
Finished Apr 18 01:04:09 PM PDT 24
Peak memory 202324 kb
Host smart-de3ed826-8955-4b3d-a01c-6527f15a8234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114371563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1114371563
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3815043797
Short name T41
Test name
Test status
Simulation time 79212292177 ps
CPU time 244.31 seconds
Started Apr 18 12:47:16 PM PDT 24
Finished Apr 18 12:51:22 PM PDT 24
Peak memory 211828 kb
Host smart-e20e6f96-4ee4-4949-bf5e-ebbba8404af8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815043797 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3815043797
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3397516702
Short name T763
Test name
Test status
Simulation time 577875475 ps
CPU time 0.69 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:47:20 PM PDT 24
Peak memory 201852 kb
Host smart-393704a9-b439-4c69-a0ad-b48dce23429f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397516702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3397516702
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.699107862
Short name T313
Test name
Test status
Simulation time 334035615664 ps
CPU time 818.29 seconds
Started Apr 18 12:47:14 PM PDT 24
Finished Apr 18 01:00:53 PM PDT 24
Peak memory 202244 kb
Host smart-106578e7-d9b4-41b9-bb0b-cbb7cdce64e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699107862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.699107862
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2171636514
Short name T256
Test name
Test status
Simulation time 496557940152 ps
CPU time 1088.31 seconds
Started Apr 18 12:47:21 PM PDT 24
Finished Apr 18 01:05:30 PM PDT 24
Peak memory 202320 kb
Host smart-7ba15636-a3b1-40ad-bb94-b3dec04a26c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171636514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2171636514
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.60000048
Short name T497
Test name
Test status
Simulation time 328513551407 ps
CPU time 376.08 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:53:34 PM PDT 24
Peak memory 202284 kb
Host smart-d240bf3b-34c9-435c-bcf5-f8115c288b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60000048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.60000048
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2841746277
Short name T506
Test name
Test status
Simulation time 497894610177 ps
CPU time 370.67 seconds
Started Apr 18 12:47:13 PM PDT 24
Finished Apr 18 12:53:25 PM PDT 24
Peak memory 202136 kb
Host smart-e45c6233-812c-4683-abf8-b9fe315ace7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841746277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2841746277
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3145250742
Short name T498
Test name
Test status
Simulation time 159694528622 ps
CPU time 82.22 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:48:39 PM PDT 24
Peak memory 202292 kb
Host smart-5f4a24a0-a263-43f8-8d6f-c531f81efaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145250742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3145250742
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2233286570
Short name T396
Test name
Test status
Simulation time 487653239244 ps
CPU time 291.51 seconds
Started Apr 18 12:47:14 PM PDT 24
Finished Apr 18 12:52:07 PM PDT 24
Peak memory 202252 kb
Host smart-591e7054-36e3-4645-a4a6-2f0537fa1f14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233286570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2233286570
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3520032819
Short name T676
Test name
Test status
Simulation time 170411519107 ps
CPU time 102.37 seconds
Started Apr 18 12:47:19 PM PDT 24
Finished Apr 18 12:49:03 PM PDT 24
Peak memory 202256 kb
Host smart-221f761c-fa51-4379-9c75-ecb75f2f1b1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520032819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3520032819
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3329026502
Short name T602
Test name
Test status
Simulation time 398885896891 ps
CPU time 459.94 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:54:56 PM PDT 24
Peak memory 202200 kb
Host smart-e6cb4455-c835-4b2c-a4e5-ba059259af0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329026502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3329026502
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3642086205
Short name T239
Test name
Test status
Simulation time 72873322635 ps
CPU time 262.39 seconds
Started Apr 18 12:47:12 PM PDT 24
Finished Apr 18 12:51:35 PM PDT 24
Peak memory 202408 kb
Host smart-1335cc87-7e5c-4818-9a3e-9c8667be35ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642086205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3642086205
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2707958337
Short name T744
Test name
Test status
Simulation time 46711442492 ps
CPU time 74.9 seconds
Started Apr 18 12:47:14 PM PDT 24
Finished Apr 18 12:48:30 PM PDT 24
Peak memory 201984 kb
Host smart-ecba842a-82e4-4991-bcbb-4dc7f2617671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707958337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2707958337
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.10256038
Short name T430
Test name
Test status
Simulation time 3131050682 ps
CPU time 1.47 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:47:20 PM PDT 24
Peak memory 202028 kb
Host smart-1850f413-46b7-4667-92f4-c42b6c697069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10256038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.10256038
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2369575635
Short name T716
Test name
Test status
Simulation time 6010879005 ps
CPU time 14.09 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:47:31 PM PDT 24
Peak memory 202044 kb
Host smart-cf8709a7-981c-4105-bb23-ba3eea465d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369575635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2369575635
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2482276506
Short name T222
Test name
Test status
Simulation time 195929997930 ps
CPU time 94.32 seconds
Started Apr 18 12:47:12 PM PDT 24
Finished Apr 18 12:48:48 PM PDT 24
Peak memory 202360 kb
Host smart-19ae6d02-0380-41e9-91a6-ec9c35ec9c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482276506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2482276506
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2874454184
Short name T230
Test name
Test status
Simulation time 114658815215 ps
CPU time 335.82 seconds
Started Apr 18 12:47:12 PM PDT 24
Finished Apr 18 12:52:49 PM PDT 24
Peak memory 210864 kb
Host smart-c85adb0a-895d-4a28-9823-3c2aadb516bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874454184 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2874454184
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1663020005
Short name T71
Test name
Test status
Simulation time 301497605 ps
CPU time 0.83 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:47:19 PM PDT 24
Peak memory 201852 kb
Host smart-3fffb3eb-a40b-49d5-9023-56f42697b70c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663020005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1663020005
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.704190104
Short name T758
Test name
Test status
Simulation time 179560557887 ps
CPU time 215.48 seconds
Started Apr 18 12:47:12 PM PDT 24
Finished Apr 18 12:50:49 PM PDT 24
Peak memory 202148 kb
Host smart-ea6e1910-fed7-4cf4-9822-e80ca679fac7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704190104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.704190104
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.530843045
Short name T207
Test name
Test status
Simulation time 321852291256 ps
CPU time 193.46 seconds
Started Apr 18 12:47:18 PM PDT 24
Finished Apr 18 12:50:33 PM PDT 24
Peak memory 202180 kb
Host smart-0a686f8a-a91c-4793-b16c-a403a17a8f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530843045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.530843045
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2691441232
Short name T729
Test name
Test status
Simulation time 161820734947 ps
CPU time 358.93 seconds
Started Apr 18 12:47:39 PM PDT 24
Finished Apr 18 12:53:39 PM PDT 24
Peak memory 202168 kb
Host smart-a531816e-d9a9-465e-b7bf-6c509b6d56ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691441232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2691441232
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1331329296
Short name T330
Test name
Test status
Simulation time 160739608533 ps
CPU time 151.69 seconds
Started Apr 18 12:47:13 PM PDT 24
Finished Apr 18 12:49:45 PM PDT 24
Peak memory 202152 kb
Host smart-8d669be2-33c8-43ba-a180-3c5afc2c8d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331329296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1331329296
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1380769740
Short name T634
Test name
Test status
Simulation time 327668496450 ps
CPU time 190.6 seconds
Started Apr 18 12:47:17 PM PDT 24
Finished Apr 18 12:50:29 PM PDT 24
Peak memory 202104 kb
Host smart-75483098-530d-4e65-b245-3a7e83963858
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380769740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1380769740
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1517218956
Short name T717
Test name
Test status
Simulation time 615249639037 ps
CPU time 344.1 seconds
Started Apr 18 12:47:20 PM PDT 24
Finished Apr 18 12:53:05 PM PDT 24
Peak memory 202224 kb
Host smart-9bbeb469-b017-4321-a9ff-bcd5c514d6f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517218956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1517218956
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2930996217
Short name T677
Test name
Test status
Simulation time 124004035418 ps
CPU time 574.57 seconds
Started Apr 18 12:47:13 PM PDT 24
Finished Apr 18 12:56:49 PM PDT 24
Peak memory 202516 kb
Host smart-3c89e3ff-46af-46aa-9c6f-1f9a20b8f082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930996217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2930996217
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1599101874
Short name T645
Test name
Test status
Simulation time 35312910776 ps
CPU time 83.82 seconds
Started Apr 18 12:47:19 PM PDT 24
Finished Apr 18 12:48:44 PM PDT 24
Peak memory 202060 kb
Host smart-641e54ef-c592-40e8-a815-c860dbf47da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599101874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1599101874
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2906261075
Short name T581
Test name
Test status
Simulation time 3691538236 ps
CPU time 1.3 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 12:47:18 PM PDT 24
Peak memory 202008 kb
Host smart-ccb71aae-4e16-4a0e-8cb3-f64c9e29afe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906261075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2906261075
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.4283409052
Short name T458
Test name
Test status
Simulation time 6146638973 ps
CPU time 7.69 seconds
Started Apr 18 12:47:12 PM PDT 24
Finished Apr 18 12:47:21 PM PDT 24
Peak memory 201968 kb
Host smart-c75485b4-d975-46d5-8334-7212956e4249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283409052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.4283409052
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.4076785861
Short name T369
Test name
Test status
Simulation time 335257870991 ps
CPU time 817.91 seconds
Started Apr 18 12:47:15 PM PDT 24
Finished Apr 18 01:00:55 PM PDT 24
Peak memory 202236 kb
Host smart-273e181e-3b5e-4f73-9b3c-6af44a538ee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076785861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
4076785861
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.4014378372
Short name T341
Test name
Test status
Simulation time 493187997821 ps
CPU time 243.31 seconds
Started Apr 18 12:47:14 PM PDT 24
Finished Apr 18 12:51:19 PM PDT 24
Peak memory 210532 kb
Host smart-47a9cd9d-a257-459b-bde1-6a7e2164e485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014378372 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.4014378372
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%