Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7192	1			T9	11		T11	46		T13	12
testmodes[AdcCtrlTestmodeNormal]	5651	1			T1	2		T3	3		T4	1
testmodes[AdcCtrlTestmodeLowpower]	5799	1			T2	2		T4	1		T5	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3855	1			T9	5		T11	11		T13	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1786	1			T9	5		T11	17		T13	8
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1450	1			T11	18		T14	8		T25	38
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1782	1			T9	5		T11	15		T13	9
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2044	1			T1	1		T3	2		T9	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1476	1			T11	14		T14	4		T25	29
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1435	1			T11	20		T14	5		T25	38
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1483	1			T4	1		T11	11		T14	7
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2632	1			T2	1		T5	1		T6	17