Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23370

1

T1

2

T2

16

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3524

1

T2

12

T3

1

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21014

1

T2

16

T3

1

T5

9

auto[1]

5880

1

T1

2

T2

12

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	63	1			T198	5		T199	1		T160	5
values[1]	775	1			T2	16		T5	12		T36	1
values[2]	666	1			T142	14		T136	23		T137	15
values[3]	780	1			T12	1		T13	1		T137	1
values[4]	2772	1			T1	2		T4	25		T8	11
values[5]	612	1			T30	24		T142	13		T138	6
values[6]	683	1			T2	12		T3	1		T4	30
values[7]	747	1			T3	1		T30	8		T141	9
values[8]	767	1			T3	1		T36	1		T183	15
values[9]	1297	1			T5	9		T36	1		T26	15
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	995	1			T2	16		T5	12		T36	1
values[1]	594	1			T12	1		T136	23		T137	1
values[2]	792	1			T13	1		T41	15		T144	15
values[3]	2819	1			T1	2		T4	25		T8	11
values[4]	636	1			T2	12		T30	24		T142	13
values[5]	783	1			T3	2		T4	30		T13	32
values[6]	683	1			T141	9		T17	4		T239	1
values[7]	787	1			T3	1		T36	1		T142	12
values[8]	775	1			T5	9		T36	1		T137	5
values[9]	279	1			T26	15		T184	11		T199	12
minimum	17751	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T2	16		T5	8		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	1		T30	5		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T136	23		T138	1		T141	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T137	1		T139	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	1		T144	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T41	15		T146	1		T240	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T1	2		T4	13		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T140	19		T241	1		T93	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T142	13		T141	15		T194	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	12		T30	3		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T3	1		T4	12		T30	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	1		T13	16		T25	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	4		T242	1		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T141	9		T239	1		T193	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	1		T183	11		T243	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T36	1		T142	12		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	9		T240	10		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T36	1		T137	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T199	1		T235	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T26	1		T184	1		T22	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17604	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	4		T15	6		T144	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	1		T30	4		T137	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T218	12		T245	7		T246	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T139	16		T247	14		T151	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T144	14		T146	4		T147	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T146	13		T149	6		T248	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	858	1			T4	12		T8	10		T249	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T241	1		T250	26		T75	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T194	8		T92	2		T96	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	21		T138	5		T175	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	18		T30	4		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	16		T25	17		T28	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T242	15		T34	3		T251	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T18	4		T19	5		T168	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T183	4		T243	11		T217	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T45	12		T98	8		T210	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T18	1		T175	2		T96	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T137	4		T198	9		T252	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T199	11		T235	16		T244	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T26	14		T184	10		T22	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	2		T15	1		T16	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T198	3		T199	1		T160	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T179	16		T253	10		T79	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	16		T5	8		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	1		T30	5		T139	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T142	14		T136	23		T254	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T137	1		T247	1		T176	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	1		T144	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	1		T137	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T1	2		T4	13		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T41	15		T149	3		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T142	13		T141	15		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T30	3		T138	1		T140	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	12		T145	1		T140	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	12		T3	1		T13	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	1		T30	4		T17	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T141	9		T150	1		T193	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	1		T183	11		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T36	1		T239	1		T98	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T5	9		T240	10		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T36	1		T26	1		T142	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T198	2		T160	2		T255	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T253	10		T79	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	4		T15	6		T144	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	1		T30	4		T139	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T256	11		T245	7		T257	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T137	14		T247	14		T176	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T144	14		T147	2		T175	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T146	13		T248	1		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	861	1			T4	12		T8	10		T249	33
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T149	6		T241	1		T37	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T96	6		T258	5		T259	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	21		T138	5		T210	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	18		T147	9		T194	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	16		T25	17		T28	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T30	4		T149	15		T242	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T18	4		T260	3		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T183	4		T34	3		T217	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T98	8		T210	10		T154	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T18	1		T199	11		T175	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T26	14		T137	4		T184	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T2	1		T5	5		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T14	2		T30	5		T137	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T136	2		T138	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	1		T137	1		T139	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	1		T144	15		T146	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T41	1		T146	14		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T1	2		T4	13		T8	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T140	1		T241	2		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T142	1		T141	1		T194	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	1		T30	22		T138	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	1		T4	19		T30	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	1		T13	17		T25	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	3		T242	16		T34	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T141	1		T239	1		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	1		T183	5		T243	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T36	1		T142	1		T45	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	1		T240	1		T18	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T36	1		T137	5		T198	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T199	12		T235	17		T244	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T26	15		T184	11		T22	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17738	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	15		T5	7		T142	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T30	4		T149	7		T193	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T136	21		T141	13		T245	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T139	11		T19	3		T261	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T175	4		T38	3		T168	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T41	14		T240	12		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T4	12		T10	17		T24	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T140	18		T93	2		T250	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T142	12		T141	14		T92	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	11		T30	2		T140	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	11		T30	3		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	15		T25	12		T28	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T17	1		T222	2		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T141	8		T193	17		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T183	10		T243	10		T262	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T142	11		T98	8		T154	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	8		T240	9		T175	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T93	8		T263	4		T206	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T223	3		T189	22		T264	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T22	3		T265	8		T266	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T267	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T198	3		T199	1		T160	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T179	1		T253	11		T79	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T2	1		T5	5		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	2		T30	5		T139	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T142	1		T136	2		T254	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T137	15		T247	15		T176	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	1		T144	15		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T12	1		T137	1		T146	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T1	2		T4	13		T8	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T41	1		T149	7		T241	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T142	1		T141	1		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T30	22		T138	6		T140	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	19		T145	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	1		T3	1		T13	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T30	5		T17	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T141	1		T150	1		T193	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	1		T183	5		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T36	1		T239	1		T98	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T5	1		T240	1		T18	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T36	1		T26	15		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T198	2		T160	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T179	15		T253	9		T79	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	15		T5	7		T15	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	4		T139	11		T149	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T142	13		T136	21		T268	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T176	10		T261	2		T269	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T141	13		T175	4		T38	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T240	12		T270	10		T19	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T4	12		T10	17		T24	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T41	14		T149	2		T37	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T142	12		T141	14		T96	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T30	2		T140	20		T250	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	11		T140	8		T92	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T2	11		T13	15		T25	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T30	3		T17	1		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	8		T193	17		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T183	10		T262	14		T217	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T98	8		T154	5		T206	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T5	8		T240	9		T175	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T142	11		T93	8		T263	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23347

1

T1

2

T2

16

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3547

1

T2

12

T3

1

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21002

1

T2

16

T3

1

T5

9

auto[1]

5892

1

T1

2

T2

12

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	219	1			T18	3		T96	20		T271	13
values[1]	793	1			T5	12		T36	1		T14	2
values[2]	740	1			T2	16		T12	1		T142	14
values[3]	692	1			T13	1		T137	1		T144	15
values[4]	2815	1			T1	2		T4	25		T8	11
values[5]	660	1			T30	24		T142	13		T138	6
values[6]	689	1			T2	12		T3	1		T4	30
values[7]	708	1			T3	1		T141	9		T17	4
values[8]	742	1			T3	1		T36	1		T183	15
values[9]	1104	1			T5	9		T36	1		T26	15
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	810	1			T2	16		T14	2		T30	9
values[1]	638	1			T12	1		T136	23		T137	1
values[2]	852	1			T13	1		T41	15		T144	15
values[3]	2787	1			T1	2		T4	25		T8	11
values[4]	652	1			T2	12		T30	24		T142	13
values[5]	741	1			T3	2		T4	30		T13	32
values[6]	711	1			T141	9		T17	4		T239	1
values[7]	738	1			T3	1		T36	1		T142	12
values[8]	894	1			T36	1		T137	5		T184	11
values[9]	196	1			T5	9		T26	15		T96	20
minimum	17875	1			T5	12		T6	18		T7	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T2	16		T142	14		T15	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	1		T30	5		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T136	23		T138	1		T141	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T137	1		T139	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	1		T144	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T41	15		T146	1		T240	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T1	2		T4	13		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T140	19		T241	1		T93	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T142	13		T141	15		T194	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	12		T30	3		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	1		T4	12		T30	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T13	16		T25	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T17	4		T242	1		T251	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T141	9		T239	1		T193	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	1		T183	11		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T36	1		T142	12		T98	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T240	10		T18	2		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T36	1		T137	1		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T5	9		T96	10		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T26	1		T271	1		T266	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17644	1			T5	8		T6	18		T7	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T215	12		T78	1		T272	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	6		T144	9		T183	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	1		T30	4		T137	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T218	12		T256	11		T245	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T139	16		T247	14		T176	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T144	14		T146	4		T147	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T146	13		T149	6		T248	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	874	1			T4	12		T8	10		T249	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T241	1		T250	26		T211	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T194	8		T92	2		T96	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T30	21		T138	5		T175	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	18		T30	4		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	16		T25	17		T28	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T242	15		T251	4		T222	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T18	4		T19	5		T168	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T183	4		T34	3		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T98	8		T210	10		T154	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T18	1		T199	11		T175	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T137	4		T184	10		T198	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T96	10		T235	16		T244	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T26	14		T271	12		T266	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	4		T13	2		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T215	9		T273	8		T79	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T18	2		T96	10		T235	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T271	1		T23	2		T274	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	8		T36	1		T15	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	1		T30	5		T149	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	16		T142	14		T136	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T137	1		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	1		T144	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T137	1		T146	1		T240	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T1	2		T4	13		T8	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T41	15		T149	3		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T142	13		T141	15		T96	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T30	3		T138	1		T140	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	12		T30	4		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	12		T3	1		T13	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	1		T17	4		T149	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T141	9		T150	1		T193	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T183	11		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T36	1		T239	1		T98	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T5	9		T240	10		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T36	1		T26	1		T142	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T18	1		T96	10		T235	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T271	12		T23	1		T275	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	4		T15	6		T144	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	1		T30	4		T149	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T218	12		T256	11		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T137	14		T139	16		T247	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T144	14		T147	2		T175	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T146	13		T248	1		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	867	1			T4	12		T8	10		T249	33
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T149	6		T241	1		T250	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T96	6		T259	25		T276	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	21		T138	5		T37	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	18		T30	4		T147	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	16		T25	17		T28	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T149	15		T242	15		T252	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T18	4		T260	3		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T183	4		T34	3		T217	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T98	8		T210	10		T154	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T199	11		T175	2		T243	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T26	14		T137	4		T184	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1