Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23559

1

T1

2

T4

25

T5

21

auto[ADC_CTRL_FILTER_COND_OUT]

3335

1

T2

28

T3

3

T4

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20989

1

T3

3

T4

25

T5

9

auto[1]

5905

1

T1

2

T2

28

T4

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	270	1			T3	1		T5	12		T260	11
values[0]	33	1			T150	1		T340	13		T341	8
values[1]	842	1			T2	12		T3	1		T13	32
values[2]	3037	1			T1	2		T8	11		T10	18
values[3]	654	1			T4	25		T36	1		T14	2
values[4]	840	1			T5	9		T41	15		T141	14
values[5]	675	1			T36	1		T15	15		T140	3
values[6]	564	1			T2	16		T30	8		T137	1
values[7]	758	1			T4	30		T25	30		T142	12
values[8]	527	1			T12	1		T146	5		T147	3
values[9]	962	1			T3	1		T13	1		T36	1
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	752	1			T3	1		T13	32		T28	34
values[1]	2970	1			T1	2		T8	11		T10	18
values[2]	601	1			T4	25		T36	1		T30	24
values[3]	975	1			T36	1		T41	15		T141	14
values[4]	615	1			T5	9		T15	15		T141	9
values[5]	679	1			T2	16		T25	30		T30	8
values[6]	593	1			T4	30		T142	12		T145	1
values[7]	616	1			T12	1		T13	1		T141	15
values[8]	977	1			T3	2		T5	12		T36	1
values[9]	69	1			T336	7		T269	9		T342	11
minimum	18047	1			T2	12		T6	18		T7	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	16		T28	14		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	1		T30	5		T136	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1693	1			T1	2		T8	1		T10	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	1		T26	1		T136	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	13		T36	1		T30	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T142	14		T183	11		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T36	1		T149	12		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T41	15		T141	14		T193	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	9		T141	9		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	9		T174	1		T175	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T140	3		T92	14		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	16		T25	13		T30	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T217	18		T158	1		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	12		T142	12		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T141	15		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T198	3		T75	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T5	8		T36	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	2		T137	1		T240	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T336	1		T343	16		T330	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T269	3		T342	7		T344	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17715	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T2	12		T140	9		T150	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	16		T28	20		T137	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T30	4		T149	6		T263	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T8	10		T249	33		T184	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T26	14		T139	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	12		T30	21		T183	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T183	9		T146	9		T176	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T149	15		T38	1		T243	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T199	11		T248	1		T45	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T146	13		T175	1		T247	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	6		T175	2		T151	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T92	2		T177	4		T252	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T25	17		T30	4		T144	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T217	10		T271	11		T296	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	18		T241	1		T152	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T146	4		T147	2		T198	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T198	2		T75	8		T309	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	4		T16	2		T260	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T137	4		T149	8		T151	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T336	6		T343	13		T330	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T269	6		T342	4		T344	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T34	3		T155	9		T246	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T5	8		T260	8		T218	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T3	1		T215	7		T217	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T341	8		T345	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T150	1		T340	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T13	16		T28	14		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	12		T3	1		T30	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1718	1			T1	2		T8	1		T10	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T26	1		T136	23		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	13		T36	1		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T142	14		T183	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	9		T149	12		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T41	15		T141	14		T248	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T36	1		T140	3		T141	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	9		T193	6		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T177	1		T252	1		T294	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	16		T30	4		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T92	14		T217	18		T271	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	12		T25	13		T142	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	1		T146	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T198	3		T168	14		T219	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T36	1		T136	1		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	1		T13	1		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T5	4		T260	3		T218	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T215	12		T217	6		T159	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T340	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T13	16		T28	20		T137	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T30	4		T149	6		T34	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	913	1			T8	10		T249	33		T184	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	14		T139	16		T18	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	12		T30	21		T183	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	1		T183	9		T146	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T149	15		T243	11		T96	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T248	1		T45	12		T98	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T146	13		T175	1		T247	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	6		T199	11		T175	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T177	4		T252	2		T346	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T30	4		T138	5		T16	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T92	2		T217	10		T271	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T4	18		T25	17		T144	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T146	4		T147	2		T296	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T198	2		T168	12		T219	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T16	2		T198	9		T37	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T137	4		T149	8		T151	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	17		T28	21		T137	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	1		T30	5		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T1	2		T8	11		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	2		T26	15		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	13		T36	1		T30	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T142	1		T183	10		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T36	1		T149	16		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T41	1		T141	1		T193	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T141	1		T146	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	11		T174	1		T175	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T140	1		T92	3		T177	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	1		T25	18		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T217	11		T158	1		T271	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	19		T142	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T141	1		T146	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	1		T198	3		T75	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T5	5		T36	1		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	2		T137	5		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T336	7		T343	14		T330	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T269	7		T342	8		T344	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17815	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T2	1		T140	1		T150	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	15		T28	13		T96	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T30	4		T136	8		T149	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T10	17		T24	20		T143	41
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T136	13		T139	11		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	12		T30	2		T142	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T142	13		T183	10		T176	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T149	11		T281	10		T187	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T41	14		T141	13		T193	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	8		T141	8		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	4		T175	9		T261	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T140	2		T92	13		T211	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	15		T25	12		T30	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T217	17		T296	14		T282	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	11		T142	11		T152	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T141	14		T37	15		T294	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T198	2		T75	10		T309	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	7		T16	2		T193	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T240	12		T149	7		T281	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T343	15		T330	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T269	2		T342	3		T347	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T281	14		T263	4		T250	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T2	11		T140	8		T19	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T5	5		T260	4		T218	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T3	1		T215	13		T217	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T341	1		T345	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T150	1		T340	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T13	17		T28	21		T137	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	1		T3	1		T30	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T1	2		T8	11		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T26	15		T136	2		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	13		T36	1		T30	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	2		T142	1		T183	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	1		T149	16		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T41	1		T141	1		T248	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T36	1		T140	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	11		T193	1		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T177	5		T252	3		T294	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	1		T30	5		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T92	3		T217	11		T271	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T4	19		T25	18		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T146	5		T147	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T198	3		T168	13		T219	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T36	1		T136	1		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	1		T13	1		T137	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T5	7		T260	7		T236	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T215	6		T217	7		T75	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T341	7		T345	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T13	15		T28	13		T281	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	11		T30	4		T140	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T10	17		T24	20		T143	41
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T136	21		T139	11		T18	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	12		T30	2		T142	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T142	13		T183	10		T176	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	8		T149	11		T281	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T41	14		T141	13		T98	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T140	2		T141	8		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	4		T193	5		T175	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T294	11		T279	15		T264	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T2	15		T30	3		T140	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T92	13		T217	17		T211	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	11		T25	12		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T296	14		T282	12		T294	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T198	2		T168	13		T219	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T16	2		T141	14		T193	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T240	12		T149	7		T281	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15