Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23611

1

T1

2

T4

25

T5

21

auto[ADC_CTRL_FILTER_COND_OUT]

3283

1

T2

28

T3

3

T4

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21003

1

T3

3

T4

25

T5

9

auto[1]

5891

1

T1

2

T2

28

T4

30

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T336	7		T344	2		-	-
values[0]	119	1			T140	9		T150	1		T263	9
values[1]	786	1			T2	12		T3	1		T13	32
values[2]	3002	1			T1	2		T8	11		T10	18
values[3]	614	1			T4	25		T36	1		T14	2
values[4]	880	1			T5	9		T41	15		T141	14
values[5]	698	1			T36	1		T15	15		T140	3
values[6]	555	1			T2	16		T30	8		T137	1
values[7]	757	1			T4	30		T25	30		T142	12
values[8]	502	1			T12	1		T146	5		T147	3
values[9]	1240	1			T3	2		T5	12		T13	1
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1000	1			T2	12		T3	1		T13	32
values[1]	3016	1			T1	2		T8	11		T10	18
values[2]	530	1			T4	25		T36	1		T30	24
values[3]	990	1			T36	1		T41	15		T141	14
values[4]	656	1			T5	9		T15	15		T141	9
values[5]	676	1			T2	16		T25	30		T30	8
values[6]	612	1			T4	30		T142	12		T145	1
values[7]	580	1			T12	1		T13	1		T141	15
values[8]	893	1			T3	2		T36	1		T136	1
values[9]	143	1			T5	12		T281	7		T336	7
minimum	17798	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T13	16		T28	14		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	12		T3	1		T30	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1705	1			T1	2		T8	1		T10	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	1		T26	1		T136	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T4	13		T36	1		T30	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T142	14		T183	11		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T36	1		T149	12		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T41	15		T141	14		T193	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	9		T141	9		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	9		T174	1		T175	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T140	3		T92	14		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	16		T25	13		T30	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T217	18		T158	1		T252	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	12		T142	12		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T141	15		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	1		T198	3		T75	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T36	1		T136	1		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	2		T137	1		T240	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T5	8		T336	1		T236	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T281	7		T269	3		T284	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17605	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T348	12		T192	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T13	16		T28	20		T137	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T30	4		T149	6		T34	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T8	10		T249	33		T184	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	1		T26	14		T139	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	12		T30	21		T183	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T183	9		T146	9		T168	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T149	15		T38	1		T243	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T199	11		T248	1		T45	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T146	13		T175	1		T247	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	6		T175	2		T151	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T92	2		T177	4		T271	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T25	17		T30	4		T144	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T217	10		T252	2		T296	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	18		T241	1		T152	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T146	4		T147	2		T198	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T198	2		T75	8		T314	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T16	2		T260	3		T270	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T137	4		T149	8		T151	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T5	4		T336	6		T236	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T269	6		T284	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T348	9		T192	11		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T336	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T344	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T263	5		T341	8		T349	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T140	9		T150	1		T340	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T13	16		T28	14		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	12		T3	1		T30	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1718	1			T1	2		T8	1		T10	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	1		T136	23		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	13		T36	1		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	1		T142	14		T183	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	9		T149	12		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T41	15		T141	14		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T36	1		T140	3		T141	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	9		T193	6		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T177	1		T252	1		T294	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	16		T30	4		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T92	14		T217	18		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	12		T25	13		T142	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T146	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T198	3		T168	14		T219	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T5	8		T36	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T3	2		T13	1		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T336	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T344	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T263	4		T349	11		T350	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T340	12		T348	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	16		T28	20		T194	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T30	4		T149	6		T34	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T8	10		T249	33		T137	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T26	14		T139	16		T18	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	12		T30	21		T183	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T14	1		T183	9		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T149	15		T243	11		T96	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T146	9		T175	2		T248	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T146	13		T175	1		T247	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	6		T199	11		T151	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T177	4		T252	2		T346	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	4		T144	9		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T92	2		T217	10		T271	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T4	18		T25	17		T144	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T146	4		T147	2		T296	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T198	2		T168	12		T219	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T5	4		T16	2		T198	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T137	4		T149	8		T151	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T13	17		T28	21		T137	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	1		T3	1		T30	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T1	2		T8	11		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	2		T26	15		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	13		T36	1		T30	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T142	1		T183	10		T146	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T36	1		T149	16		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T41	1		T141	1		T193	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	1		T141	1		T146	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	11		T174	1		T175	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T140	1		T92	3		T177	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	1		T25	18		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T217	11		T158	1		T252	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	19		T142	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	1		T141	1		T146	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	1		T198	3		T75	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T36	1		T136	1		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	2		T137	5		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T5	5		T336	7		T236	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T281	1		T269	7		T284	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17739	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T348	10		T192	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T13	15		T28	13		T281	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	11		T30	4		T136	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T10	17		T24	20		T143	41
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T136	13		T139	11		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	12		T30	2		T142	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T142	13		T183	10		T168	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T149	11		T281	10		T187	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T41	14		T141	13		T193	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	8		T141	8		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	4		T175	9		T261	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T140	2		T92	13		T211	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	15		T25	12		T30	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T217	17		T296	14		T282	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	11		T142	11		T152	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T141	14		T37	15		T297	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T198	2		T75	10		T294	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T16	2		T193	17		T260	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T240	12		T149	7		T98	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T5	7		T236	12		T351	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T281	6		T269	2		T284	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T267	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T348	11		T192	13		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T336	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T344	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T263	5		T341	1		T349	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T140	1		T150	1		T340	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	17		T28	21		T194	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	1		T3	1		T30	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T1	2		T8	11		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T26	15		T136	2		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	13		T36	1		T30	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	2		T142	1		T183	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	1		T149	16		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T41	1		T141	1		T146	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T36	1		T140	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	11		T193	1		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T177	5		T252	3		T294	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	1		T30	5		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T92	3		T217	11		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T4	19		T25	18		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T146	5		T147	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T198	3		T168	13		T219	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	404	1			T5	5		T36	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T3	2		T13	1		T137	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T263	4		T341	7		T349	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T140	8		T348	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T13	15		T28	13		T281	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	11		T30	4		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T10	17		T24	20		T143	41
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T136	21		T139	11		T18	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	12		T30	2		T142	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T142	13		T183	10		T168	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	8		T149	11		T281	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T41	14		T141	13		T175	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T140	2		T141	8		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	4		T193	5		T93	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T294	11		T264	6		T352	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T2	15		T30	3		T140	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T92	13		T217	17		T211	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	11		T25	12		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T296	14		T282	12		T298	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T198	2		T168	13		T219	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T5	7		T16	2		T141	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T240	12		T149	7		T281	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15