Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20994

1

T2

12

T3

2

T4

30

auto[ADC_CTRL_FILTER_COND_OUT]

5900

1

T1

2

T2

16

T3

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21007

1

T2

12

T3

2

T4

30

auto[1]

5887

1

T1

2

T2

16

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	284	1			T16	9		T146	10		T92	16
values[0]	106	1			T168	24		T215	21		T162	5
values[1]	689	1			T4	30		T5	12		T28	34
values[2]	766	1			T3	1		T14	2		T30	24
values[3]	524	1			T36	1		T25	30		T184	11
values[4]	597	1			T3	1		T142	26		T139	28
values[5]	708	1			T30	9		T41	15		T136	9
values[6]	754	1			T2	28		T4	25		T13	32
values[7]	832	1			T5	9		T30	8		T136	14
values[8]	784	1			T36	1		T15	15		T136	1
values[9]	3118	1			T1	2		T3	1		T8	11
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	701	1			T4	30		T5	12		T28	34
values[1]	2897	1			T1	2		T3	1		T8	11
values[2]	489	1			T36	1		T25	30		T142	12
values[3]	689	1			T3	1		T30	9		T142	14
values[4]	666	1			T26	15		T41	15		T144	15
values[5]	862	1			T2	28		T4	25		T13	32
values[6]	775	1			T5	9		T30	8		T136	14
values[7]	730	1			T12	1		T13	1		T36	1
values[8]	896	1			T3	1		T36	1		T144	10
values[9]	178	1			T175	11		T98	17		T158	1
minimum	18011	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	12		T28	14		T240	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	8		T30	3		T183	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	1		T141	15		T241	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1636	1			T1	2		T8	1		T10	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T184	1		T141	9		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T36	1		T25	13		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	1		T136	9		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T30	5		T142	14		T139	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T26	1		T145	1		T141	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T41	15		T144	1		T240	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	12		T146	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	16		T4	13		T13	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T136	14		T138	1		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	9		T30	4		T137	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	1		T15	9		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	1		T36	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T144	1		T183	11		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	1		T36	1		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T158	1		T252	1		T309	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T175	5		T98	9		T316	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17651	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T247	1		T168	16		T215	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	18		T28	20		T149	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	4		T30	21		T183	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T241	1		T168	9		T20	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	898	1			T8	10		T14	1		T249	33
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T184	10		T98	2		T252	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T25	17		T35	11		T271	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T18	1		T270	16		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T30	4		T139	16		T260	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T26	14		T243	11		T296	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T144	14		T151	6		T270	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T146	13		T176	11		T19	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	12		T13	16		T198	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T199	11		T98	6		T218	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T30	4		T137	4		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	6		T137	14		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T146	4		T37	12		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T144	9		T183	9		T16	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	2		T18	4		T159	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T252	2		T309	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T175	6		T98	8		T263	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T247	14		T168	8		T215	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	5		T146	1		T92	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T316	1		T263	9		T211	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T162	1		T318	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T168	16		T215	12		T181	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	12		T28	14		T142	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	8		T140	19		T147	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T141	15		T168	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	1		T30	3		T183	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T184	1		T150	1		T281	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T36	1		T25	13		T281	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	1		T140	9		T141	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T142	26		T139	12		T260	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T136	9		T145	1		T141	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T30	5		T41	15		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	12		T26	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	16		T4	13		T13	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T136	14		T138	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	9		T30	4		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T15	9		T136	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T36	1		T146	1		T37	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	1		T144	1		T183	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1741	1			T1	2		T3	1		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T16	4		T146	9		T92	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T263	11		T211	2		T353	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T162	4		T318	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T168	8		T215	9		T181	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	18		T28	20		T149	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	4		T147	11		T247	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T168	9		T215	12		T21	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	1		T30	21		T183	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T184	10		T241	1		T98	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T25	17		T210	9		T271	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T18	1		T270	16		T210	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T139	16		T260	3		T35	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T296	3		T258	5		T327	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T30	4		T144	14		T151	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	14		T243	11		T176	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	12		T13	16		T198	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T146	13		T199	11		T98	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T30	4		T137	4		T138	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T15	6		T137	14		T175	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T146	4		T37	12		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T144	9		T183	9		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	991	1			T8	10		T249	33		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	19		T28	21		T240	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	5		T30	22		T183	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	1		T141	1		T241	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1226	1			T1	2		T8	11		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T184	11		T141	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	1		T25	18		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	1		T136	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T30	5		T142	1		T139	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T26	15		T145	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T41	1		T144	15		T240	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T2	1		T146	14		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	1		T4	13		T13	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T136	1		T138	1		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T30	5		T137	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T12	1		T15	11		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T36	1		T146	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T144	10		T183	10		T16	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T36	1		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T158	1		T252	3		T309	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T175	7		T98	9		T316	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17770	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T247	15		T168	9		T215	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	11		T28	13		T240	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	7		T30	2		T183	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T141	14		T187	14		T168	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1308	1			T10	17		T24	20		T143	41
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T141	8		T281	14		T93	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T25	12		T142	11		T281	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T136	8		T140	8		T193	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T30	4		T142	13		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T141	13		T243	10		T296	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T41	14		T240	12		T193	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T2	11		T176	17		T19	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	15		T4	12		T13	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T136	13		T277	9		T98	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	8		T30	3		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	4		T198	2		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T37	15		T38	3		T262	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T183	10		T16	2		T149	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	2		T18	2		T211	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T309	14		T319	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T175	4		T98	8		T263	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T142	12		T140	2		T287	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T168	15		T215	11		T222	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T16	7		T146	10		T92	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T316	1		T263	12		T211	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T162	5		T318	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T168	9		T215	10		T181	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	19		T28	21		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	5		T140	1		T147	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	1		T141	1		T168	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T14	2		T30	22		T183	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T184	11		T150	1		T281	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	1		T25	18		T281	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	1		T140	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T142	2		T139	17		T260	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T136	1		T145	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T30	5		T41	1		T144	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	1		T26	15		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	1		T4	13		T13	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T136	1		T138	1		T146	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	1		T30	5		T137	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T15	11		T136	1		T137	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T36	1		T146	5		T37	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	1		T144	10		T183	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1339	1			T1	2		T3	1		T8	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T16	2		T92	13		T263	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T263	8		T211	3		T354	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T168	15		T215	11		T181	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	11		T28	13		T142	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	7		T140	18		T281	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T141	14		T168	11		T215	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T30	2		T183	10		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T281	14		T187	14		T93	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T25	12		T281	6		T268	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T140	8		T141	8		T193	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T142	24		T139	11		T260	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	8		T141	13		T296	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T30	4		T41	14		T240	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	11		T243	10		T176	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	15		T4	12		T13	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T136	13		T277	9		T98	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	8		T30	3		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	4		T175	9		T176	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	15		T38	3		T262	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T183	10		T149	7		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1393	1			T10	17		T24	20		T143	41

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15