Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23364

1

T1

2

T2

12

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3530

1

T2

16

T3

1

T4

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20681

1

T3

1

T4

30

T5

12

auto[1]

6213

1

T1

2

T2

28

T3

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	32	1			T155	20		T355	9		T356	1
values[0]	89	1			T175	11		T168	24		T256	1
values[1]	629	1			T5	12		T36	1		T26	15
values[2]	653	1			T183	20		T138	6		T150	1
values[3]	768	1			T2	12		T3	2		T14	2
values[4]	664	1			T2	16		T4	30		T41	15
values[5]	2631	1			T1	2		T3	1		T8	11
values[6]	674	1			T36	1		T15	15		T146	14
values[7]	995	1			T28	34		T138	1		T239	1
values[8]	635	1			T5	9		T13	32		T30	8
values[9]	1392	1			T4	25		T12	1		T13	1
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	916	1			T5	12		T36	1		T26	15
values[1]	609	1			T3	1		T14	2		T137	15
values[2]	743	1			T2	16		T3	1		T4	30
values[3]	2790	1			T1	2		T2	12		T8	11
values[4]	502	1			T3	1		T140	3		T174	1
values[5]	883	1			T36	1		T28	34		T15	15
values[6]	717	1			T136	14		T138	1		T145	1
values[7]	707	1			T5	9		T13	32		T30	8
values[8]	910	1			T4	25		T12	1		T13	1
values[9]	336	1			T25	30		T30	24		T240	10
minimum	17781	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T193	18		T175	1		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	8		T36	1		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	1		T138	1		T92	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	1		T137	1		T183	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T41	15		T17	1		T221	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	16		T3	1		T4	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T1	2		T2	12		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T149	8		T151	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	1		T140	3		T242	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T174	1		T175	10		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T36	1		T239	1		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T28	14		T15	9		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T136	14		T145	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T138	1		T148	1		T149	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	9		T30	4		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	16		T144	1		T140	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T4	13		T12	1		T142	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T13	1		T36	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T271	1		T357	10		T285	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T25	13		T30	3		T240	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17599	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T270	11		T320	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T175	1		T98	8		T168	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	4		T26	14		T184	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T138	5		T92	6		T168	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	1		T137	14		T183	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T241	1		T152	10		T98	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	18		T139	16		T261	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	862	1			T8	10		T30	4		T249	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T149	8		T303	11		T273	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T242	15		T215	9		T178	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T175	2		T177	2		T178	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T176	16		T19	5		T45	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T28	20		T15	6		T146	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T199	11		T176	11		T252	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T149	15		T151	6		T37	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T30	4		T198	2		T34	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	16		T144	14		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	12		T183	4		T16	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T137	4		T146	4		T149	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T271	11		T357	11		T285	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T25	17		T30	21		T102	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T270	11		T320	3		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T355	1		T356	1		T358	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T155	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T168	16		T256	1		T245	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T175	5		T246	9		T284	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T175	1		T40	1		T98	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	8		T36	1		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T138	1		T193	18		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T183	11		T150	1		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T2	12		T3	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	1		T14	1		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T41	15		T142	13		T140	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	16		T4	12		T139	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1574	1			T1	2		T3	1		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T174	1		T175	10		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T36	1		T242	1		T254	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	9		T146	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T239	1		T199	1		T281	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T28	14		T138	1		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	9		T30	4		T136	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	16		T144	1		T140	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	435	1			T4	13		T12	1		T142	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T13	1		T36	1		T25	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T355	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T155	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T168	8		T245	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T175	6		T246	6		T284	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T175	1		T98	8		T217	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	4		T26	14		T184	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	5		T92	6		T210	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T183	9		T198	9		T235	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T152	10		T98	2		T168	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	1		T137	14		T21	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T241	1		T151	8		T98	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	18		T139	16		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	836	1			T8	10		T30	4		T249	33
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T175	2		T177	2		T178	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T242	15		T19	5		T45	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T15	6		T146	13		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T199	11		T176	16		T252	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T28	20		T149	15		T151	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T30	4		T34	3		T243	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	16		T144	14		T147	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T4	12		T183	4		T16	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T25	17		T30	21		T137	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T193	1		T175	2		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	5		T36	1		T26	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T138	6		T92	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	2		T137	15		T183	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T41	1		T17	1		T221	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	1		T3	1		T4	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T1	2		T2	1		T8	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T149	9		T151	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	1		T140	1		T242	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T174	1		T175	3		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T36	1		T239	1		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T28	21		T15	11		T146	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	1		T145	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T138	1		T148	1		T149	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	1		T30	5		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	17		T144	15		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T4	13		T12	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	1		T36	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T271	12		T357	12		T285	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T25	18		T30	22		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17744	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T270	12		T320	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T193	17		T98	8		T168	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	7		T17	1		T175	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T92	8		T168	13		T215	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T183	10		T21	1		T359	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T41	14		T152	10		T277	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	15		T4	11		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T2	11		T10	17		T24	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T149	7		T310	12		T303	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T140	2		T215	11		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T175	9		T334	8		T223	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T176	10		T19	7		T250	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T28	13		T15	4		T92	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T136	13		T281	6		T176	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T149	11		T37	15		T217	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	8		T30	3		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	15		T140	8		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	12		T142	13		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T240	12		T149	2		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T357	9		T200	16		T181	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T25	12		T30	2		T240	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T282	3		T335	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T270	10		T320	6		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T355	9		T356	1		T358	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T155	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T168	9		T256	1		T245	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T175	7		T246	7		T284	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T175	2		T40	1		T98	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	5		T36	1		T26	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T138	6		T193	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T183	10		T150	1		T198	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	1		T3	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	1		T14	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T41	1		T142	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	1		T4	19		T139	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1148	1			T1	2		T3	1		T8	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T174	1		T175	3		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T36	1		T242	16		T254	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	11		T146	14		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T239	1		T199	12		T281	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T28	21		T138	1		T149	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	1		T30	5		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	17		T144	15		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	430	1			T4	13		T12	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T13	1		T36	1		T25	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T155	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T168	15		T245	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T175	4		T246	8		T284	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T98	8		T217	7		T263	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	7		T17	1		T260	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T193	17		T92	8		T222	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T183	10		T359	7		T273	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	11		T152	10		T277	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T142	11		T141	14		T193	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T41	14		T142	12		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	15		T4	11		T139	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T10	17		T24	20		T30	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T175	9		T310	12		T334	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T19	7		T222	9		T211	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	4		T262	10		T223	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T281	6		T176	10		T154	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T28	13		T149	11		T37	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	8		T30	3		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	15		T140	8		T263	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T4	12		T142	13		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T25	12		T30	2		T240	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15