Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23498

1

T1

2

T2

12

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3396

1

T2

16

T3

1

T4

30

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20890

1

T3

2

T4

30

T5

12

auto[1]

6004

1

T1

2

T2

28

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	311	1			T12	1		T30	24		T136	9
values[0]	50	1			T291	1		T245	16		T320	10
values[1]	758	1			T5	12		T36	1		T26	15
values[2]	591	1			T138	6		T150	1		T193	18
values[3]	749	1			T2	12		T3	2		T4	30
values[4]	646	1			T2	16		T30	9		T41	15
values[5]	2745	1			T1	2		T3	1		T8	11
values[6]	583	1			T36	1		T15	15		T146	14
values[7]	969	1			T28	34		T138	1		T239	1
values[8]	641	1			T5	9		T13	32		T30	8
values[9]	1119	1			T4	25		T13	1		T36	1
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	644	1			T5	12		T184	11		T17	4
values[1]	617	1			T3	1		T14	2		T137	15
values[2]	819	1			T2	28		T3	1		T4	30
values[3]	2782	1			T1	2		T8	11		T10	18
values[4]	505	1			T3	1		T174	1		T175	12
values[5]	826	1			T36	1		T28	34		T15	15
values[6]	715	1			T136	14		T138	1		T145	1
values[7]	731	1			T5	9		T13	32		T30	8
values[8]	1052	1			T4	25		T12	1		T13	1
values[9]	194	1			T30	24		T240	10		T102	2
minimum	18009	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T193	18		T175	1		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	8		T184	1		T17	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	1		T137	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	1		T198	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T2	12		T41	15		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	16		T3	1		T4	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T1	2		T8	1		T10	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T149	8		T151	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T242	1		T215	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T174	1		T175	10		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T36	1		T254	1		T176	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T28	14		T15	9		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T136	14		T145	1		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T138	1		T199	1		T37	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	9		T30	4		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	16		T140	9		T18	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T4	13		T12	1		T142	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	1		T36	1		T25	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T240	10		T355	1		T356	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T30	3		T102	1		T162	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17668	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T36	1		T26	1		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T175	1		T168	8		T210	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	4		T184	10		T147	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T137	14		T138	5		T92	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T198	9		T235	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T241	1		T152	10		T98	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	18		T183	9		T139	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	865	1			T8	10		T30	4		T249	33
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T149	8		T334	10		T303	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T242	15		T215	9		T250	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T175	2		T177	2		T178	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T176	16		T19	5		T45	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T28	20		T15	6		T146	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T149	15		T34	3		T151	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T199	11		T37	12		T251	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T30	4		T144	14		T147	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	16		T18	4		T243	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T4	12		T16	2		T146	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T25	17		T137	4		T183	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T355	8		T356	10		T165	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T30	21		T102	1		T162	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T26	14		T247	14		T270	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T12	1		T136	9		T155	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T30	3		T137	1		T16	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T245	9		T191	4		T360	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T291	1		T320	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T175	6		T96	7		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	8		T36	1		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T138	1		T193	18		T92	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T150	1		T198	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	12		T3	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T4	12		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T30	5		T41	15		T142	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T2	16		T139	12		T149	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1623	1			T1	2		T3	1		T8	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T174	1		T175	10		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	1		T254	1		T19	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	9		T146	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T239	1		T149	12		T281	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T28	14		T138	1		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	9		T30	4		T136	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	16		T140	9		T243	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T4	13		T142	14		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	1		T36	1		T25	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T155	9		T285	1		T355	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T30	21		T137	4		T16	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T245	7		T191	2		T360	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T320	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T175	7		T96	6		T98	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	4		T26	14		T184	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T138	5		T92	6		T222	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T198	9		T235	16		T273	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T137	14		T152	10		T98	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	18		T14	1		T183	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T30	4		T241	1		T151	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T139	16		T149	8		T23	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	852	1			T8	10		T249	33		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T175	2		T177	2		T178	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T19	5		T45	12		T271	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T15	6		T146	13		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T149	15		T151	6		T176	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T28	20		T199	11		T37	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T30	4		T144	14		T147	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	16		T243	11		T263	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T4	12		T16	2		T146	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T25	17		T183	4		T149	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T193	1		T175	2		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	5		T184	11		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T137	15		T138	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	2		T198	10		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	1		T41	1		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	1		T3	1		T4	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T1	2		T8	11		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T149	9		T151	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	1		T242	16		T215	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T174	1		T175	3		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T36	1		T254	1		T176	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T28	21		T15	11		T146	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T136	1		T145	1		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T138	1		T199	12		T37	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T30	5		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	17		T140	1		T18	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T4	13		T12	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	1		T36	1		T25	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T240	1		T355	9		T356	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T30	22		T102	2		T162	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17827	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T36	1		T26	15		T247	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T193	17		T168	15		T75	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T5	7		T17	1		T260	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T92	8		T215	6		T219	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T359	7		T333	11		T273	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	11		T41	14		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	15		T4	11		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T10	17		T24	20		T30	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T149	7		T310	12		T334	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T215	11		T250	11		T309	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T175	9		T222	9		T339	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T176	10		T19	7		T211	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T28	13		T15	4		T92	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T136	13		T149	11		T281	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T37	15		T217	17		T206	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	8		T30	3		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	15		T140	8		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T4	12		T142	13		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T25	12		T183	10		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T240	9		T165	8		T332	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T30	2		T179	18		T253	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T175	4		T96	6		T98	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T270	10		T305	14		T361	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T12	1		T136	1		T155	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T30	22		T137	5		T16	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T245	8		T191	3		T360	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T291	1		T320	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T175	9		T96	7		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	5		T36	1		T26	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	6		T193	1		T92	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T150	1		T198	10		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	1		T3	1		T137	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	1		T4	19		T14	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T30	5		T41	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	1		T139	17		T149	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T1	2		T3	1		T8	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T174	1		T175	3		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T36	1		T254	1		T19	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	11		T146	14		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T239	1		T149	16		T281	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T28	21		T138	1		T199	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	1		T30	5		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	17		T140	1		T243	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	378	1			T4	13		T142	1		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	1		T36	1		T25	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T136	8		T155	10		T321	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T30	2		T16	2		T270	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T245	8		T191	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T320	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T175	4		T96	6		T98	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	7		T17	1		T260	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T193	17		T92	8		T222	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T359	7		T273	10		T265	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	11		T152	10		T277	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	11		T142	11		T183	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	4		T41	14		T142	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	15		T139	11		T149	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T10	17		T24	20		T143	41
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T175	9		T310	12		T334	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T19	7		T309	11		T294	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	4		T262	10		T222	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T149	11		T281	6		T176	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T28	13		T37	15		T92	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	8		T30	3		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	15		T140	8		T243	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T4	12		T142	13		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T25	12		T183	10		T240	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15