Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23055

1

T1

2

T2

12

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3839

1

T2

16

T4

25

T5

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20573

1

T2

12

T3

2

T5

21

auto[1]

6321

1

T1

2

T2

16

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	182	1			T3	1		T12	1		T142	14
values[0]	31	1			T149	16		T102	2		T362	3
values[1]	634	1			T150	1		T221	1		T242	5
values[2]	623	1			T3	1		T4	25		T5	12
values[3]	663	1			T30	8		T142	13		T136	1
values[4]	793	1			T13	1		T15	15		T139	28
values[5]	649	1			T5	9		T14	2		T142	12
values[6]	731	1			T13	32		T28	34		T30	24
values[7]	874	1			T2	16		T144	25		T141	15
values[8]	594	1			T30	9		T16	9		T17	4
values[9]	3388	1			T1	2		T2	12		T3	1
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	682	1			T3	1		T4	25		T183	15
values[1]	587	1			T5	12		T36	1		T25	30
values[2]	624	1			T13	1		T142	13		T15	15
values[3]	796	1			T5	9		T141	9		T240	13
values[4]	783	1			T13	32		T14	2		T30	24
values[5]	810	1			T28	34		T41	15		T144	10
values[6]	2944	1			T1	2		T2	16		T8	11
values[7]	604	1			T4	30		T30	9		T17	5
values[8]	1069	1			T2	12		T3	2		T36	2
values[9]	95	1			T12	1		T210	10		T158	1
minimum	17900	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	1		T150	1		T248	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	13		T183	11		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T36	1		T25	13		T30	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	8		T136	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T145	1		T175	10		T92	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	1		T142	13		T15	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	9		T176	11		T251	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T141	9		T240	13		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	16		T142	12		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T14	1		T30	3		T136	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T41	15		T144	1		T239	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	14		T281	15		T270	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1642	1			T1	2		T8	1		T10	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	16		T144	1		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	12		T30	5		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	4		T148	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T2	12		T3	2		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T36	1		T26	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T310	13		T258	6		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T12	1		T210	1		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17664	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T242	1		T78	1		T363	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T248	1		T151	6		T98	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	12		T183	4		T151	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T25	17		T30	4		T146	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	4		T137	14		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T175	2		T92	6		T257	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T15	6		T183	9		T139	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T176	16		T251	4		T92	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T147	2		T175	6		T37	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	16		T137	4		T18	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	1		T30	21		T184	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T144	9		T242	15		T168	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T28	20		T270	16		T159	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	876	1			T8	10		T249	33		T186	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T144	14		T16	4		T199	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T4	18		T30	4		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	3		T241	1		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T146	9		T18	1		T198	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T26	14		T146	13		T243	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T258	5		T255	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T210	9		T246	7		T327	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T242	4		T102	1		T336	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T3	1		T142	14		T136	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T12	1		T263	9		T364	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T149	8		T362	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T102	1		T313	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T221	1		T151	1		T98	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T150	1		T242	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	1		T36	1		T25	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T4	13		T5	8		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	4		T145	1		T140	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T142	13		T136	1		T183	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T176	11		T92	14		T93	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	1		T15	9		T139	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	9		T142	12		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	1		T184	1		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	16		T41	15		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T28	14		T30	3		T136	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T144	1		T150	1		T215	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T2	16		T144	1		T141	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T30	5		T198	3		T281	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T16	5		T17	4		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1811	1			T1	2		T2	12		T3	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T36	1		T26	1		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T270	11		T258	5		T280	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T263	11		T165	2		T365	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T149	8		T362	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T102	1		T313	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T151	6		T98	2		T168	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T242	4		T151	8		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T25	17		T146	4		T149	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	12		T5	4		T137	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T30	4		T194	8		T175	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T183	9		T149	15		T178	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T176	16		T92	2		T45	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	6		T139	16		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T137	4		T251	4		T235	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	1		T184	10		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	16		T18	4		T247	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T28	20		T30	21		T271	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T144	9		T215	21		T217	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T144	14		T199	11		T175	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T30	4		T198	2		T252	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T16	4		T34	3		T241	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T4	18		T8	10		T249	33
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T26	14		T146	13		T152	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	1		T150	1		T248	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T4	13		T183	5		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T36	1		T25	18		T30	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	5		T136	1		T137	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T145	1		T175	3		T92	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	1		T142	1		T15	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	1		T176	17		T251	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T141	1		T240	1		T147	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	17		T142	1		T137	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T14	2		T30	22		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T41	1		T144	10		T239	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T28	21		T281	1		T270	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T1	2		T8	11		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	1		T144	15		T16	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T4	19		T30	5		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T17	3		T148	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T2	1		T3	2		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T36	1		T26	15		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T310	1		T258	6		T255	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T12	1		T210	10		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17801	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T242	5		T78	1		T363	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T98	4		T212	4		T321	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	12		T183	10		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T25	12		T30	3		T140	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T5	7		T263	4		T303	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T175	9		T92	8		T294	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T142	12		T15	4		T183	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	8		T176	10		T92	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T141	8		T240	12		T193	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	15		T142	11		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T30	2		T136	8		T16	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T41	14		T187	14		T168	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T28	13		T281	14		T270	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T10	17		T24	20		T143	41
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	15		T16	2		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T4	11		T30	4		T193	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	1		T152	10		T262	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T2	11		T142	13		T136	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T140	8		T141	13		T243	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T310	12		T258	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T268	11		T264	5		T165	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T149	7		T168	11		T304	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T363	10		T366	1		T313	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T3	1		T142	1		T136	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T12	1		T263	12		T364	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T149	9		T362	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T102	2		T313	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T221	1		T151	7		T98	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T150	1		T242	5		T151	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T3	1		T36	1		T25	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	13		T5	5		T137	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T30	5		T145	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T142	1		T136	1		T183	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T176	17		T92	3		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	1		T15	11		T139	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T142	1		T137	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	2		T184	11		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	17		T41	1		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T28	21		T30	22		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T144	10		T150	1		T215	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T2	1		T144	15		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T30	5		T198	3		T281	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T16	7		T17	3		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T1	2		T2	1		T3	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T36	1		T26	15		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T142	13		T136	13		T270	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T263	8		T311	5		T165	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T149	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T313	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T98	4		T168	11		T304	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T38	3		T98	4		T168	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T25	12		T149	2		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	12		T5	7		T183	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T30	3		T140	18		T175	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T142	12		T183	10		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T176	10		T92	13		T93	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T15	4		T139	11		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T5	8		T142	11		T140	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	2		T141	8		T240	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	15		T41	14		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T28	13		T30	2		T136	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T215	17		T217	24		T256	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	15		T141	14		T281	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T30	4		T198	2		T281	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T16	2		T17	1		T75	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T2	11		T4	11		T10	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T140	8		T141	13		T152	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15