Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23016

1

T1

2

T4

30

T5

9

auto[ADC_CTRL_FILTER_COND_OUT]

3878

1

T2

28

T3

3

T4

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21021

1

T3

2

T4

55

T5

9

auto[1]

5873

1

T1

2

T2

28

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	266	1			T150	1		T153	1		T215	19
values[0]	45	1			T262	3		T210	10		T309	24
values[1]	730	1			T14	2		T26	15		T144	10
values[2]	686	1			T25	30		T28	34		T141	9
values[3]	632	1			T13	1		T142	14		T140	9
values[4]	491	1			T3	1		T30	8		T136	23
values[5]	2837	1			T1	2		T3	1		T8	11
values[6]	642	1			T2	28		T4	25		T144	15
values[7]	683	1			T36	1		T30	24		T142	25
values[8]	1059	1			T3	1		T4	30		T36	1
values[9]	1091	1			T5	21		T13	32		T30	9
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	629	1			T14	2		T25	30		T26	15
values[1]	756	1			T28	34		T17	1		T239	1
values[2]	545	1			T13	1		T142	14		T140	9
values[3]	2697	1			T1	2		T3	2		T8	11
values[4]	676	1			T2	16		T4	25		T15	15
values[5]	621	1			T2	12		T144	15		T183	15
values[6]	809	1			T36	2		T30	24		T142	25
values[7]	888	1			T3	1		T4	30		T136	1
values[8]	1092	1			T5	21		T13	32		T30	9
values[9]	160	1			T40	1		T263	20		T235	17
minimum	18021	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T141	9		T147	1		T98	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	1		T25	13		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T28	14		T239	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T17	1		T174	1		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	1		T142	14		T140	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T193	24		T199	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T1	2		T8	1		T10	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	2		T36	1		T30	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	9		T140	19		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	16		T4	13		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T144	1		T183	11		T17	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	12		T16	5		T141	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	1		T30	3		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T36	1		T142	25		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T4	12		T137	1		T141	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	1		T136	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	9		T13	16		T30	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T5	8		T137	1		T183	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T40	1		T256	9		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T263	9		T235	1		T236	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17662	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T146	1		T271	1		T309	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T147	2		T98	6		T202	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	1		T25	17		T26	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T28	20		T92	6		T210	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T247	14		T270	11		T168	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T198	9		T242	4		T252	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T199	11		T151	6		T177	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T8	10		T249	33		T138	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T30	4		T149	6		T92	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T15	6		T248	1		T241	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	12		T19	5		T98	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T144	14		T183	4		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T16	4		T260	3		T96	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T30	21		T18	1		T175	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T139	16		T149	8		T175	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	18		T137	14		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T149	15		T243	11		T263	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	16		T30	4		T175	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	4		T137	4		T183	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T256	8		T283	11		T367	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T263	11		T235	16		T236	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	2		T15	1		T144	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T146	9		T271	12		T309	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T177	1		T70	1		T256	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T150	1		T153	1		T215	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T262	3		T210	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T309	12		T246	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T144	1		T145	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	1		T26	1		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	14		T141	9		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T25	13		T17	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	1		T142	14		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T193	24		T199	1		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T136	14		T138	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	1		T30	4		T136	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T1	2		T8	1		T10	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T36	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T144	1		T183	11		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T2	28		T4	13		T141	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T30	3		T17	4		T18	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T36	1		T142	25		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T4	12		T36	1		T141	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	1		T136	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	9		T13	16		T30	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T5	8		T137	1		T183	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T177	7		T256	8		T283	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T215	12		T263	11		T235	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T210	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T309	12		T246	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T144	9		T151	8		T98	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T14	1		T26	14		T184	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	20		T147	2		T92	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T25	17		T298	4		T259	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T198	9		T242	4		T252	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T199	11		T247	14		T151	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T138	5		T147	9		T18	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T30	4		T149	6		T92	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T8	10		T249	33		T15	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T19	5		T212	4		T337	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T144	14		T183	4		T20	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	12		T260	3		T96	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T30	21		T18	1		T217	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T139	16		T16	4		T175	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T4	18		T198	2		T175	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T149	23		T37	12		T243	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	16		T30	4		T137	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	4		T137	4		T183	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T141	1		T147	3		T98	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	2		T25	18		T26	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T28	21		T239	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T17	1		T174	1		T247	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	1		T142	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T193	2		T199	12		T151	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T1	2		T8	11		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	2		T36	1		T30	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	11		T140	1		T248	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	1		T4	13		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T144	15		T183	5		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	1		T16	7		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T36	1		T30	22		T18	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T36	1		T142	2		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T4	19		T137	15		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	1		T136	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T5	1		T13	17		T30	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T5	5		T137	5		T183	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T40	1		T256	9		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T263	12		T235	17		T236	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17829	1			T6	18		T7	17		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T146	10		T271	13		T309	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T141	8		T98	4		T155	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T25	12		T16	2		T98	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T28	13		T92	8		T154	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T270	10		T277	9		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T142	13		T140	8		T240	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T193	22		T19	3		T211	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T10	17		T24	20		T136	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T30	3		T136	8		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	4		T140	18		T176	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	15		T4	12		T19	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T183	10		T17	1		T75	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	11		T16	2		T141	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T30	2		T175	9		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T142	23		T139	11		T149	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	11		T141	13		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T149	11		T243	10		T263	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	8		T13	15		T30	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T5	7		T183	10		T240	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T256	8		T283	12		T338	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T263	8		T236	12		T189	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T262	14		T211	3		T273	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T309	11		T265	8		T338	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T177	8		T70	1		T256	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T150	1		T153	1		T215	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T262	1		T210	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T309	13		T246	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T144	10		T145	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T14	2		T26	15		T184	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T28	21		T141	1		T147	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	18		T17	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T142	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T193	2		T199	12		T247	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T136	1		T138	6		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	1		T30	5		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T1	2		T8	11		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	1		T36	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T144	15		T183	5		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	2		T4	13		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T30	22		T17	3		T18	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T36	1		T142	2		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T4	19		T36	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	1		T136	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	1		T13	17		T30	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T5	5		T137	5		T183	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T256	8		T333	11		T283	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T215	6		T263	8		T294	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T262	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T309	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T98	4		T262	12		T211	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	2		T98	4		T268	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T28	13		T141	8		T92	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	12		T277	9		T298	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T142	13		T140	8		T240	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T193	22		T270	10		T19	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T136	13		T18	2		T281	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T30	3		T136	8		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T10	17		T24	20		T15	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T19	7		T268	15		T282	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T183	10		T202	8		T339	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	26		T4	12		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T30	2		T17	1		T217	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T142	23		T139	11		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T4	11		T141	13		T198	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T149	18		T37	15		T243	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	8		T13	15		T30	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T5	7		T183	10		T240	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15