Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	1		T142	1		T15	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	2		T30	5		T137	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T136	2		T138	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	1		T137	1		T139	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	1		T144	15		T146	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T41	1		T146	14		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T1	2		T4	13		T8	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T140	1		T241	2		T93	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T142	1		T141	1		T194	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	1		T30	22		T138	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T3	1		T4	19		T30	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	1		T13	17		T25	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T17	3		T242	16		T251	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T141	1		T239	1		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	1		T183	5		T34	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T36	1		T142	1		T98	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T240	1		T18	3		T199	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T36	1		T137	5		T184	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T5	1		T96	11		T235	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T26	15		T271	13		T266	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T5	5		T6	18		T7	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T215	10		T78	1		T272	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	15		T142	13		T15	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T30	4		T149	7		T193	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T136	21		T141	13		T256	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T139	11		T176	10		T19	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T175	4		T38	3		T168	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T41	14		T240	12		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T4	12		T10	17		T24	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T140	18		T93	2		T250	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T142	12		T141	14		T92	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	11		T30	2		T140	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	11		T30	3		T140	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	15		T25	12		T28	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T17	1		T222	2		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T141	8		T193	17		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T183	10		T243	10		T262	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T142	11		T98	8		T154	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T240	9		T175	9		T277	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T93	8		T263	4		T22	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T5	8		T96	9		T278	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T266	1		T163	20		T274	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T5	7		T75	6		T279	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T215	11		T273	11		T79	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T18	3		T96	11		T235	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T271	13		T23	2		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	5		T36	1		T15	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	2		T30	5		T149	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	1		T142	1		T136	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T137	15		T139	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	1		T144	15		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T137	1		T146	14		T240	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T1	2		T4	13		T8	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	1		T149	7		T241	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T142	1		T141	1		T96	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T30	22		T138	6		T140	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	19		T30	5		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T3	1		T13	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	1		T17	3		T149	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T141	1		T150	1		T193	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T3	1		T183	5		T34	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T36	1		T239	1		T98	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T5	1		T240	1		T199	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T36	1		T26	15		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T96	9		T223	3		T280	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T23	1		T274	20		T275	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	7		T15	4		T183	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	4		T149	7		T193	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	15		T142	13		T136	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T139	11		T176	10		T261	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T141	13		T175	4		T168	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T240	12		T270	10		T19	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T4	12		T10	17		T24	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T41	14		T149	2		T93	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T142	12		T141	14		T96	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T30	2		T140	20		T37	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	11		T30	3		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T2	11		T13	15		T25	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T17	1		T149	11		T281	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T141	8		T193	17		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T183	10		T262	14		T217	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T98	8		T154	5		T282	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	8		T240	9		T175	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T142	11		T93	8		T263	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15