Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23467

1

T1

2

T3

2

T4

30

auto[ADC_CTRL_FILTER_COND_OUT]

3427

1

T2

28

T3

1

T4

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20998

1

T2

16

T3

2

T4

25

auto[1]

5896

1

T1

2

T2

12

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T283	22		T284	5		-	-
values[0]	43	1			T242	5		T285	2		T286	1
values[1]	545	1			T4	25		T30	9		T15	15
values[2]	834	1			T25	30		T30	24		T144	15
values[3]	703	1			T5	12		T30	8		T142	14
values[4]	679	1			T3	1		T4	30		T13	1
values[5]	778	1			T13	32		T142	12		T137	15
values[6]	842	1			T5	9		T36	1		T142	13
values[7]	689	1			T2	12		T36	1		T136	9
values[8]	2761	1			T1	2		T8	11		T10	18
values[9]	1261	1			T2	16		T3	2		T14	2
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	670	1			T4	25		T30	33		T15	15
values[1]	832	1			T25	30		T137	5		T138	7
values[2]	833	1			T3	1		T5	12		T13	1
values[3]	580	1			T4	30		T36	1		T28	34
values[4]	864	1			T13	32		T142	25		T137	15
values[5]	820	1			T5	9		T36	2		T240	13
values[6]	2859	1			T1	2		T2	12		T8	11
values[7]	616	1			T2	16		T3	1		T26	15
values[8]	918	1			T3	1		T14	2		T41	15
values[9]	149	1			T144	10		T16	9		T149	16
minimum	17753	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T15	9		T242	1		T210	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	13		T30	8		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T25	13		T137	1		T138	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T17	1		T239	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	1		T5	8		T30	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	1		T142	14		T136	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	12		T139	12		T168	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	1		T28	14		T141	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T13	16		T142	13		T183	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T142	12		T137	1		T141	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T36	2		T240	13		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	9		T199	1		T176	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T1	2		T8	1		T10	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	12		T12	1		T136	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	1		T184	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	16		T26	1		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T41	15		T137	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	1		T14	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T144	1		T16	5		T270	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T149	8		T271	1		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17600	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T15	6		T242	4		T210	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	12		T30	25		T144	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T25	17		T137	4		T138	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T96	10		T168	9		T287	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	4		T30	4		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	2		T147	9		T149	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T4	18		T139	16		T168	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T28	20		T263	5		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	16		T183	4		T146	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T137	14		T175	2		T34	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T241	1		T151	8		T270	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T176	27		T96	6		T217	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	850	1			T8	10		T249	33		T186	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T18	4		T151	6		T19	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T184	10		T146	9		T198	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T26	14		T288	25		T289	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T146	4		T147	2		T149	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T183	9		T198	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T144	9		T16	4		T270	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T149	8		T271	12		T178	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	2		T15	1		T16	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T283	11		T284	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T242	1		T285	1		T192	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T286	1		T290	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T15	9		T137	1		T140	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	13		T30	5		T254	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T25	13		T138	2		T140	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	3		T144	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	8		T30	4		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T142	14		T136	14		T141	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T4	12		T183	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	1		T36	1		T28	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	16		T139	12		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T142	12		T137	1		T141	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T36	1		T142	13		T240	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	9		T199	1		T175	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T36	1		T247	1		T291	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	12		T136	9		T18	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1595	1			T1	2		T8	1		T10	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	1		T218	1		T250	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T3	1		T41	15		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T2	16		T3	1		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T283	11		T284	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T242	4		T285	1		T192	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	6		T137	4		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	12		T30	4		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T25	17		T138	5		T175	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T30	21		T144	14		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	4		T30	4		T199	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T149	6		T251	4		T210	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T4	18		T183	4		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T28	20		T147	9		T292	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	16		T139	16		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T137	14		T263	5		T154	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T241	1		T151	8		T37	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T175	2		T34	3		T176	27
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T247	14		T270	16		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T18	4		T151	6		T19	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	866	1			T8	10		T249	33		T146	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T218	12		T250	13		T293	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T144	9		T184	10		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T14	1		T26	14		T183	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	11		T242	5		T210	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	13		T30	27		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T25	18		T137	5		T138	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	1		T239	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	1		T5	5		T30	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	1		T142	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	19		T139	17		T168	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T36	1		T28	21		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	17		T142	1		T183	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T142	1		T137	15		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T36	2		T240	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T199	1		T176	29
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T1	2		T8	11		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	1		T12	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	1		T184	11		T146	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	1		T26	15		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T41	1		T137	1		T146	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	1		T14	2		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T144	10		T16	7		T270	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T149	9		T271	13		T178	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17743	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T15	4		T294	2		T295	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	12		T30	6		T38	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T25	12		T140	10		T240	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T277	9		T19	3		T96	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	7		T30	3		T140	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	13		T136	13		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	11		T139	11		T168	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T28	13		T141	14		T281	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	15		T142	12		T183	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T142	11		T141	8		T175	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T240	12		T270	10		T219	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	8		T176	27		T96	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T10	17		T24	20		T143	41
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	11		T136	8		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T198	2		T260	7		T296	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T2	15		T288	11		T297	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T41	14		T149	11		T193	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T183	10		T268	15		T298	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T16	2		T270	10		T293	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T149	7		T23	1		T160	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T152	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T283	12		T284	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T242	5		T285	2		T192	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T286	1		T290	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T15	11		T137	5		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	13		T30	5		T254	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T25	18		T138	7		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T30	22		T144	15		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	5		T30	5		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T142	1		T136	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	1		T4	19		T183	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	1		T36	1		T28	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	17		T139	17		T146	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T142	1		T137	15		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T36	1		T142	1		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	1		T199	1		T175	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T36	1		T247	15		T291	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	1		T136	1		T18	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1178	1			T1	2		T8	11		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	1		T218	13		T250	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T3	1		T41	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T2	1		T3	1		T14	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	10		T284	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T192	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T290	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T15	4		T140	2		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	12		T30	4		T38	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T25	12		T140	18		T240	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T30	2		T16	2		T19	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	7		T30	3		T140	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T142	13		T136	13		T141	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	11		T183	10		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T28	13		T141	14		T281	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	15		T139	11		T175	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T142	11		T141	8		T263	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T142	12		T240	12		T281	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	8		T175	9		T176	27
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T270	10		T262	12		T215	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	11		T136	8		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T10	17		T24	20		T143	41
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T250	8		T293	4		T297	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T41	14		T16	2		T149	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	15		T183	10		T149	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15