Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26894

1

T1

2

T2

28

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23513

1

T1

2

T4

55

T5

9

auto[ADC_CTRL_FILTER_COND_OUT]

3381

1

T2

28

T3

3

T5

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20266

1

T2

28

T3

1

T5

12

auto[1]

6628

1

T1

2

T3

2

T4

55

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22912

1

T1

2

T2

28

T3

3

auto[1]

3982

1

T4

30

T5

4

T8

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	474	1			T11	6		T14	17		T25	5
values[0]	17	1			T137	5		T299	11		T300	1
values[1]	768	1			T3	2		T41	15		T136	9
values[2]	2759	1			T1	2		T8	11		T10	18
values[3]	612	1			T36	1		T137	15		T183	15
values[4]	708	1			T4	30		T5	9		T12	1
values[5]	741	1			T3	1		T4	25		T183	20
values[6]	790	1			T2	28		T13	33		T36	1
values[7]	782	1			T15	15		T136	1		T138	6
values[8]	851	1			T5	12		T14	2		T30	9
values[9]	1095	1			T25	30		T28	34		T30	24
minimum	17297	1			T6	18		T7	17		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1007	1			T3	2		T41	15		T136	9
values[1]	2695	1			T1	2		T8	11		T10	18
values[2]	534	1			T5	9		T12	1		T36	1
values[3]	821	1			T4	30		T30	8		T140	9
values[4]	803	1			T2	28		T3	1		T4	25
values[5]	727	1			T13	1		T26	15		T15	15
values[6]	815	1			T5	12		T14	2		T138	6
values[7]	788	1			T25	30		T30	9		T142	12
values[8]	779	1			T28	34		T30	24		T142	14
values[9]	193	1			T138	1		T239	1		T176	29
minimum	17732	1			T6	18		T7	17		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

4270

1

T2

26

T4

23

T5

15

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T41	15		T136	9		T240	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	2		T137	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T1	2		T8	1		T10	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T137	1		T146	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	9		T146	1		T193	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	1		T36	1		T183	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T4	12		T281	11		T270	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T30	4		T140	9		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T4	13		T13	16		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	28		T3	1		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	1		T149	12		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T26	1		T15	9		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T199	1		T221	1		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	8		T14	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T25	13		T30	5		T142	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T144	1		T184	1		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T28	14		T30	3		T142	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T136	14		T240	13		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T239	1		T210	1		T294	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T138	1		T176	18		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T175	6		T241	1		T270	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T137	4		T144	14		T149	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	814	1			T8	10		T249	33		T186	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T137	14		T146	13		T151	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T146	4		T198	2		T251	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T183	4		T16	2		T21	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	18		T270	11		T271	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T30	4		T198	9		T242	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	12		T13	16		T92	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T183	9		T151	8		T45	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T149	15		T98	8		T210	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T26	14		T15	6		T34	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T242	15		T288	9		T289	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	4		T14	1		T138	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T25	17		T30	4		T147	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T144	9		T184	10		T146	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T28	20		T30	21		T248	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T199	11		T175	3		T92	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T210	10		T23	1		T283	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T176	11		T279	12		T302	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	450	1			T11	6		T14	17		T25	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T240	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T299	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T137	1		T300	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T41	15		T136	9		T240	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	2		T144	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T1	2		T8	1		T10	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T146	1		T149	3		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T146	1		T147	1		T193	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T36	1		T137	1		T183	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	12		T5	9		T140	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T36	1		T30	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	13		T145	1		T168	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	1		T183	11		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	17		T141	9		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	28		T36	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T136	1		T149	12		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T15	9		T138	1		T139	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T30	5		T142	12		T17	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	8		T14	1		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T25	13		T28	14		T30	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T136	14		T144	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17154	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T303	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T137	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T175	6		T241	1		T270	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T144	14		T37	12		T217	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	834	1			T8	10		T249	33		T186	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T146	13		T149	6		T151	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	4		T147	9		T198	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T137	14		T183	4		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	18		T270	11		T98	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T30	4		T242	4		T243	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	12		T168	8		T177	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T183	9		T198	9		T45	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	16		T92	6		T98	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T26	14		T151	8		T152	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T149	15		T242	15		T177	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	6		T138	5		T139	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T30	4		T147	2		T194	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	4		T14	1		T184	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T25	17		T28	20		T30	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T144	9		T199	11		T175	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	2		T15	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T41	1		T136	1		T240	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	2		T137	5		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T1	2		T8	11		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T137	15		T146	14		T151	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	1		T146	5		T193	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T36	1		T183	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T4	19		T281	1		T270	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T30	5		T140	1		T198	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T4	13		T13	17		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	2		T3	1		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	1		T149	16		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T26	15		T15	11		T34	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T199	1		T221	1		T242	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T5	5		T14	2		T138	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T25	18		T30	5		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T144	10		T184	11		T146	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T28	21		T30	22		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T136	1		T240	1		T199	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T239	1		T210	11		T294	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T138	1		T176	12		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17732	1			T6	18		T7	17		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T41	14		T136	8		T240	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T149	2		T187	14		T37	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T10	17		T24	20		T142	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T304	3		T265	15		T264	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T5	8		T193	5		T198	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T183	10		T16	2		T141	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	11		T281	10		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T30	3		T140	8		T243	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T4	12		T13	15		T140	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	26		T183	10		T140	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T149	11		T98	8		T263	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T15	4		T152	10		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T281	6		T268	11		T305	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	7		T139	11		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T25	12		T30	4		T142	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	2		T260	7		T306	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T28	13		T30	2		T142	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T136	13		T240	12		T175	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T294	2		T23	1		T283	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T176	17		T279	9		T307	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	447	1			T11	6		T14	17		T25	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T240	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T137	5		T300	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T41	1		T136	1		T240	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	2		T144	15		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T1	2		T8	11		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T146	14		T149	7		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T146	5		T147	10		T193	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T36	1		T137	15		T183	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	19		T5	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	1		T36	1		T30	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T4	13		T145	1		T168	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	1		T183	10		T198	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T13	18		T141	1		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	2		T36	1		T26	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T136	1		T149	16		T221	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T15	11		T138	6		T139	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T30	5		T142	1		T17	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	5		T14	2		T184	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T25	18		T28	21		T30	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T136	1		T144	10		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17297	1			T6	18		T7	17		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T303	14		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T240	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T299	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T41	14		T136	8		T240	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T37	15		T217	7		T250	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T10	17		T24	20		T142	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T149	2		T187	14		T265	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T193	5		T198	2		T281	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T183	10		T16	2		T141	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	11		T5	8		T140	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	3		T140	10		T243	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T4	12		T168	15		T296	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T183	10		T305	21		T308	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	15		T141	8		T19	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	26		T152	10		T38	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T149	11		T281	6		T263	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	4		T139	11		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T30	4		T142	11		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	7		T18	2		T260	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T25	12		T28	13		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T136	13		T175	9		T281	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22624

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4270

1

T2

26

T4

23

T5

15